ASSIGNMENT#3

SESSION: FALL-19

SUBJECT: EEE 241 - DIGITAL LOGIC DESIGN

INSTRUCTOR: SIR BILAL QASIM

ISSUE DATE: 31/10/2019

DUE DATE: 06/10/2019

COMSATS UNIVERSITY ISLAMABAD (CUI)

You must show ALL steps for obtaining the solution. Just reporting the correct
answer, without showing work performed at each step will result in getting 0 points
for that problem.
Do your individual work. Copied work will be marked Zero.

Topic: Functions of Combinational Logic

Q1. Four people judge a competition. The vote of each is indicated by a 1 (pass) or 0
(fail) on an input wire. The four wires form the input of a logic circuit. The rules of the
competition allow one dissenting vote. If the vote is 2-2 (a tie), then the competition must
continue. The logic circuit is to have two outputs, x and y. If the vote is 4-0 or 3-1 to
pass, then x=y=1. If the vote is 4-0 or 3-1 to fail, then x=y=0. If the vote is 2-2, then x=1
and y=0. Show Karnaugh maps for outputs x and y.

Q2. Implement the following 4-input Boolean function using a single 8:1 Mux. Find the
solution with the fewest complemented inputs to the Mux.

F (A, B, C, D) = M (1, 3, 13, 14, 15).

Q3. A combinational circuit is defined by the following three Boolean functions.

F 1  ac  bc
F 2  (b  c)( a  c)
F 3   (0, 2, 4, 6, 7)

Design the circuit with a 3-to-8 decoder and three NOR gates. No inverter or any other
type of logic gates is allowed. Do NOT assume the complement of any Boolean variables
is available either.

Q4. Assume we have two source inputs A and B, and four outputs W, X, Y, Z. Selection
bits S2, S1, S0 will connect one of the sources to one of the outputs, as shown in the
abbreviated truth table below. Draw a circuit diagram to show how to implement this
device using multiplexers and decoders and as few additional gates as possible. You can
draw block symbols for muxes and decoders, but be sure to label inputs and outputs
clearly.

S2 S1 S0 W X Y Z
0 0 0 0 0 0 A
0 0 1 0 0 A 0
0 1 0 0 A 0 0
0 1 1 A 0 0 0
1 0 0 0 0 0 B
1 0 1 0 0 B 0
1 1 0 0 B 0 0
1 1 1 B 0 0 0
Q5. Consider the two functions that are in terms of the four variables a, b, c, d:
f = m (0, 1, 2, 6, 8, 10, 11, 12)
g = m (0, 1, 2, 6, 7, 8, 10, 11, 12, 13)

Where appropriate in the questions below, you may assume that the system variables are
available to your circuits in both complemented and uncomplemented forms.

(a) Draw Karnaugh maps and find minimal SOP and POS forms for each function.

(b) Using your answer to part (a), implement the circuit for the function f using only
2-input NAND gates (inverters are not available). Appropriately choose the SOP or
POS form in part (a) that yields the simplest circuit.

(c) Using your answer to part (a), implement the circuit for the function g using only
2-input NOR gates (inverters are not available). Appropriately choose the SOP or POS
form in part (a) that yields the simplest circuit.

(d) Design the circuit for the function f using 3-to-8 decoders and any additional
combinational gates that you may need. The decoders have enable inputs.

(e) Design the circuit for the function g using 4-to-1 multiplexers. No other
combinational gates are available.

Q6. Design a combinational circuit using a decoder and external OR gates that accepts
one 3-bit number (i.e. A2A1A0) and generates a 3-bit number output equal to its
complement (C2C1C0).

Ex1: A2A1A0 = 001 C2C1C0 = 110

Ex2: A2A1A0 = 101 C2C1C0 = 010

Hint: Firstly, construct a truth table with all the possible values A2A1A0, could take.
Then compute the corresponding C2C1C0 values. Express C2, C1, and C0 as a Sum of
minterms.

Q7. Design a combinational circuit that accepts three 1-bit numbers, X, Y, and Cin and
generates a 2-bit number CoutS equal to the sum of the input numbers. Implement this
circuit using two 4-to-1 line multiplexors and inverters ONLY.

Hint: Firstly, construct a truth table with all the possible values X, Y, and Cin could
take. Then compute the corresponding CoutS values. Assign to Cout the corresponding
connections for multiplexer 1. Assign to S the corresponding connections for
multiplexer 2.