Integrated-circuit digital

I-Requirements and features of a

logic family; RTL, DTL, and HTL devices
In this first part of a three-part article comparing the
major IC logic families, the emphasis is on three types:
resistor-transistor, diode-transistor, and high-threshold logic
Lane S. Garrett Motorola Semiconductor Products Inc.

The purpose of this article is to categorize the needs 2. Complement outputs

and desired features that a logic or system designer
should consider when selecting a family of digital in-
tegrated circuits. The various major digital IC fami-
lies are evaluated and compared with these needs in
view. The intended results are that the reader will gain
facility in IC technology, terminology, and usage in
various areas of application. Part 11 of this article will puts of gates or functions together to perform additional
cover transistor-transistor logic (TTL) devices. Part Ill
is devoted to emitter-coupled logic (ECL) and metal
oxide semiconductor (MOS) devices.
Each user of digital logic has different needs, which
vary in importance with each design and application.
The eight major requirements and desired features of a
logic family are as follows:
1. Logic flexibility
2. Speed
3. Availability of complex functions
4. High noise immunity
5. Wide operating-temperature range
6. Low power dissipation
7. Lack of generated noise
8. Low cost
In following sections, these needs will be examined
the
individually.
flxiilt
Logic febltyLogic flexibility can be summed up as the capability
Logic flexibility is a measure of the capability and
versatiLity or the amount of work or variety of uses
that can be obtained from a logic family; in other words,
it is a measure of the utility of a logic family in meeting
various system needs.
Logic flexibility can be compared between the families
on the basis of several factors, as follows:
1. Wired logic capabilities
46
3. Line-driving capability
4. Indicator driving
5. I/O interfacing
6. Driving other logic forms
7. Multiple gates
Wired logic refers to the capability of tying the out-
logic without extra hardware or components. Examples
of two types of output circuitry common in integrated
circuits are illustrated in Figs. 1 and 2. Note how botb
the positive logic AND and OR functions can be obtained,
without the use of additional gates, simply by tying the
outputs of the gates together.
Frequently, both a variable and its complement are
required in a logic system. If the family of logic being
used has gates with complement outputs, the need for
inverters can be avoided. Gates with complementary
outputs perform the OR/NOR and AND/NAND functions,
as shown symbolically in Fig. 3.
Also included in the category of logic flexibility is
the need for driving nonstandard loads, such as long
signal lines, lamps, and indicator tubes.
In the design of a logic system, the gate count is mini-
mized if AND, NAND, OR, NOR, and "exclusive OR" gates
(Fig. 4) are all available in the family. This is not always
the case; but the more types of gate included, the easier
the design implementation.
of the family to meet the needs of the logic and system
designer and to provide a wide selection of building
blocks.
Speed
An increasingly important requirement in many areas
is for getting more things done in the minimum amount
of time. The simplest way to increase machine capability
IEEE spectrum OCTOBER 1970

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 logic families
is to speed up the logic and information access rates.
Moreover, to accomplish a given task in a given time it
may be possible to go to a high-speed serial implementa-
tion instead of a parallel design with a larger number of
functions. This approach obviously can save money
through the use of fewer gates.
The most important measures of speed are gate propa-
gation delay and pair delay. The latter may be defined
as the propagation delay through two successive invert-
ing gates. Pair delay averages out propagation delays
for positive- and negative-going output transitions, which
may be unequal. Another important factor is the maxi-
mum shift frequency of flip-flops, which may be signifi-
cant in determining the maximum cycle time of a system.
Complex functions
Complex functions are becoming more and more Output
common as the sophistication of designs increases. A of first
complex function may be described as a grouping of basic gste
gates for performing a relatively high level of integration, A
usually involving more than 12 but less than 100 gates.
As complexity increases, the number of input/output
pins also increases-but usually at a decreasing rate.
Wired-logic
-- _- { output

Output of
FIGURE 1. Example of "implied AND" or "o AND" wired seond
logic (frequently but improperly called "wired OR.")
The output is high (most positive level) if transistors
A and B are off. Conversely, we may say that the output
is low if A or B is on (negative logic). l

IL
Positive logic High level is true 1"
Negative logic, Low level is true - O

of first 7FIGURE 2. Example of "implied OR" wired logic. The

gate output is high if transistor A or B has a high output.
Conversely, the output is low if A and B outputs are both
low (negative logic).

O0R -cAND
.A Wired-logic - O
output
, {_. _-NOR ,--v NAND

l ~~~~~~IGU
RE 3. Complementary outputs. Standard symbols for
< > | ~~~~~~OR/NORk and AND/NAND gates.
Output of o l
secondtI FIGURE 4. Standard symbols for various gate types.

+ ,~ ~ ~ j AND OIIIo NAND

.----~~~~~ OR? NOR ExciusiveOR

Garrett-integratedl-circuit dicital logic fam]lilies 47

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 ~ ~ Do=-O<
Gate-to-pin ratios that normally increase with complexity data by a clock period and also are useful in forming
give the benefit of decreasing assembly costs per gate shift registers. A typical quad-D block diagram is illus-
while also increasing the reliability per gate. trated in Fig. 7.
At times, multiple groupings of a common logic func- Counters also may be classified as complex functions.
tion are available in the same package. A better under- They are groupings of flip-flops and gates, which perform
standing of the term "complex function" is obtained by such functions as "divide by 10," "divide by 16," or
noting several examples: "divide by N." Counters may also be able to count up
A parity tree is a grouping of gates designed to perform or down according to logic-control inputs. Three exam-
the "exclusive OR" function; the exclusive OR'S are then ples are shown in Fig. 8.
grouped to form a logic tree. A typical example is the Decoders, such as the one shown in Fig. 9, may hold
eight-bit parity tree, which checks eight different binary one of ten output lines at a low level based upon the
bits at a time to see whether the sum is odd or even. states of four input control lines. The channel or data
(Refer to Fig. 5, where an eight-bit parity tree is shown selectors comprise another group of complex functions.
in logic-notation form.) A quad latch (Fig. 6) is a four-bit A typical device is an eight-channel data selector that
storage element, frequently used as buffer storage or picks one of eight input lines and passes its information
temporary memory. Each of the four elements employs on to the output. The input selected is determined by the
several gates. A "quad D" is a complex function con- states of the three input-control lines (see Fig. 10).
taining four D-type flip-flops, which logically delay Complex functions, which are rapidly increasing in
types and numbers in the major logic families, represent a
second generation of complexity in the integrated-circuit
art and often use the latest developments in technology,
such as double-layer metalization. They are frequently
Bo 0 \ 7 the key to minimizing system size, cost, and parts count.
0 ! /A, Many IC families are chosen on the basis of the complex
B1 /,.' < \1 functions available.
B2 '-<a 1 High noise immunity
B3 0 Odd In order to prevent the occurrence of false logic signals
parity in a system, high immunity to noise is desired. Erroneous
° \\ } .t Even signals may be caused by switching transients, excessive
parity coupling between signal leads, and external sources such
v
B5 L \
as relays, circuit breakers, and powerline transients. In
general, the higher the noise immunity of the circuits, the
B6 X_ - =
O 0 false
B7O
CD---

1 < 1 true
FIGURE 7. Block diagram of quad-D function.
FIGURE 5. Eight-bit parity tree. The output of each exclu-
sive OR is true whenever the inputs are different. The
odd output is true whenever the sum of Bo through B7 Qo
is odd. The even output is true when the sum is even. Co

FIGURE 6. Block diagram of quad latch.

D ~ ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~~~D

0 ~ ~ ~~ ~ ~ ~ ~ ~ ~ ~~~~~~0
D Q clear

Dlock Enable Cn,o la

48
~~~~~~~~~~~~~~~~~~~~~~~~~~~IEEE
spectrum OCTOBER 1970

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 81 Ql S2Q2 S4 Q4 S8 Q8 SI QlS2 Q2 S4Q4 SSQ8 S1 Ql S2Q2 S4 Q4 S8Q8

Enable
CokCokClock Up-down

Reset Reset Reset

+10 counter 16 counter Up -down decade counter

FIGURE 8. Three basic counters.

fewer the precautions required to prevent false logic

FIGURE 9. Fou r-to-ten-tine decoder. signals. This becomes an important advantage in those
areas, such as in small industrial logic control systems,
cA ~~~~~~~~~~that
are subject to high noise levels. Voltage-noise im-
munity, or noise margin, is normally specified in terms
__ __t_____ ~ ~~~~~~~of millivolts or volts-more specifically, tothea amount
voltage that can be added algebraically
of
worst-case
output level before a worst-case gate tied to that output
will begin to switch. Noise margins for two gates are
illustrated in Fig. 1 1, in which
-0 0 VoH(min,)
= minimum specified output voltage when the
gate is in the "high" state
VOL(max) = maximum specified output voltage when the
1 ~~~~~gate
is in the "low" state
VIH(min) = minimum specified high-level input voltage at

FIGURE 10. Eight-channel data selector.

3 D
D3
D0
05
06

s
S2
S L~
3~ ~~2
7~~~~~~i~ 30

8~ ~ ~~~Si8 30

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 which the gate output voltage will still Low cost
meet specified limits The last consideration, and often the most important
VIL(mlx) = maximum specified low-level input voltage at one, is the cost of a given logic family. The first approxi-
which the gate output voltage will still mate cost comparison can be obtained by pricing a
meet specified limits common function such as a dual four-input or quad
two-input gate. This is only approximate at best. Among
The high-level and low-level noise margins are, respec- otecstoniraosaepckgcutfragvn
tively,[VOHr(min) - VIH(miii)] and [VIL(max) --VOL(ax)'
tivey, [VoH(-,,i,) -VIH(i.)]and[IL(mx) VOL(max)l. other cost considerations are package count for a given
system speed, layout and shielding costs, and interface
Wide operating-temperature range costs. An effective cost comparison involves a paper de-
A wide operating-temperature range is always desired sign of a system with two or more different families. If
and is often a design requirement. For commercial and the system employs a number of circuits, it is preferable to
obtain factory quotes rather than rely on book prices.
industrial needs, temperatures usually range from 0C or
-30°C to 55, 70, or 75°C. The military has an almost Basic design problems
universal requirement for operability from -55°C to The question arises, why not design a family that best
+15 °C. Inos
+ 125 Inmost
. cases, aa loiln
caes spcfido
logic line specifed for -55 0C tto
+125 C will exhibit better characteristics at room ambi- .5 meets these needs and then mass produce it and drive
these nees cand tednemassrce ituan el
meets down?
ent conditions than.. a line. specified
. . re- ~~~~~~~~costs This cannot be done, since unfortunately
for commercial there is no universal logic family that does a good job of
quirements; that is, fanout, noise immunity, and toler- meeting all of the previously stated needs. Silicon tech-
ance to power supply variations are usually better, since nology, though better understood and studied than any
the circuits must still be within specifications even when
the inherent degradation due to temperature extremes other solid-state technology, still has limitations. These
occurs. The advantages of wide temperature specification limitations, along with the inherent restrictions on circuit
design, allow only some of the desired parameters to
are often offset by increased IC cost.
be optimized. First, the silicon wafers used in processing
Low power dissipation integrated circuits have faults in the crystalline structure.
Logi wit lowpowe Logic disipaion s deiredin
with low lrge
power dissipao iAlthough
number, modern technology has greatly reduced their
these faults are still a large contributing factor
systems because it lowers cooling costs and power supply tnumber, ofabadsde or circi ontabgivn
to the number of bad die or circuits on a given wafero
and distribution
and istrbutin costs,
csts,therby reducing mechanical
thereby rducng mchancal slcn htrss,mtlzto,adpoorpi wafer of
design problems. In an airborne or satellite application,
power dissipatn my bmasks
themselves are' all sources of frequent errors and
bcueopower-dissipatonumaycbe
because theimostaitic.Alt
of power-source limitations. Althoughpha power er faults that contribute to the number of bad spots on a
wfr
dissipation may not be a large financial factor in the eco- wafer.
nomic design of a system, it must certainly be considered The larger the size of a given die, the higher is the
along with other factors, suchaslogicprobability that it will incorporate a fault resulting in a
complexity andalong with othe
packing factors, suchasloi Abad circuit. Integrated-circuit bipolar die larger than
density continue to . increase,
power dissipation will decrease on a per-gatepowr basis. about 80 mils (2 mm) on a side exhibit rapidly increasing
This is dictated by heat-dissipation restrictions arising
d
n. costs, due to reduced yields. The fact that a lot fewer large
from system design and maximum allowable semicon- die can fit on a wafer also increases expense. Thus, the
ductor junction temperatures. complexity that can be obtained on a single chip is limited
by simple economics. Silicon IC technology has limits in
Minimum noise generation absolute values of resistivity obtainable, maximum vol-
The lack of generated noise is an important require- tage breakdowns, parasitic capacitance per given area,
ment. All power-supply leads in a system must be by-
require-current density,.
and
a even operating temperatures.
passed. The amount of capacitive bypassing and methods In addition, there are several major restrictions on
of power supply and ground distribution depend heavily circuit design. For example, to design a given function
upon the form of logic utilized. Supply distribution is less requires a certain number of components, which in turn
expensive if the logic family generates minimal noise. demand a given chip area. The best circuit design elimi-
Also, maximum line lengths in the back plane and wiring nates only redundant components, and further reducing
of the computer are a function of crosstalk generated by components usually results in performance degradation,
the logic when it switches states. The ideal would be a but this may be required due to die-size limitations.
logic family that draws constant current in either a logic Good circuit design can alleviate some processing
0 or 1 state and does not change supply drain current problems, such as increasing allowable transistor ,B
when switching states. Also, signal line currents would variations or permitting larger changes in resistor values,
approach 0 with very slow rise and fall times. but unfortunately this usually comes at the expense of
more components. Moreover, bipolar design has a dis-
advantage in that current can effectively pass through
the transistors in only one direction. In other words a
transistor does not act as a conventional switch, which
FIGURE 11. Noise margins for two gates. passes current in either direction. Metal oxide semi-
conductor devices on the other hand, have the advantage
VOH (min) a =High-level noise immunity Output remains that once the device is turned on, current will pass in
=~ ~~~-
>:_<
__jb VViH (mli.)
-
oupu or(mn
output~~~~~remains eitherhigh
have direction. The problem
"on" impedanees, here afew
usually is that MOS devices
thousand ohms,
belo VOLX maxlcseev and impedance can be reduced only
Maximum tanout Low-level noise immunity
Wr-csdevice O(a)v if the device is made
b= large, thereby causing an area problem.

50 IEEE spectrum OCTOBER 1970

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 Another limitation on circuit design is the interrela- Vcc 3.6v
tionship of parameters. As transistor ,3 is increased, col-
lector breakdown voltage decreases, and the storage 640
time of the device also increases. High-speed parameters
require low circuit impedances, small devices, and narrow Output
metalization, which in turn tends to be incompatible / -
with the high currents that are required by the low-
impedance circuitry. It is obvious that good circuit design
involves extensive juggling of parameters. Different design 1
parameters have been emphasized in each of the digital 450 450 450 450
logic families. It will be seen that each logic family is 1 1
geared to its own particular market, meeting a specific set
of needs. Inputs: A B C D
Most of the semiconductor digital efforts are centered FIGURE 12. Four-input RTL gate.
in seven major categories, each with its own inherent
advantages and disadvantages. Let's look at each of the
seven major categories briefly before going into detail FIGURE 13. Level table for four-input RTL gate.
on each individual category. The first three of these D C B A Out.
categories will be discussed in this month's installment. D C B A
1. Resistor-transistor logic (RTL) results in the small- L L L L H
est die size (minimum space on a silicon wafer) for L L L H L
standard bipolar functions. It is easy to process and has L L H L L
low to medium power dissipation. RTL is known pri- L L H H L
marily for its economy.
2. Modified diode-transistor logic (DTL) is low in L H L L L
cost, has logic familar to most designers, is available L H L H L
from many sources, and can be used for most general- L H H L L
purpose designs.
3. High-threshold logic (HTL) is designed for noise L H H H L
immunity and finds application in industrial environ- H L L L L
ments and locations likely to have high electrical noise H L L H L
levels. It is noted for its ability to interface easily with
discrete devices and electromechanical components. H L H L L
4. Transistor-transistor logic (TTL) has characteristics H L H H L
that are similar to DTL, and is noted for many complex
functions and the highest available speed of any saturated H H L L L
logic. Moreover, many sources are available with an H H L H L
excellent rate of complex-function introductions. H H H L L
5. Emitter-coupled logic (ECL) is known for perform- H H H H L
ance and logic flexibility. It has the highest speed of any
of the logic forms.
6. Metal oxide semiconductor (MOS) devices are noted
for small die and large complex repetitive circuits, such
as memories and shift registers. Power dissipation is low saturated logic families will be studied in order of their
to moderate, with low cost per gate. comuplexity, followed by ECL, MOS, and CMOS logic.
7. Complementary metal oxide semiconductor (CMOS)
devices employ both p- and n-channel MOS components RTL
and are known for very low power dissipation with Resistor-transistor logic is well named, since it con-
moderate delay times. tains resistors and transistors exclusively. The schematic
The characteristics of a family of digital ICs are set diagram of a four-input RTL gate (Fig. 12) and its level
primarily by the design of the basic gate. A simple four- table (Fig. 13) illustrate basic gate operation. The gate
input gate will be used as the common dominator for mlay be symbolized as a four-input NOR (positive logic)
comparisons between families. Input, transfer, and output or a four-input NAND (negative logic), as shown in Fig.
characteristic curves are essential in the understanding 14. In Fig. 12, it can be seen that if input A goes to a
of device parameters and will be illustrated. Gates will high level, current will flow through the 450-ohm input
be discussed using MIL-STD-806B conventions. A resistor into the base of the first transistor, turning it on.
high level (H) represents the most positive or least nega- The input voltage is then the sum of the base-emitter
tive logic level, whereas L represents the most negative diode drop (about 0.75 volt) and the drop across the
logic level. A high- and low-level table (as opposed to a input resistor. Note that if any one of the inputs, or
truth table) will be shown for the various gates. Gates even if all inputs, go to a high level, current will flow from
are named for their positive logic function; that is, a V< through the 640-ohm resistor, resulting in a low-
high level is-taken as true. The positive logic equation level output. Gain of the transistors is high, giving an
generated by the gate is shown along with the equivalent output (V<at) that is usually about 0.1 volt. The circuit
or "dual" negative logic equation; the latter is generated performs the NOR function, since if one or more inputs
by calling the low entries in the level table true. The are high the output is not high.

Garrett-Inategr-ated-circuit digital logic families 51

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 A unique situltion occurs when (all inputs are at a low
level. Each of the transistors is turned olf, and therefore
the 640-ohm pull-up resistor is allowed to bring the
output, and associated capacitance, to a relatively high
voltage level. Thus, using negative logic notation, the
circuit performs the NANI) fuLnction; that is. when and
only when a//inputsare low the outpit is not low.
Figure 15 shows how the outputs of two gates would
function when tied together. Assuming that each of the
transistors has the capability of sinking the current
through parallel pull-up resistors, the output node will
be low if one or more of the transistors are turned on. The
output will be high only when both transistors are otf.
This generates the positive logic AND functioni simply by
tying outputs together. This connection is represented
by the dashed ANI) gate drawn around the tie point to
show that the function is "implied." This connection is
sometimes improperly called the "wired OR." but should
be called the "iimplied AND." Note that the resultint
function is the AND of the two functions generated by
each gate. For example, if
=__________
- -
f; = A + B + C and f' = D + E
we would have
Output (J,)(/.) = (,1 + B + (C)(D 1- 1I)
or
Output (. IBC)(DE) = .IBCDE
= T
= A + B + C + D + E
by the use of DeMorgan's rule. It is seen that we ha\e
eircctively expanded the inputs of the RTL gate. This
limits the usefulness of the -implied ANiD" capability of
RTL except with some of the more advanced functions.
To provide a better understanding of the circuit.
the input, transfer, and output characteristics arc
shown in Figs. 16 19. From the input characteristics
(Fig. 16) it can be seen that the RTL gate starts to turn
on and draw current when the input voltage reaches one
diode voltage drop. RTL transistors are designed with
fairly high 3. and since the input resistor is fairly low in
value, a slight increase in input voltage above a diode
drop is sutlicient to turn the pertinent transistor on com-
pletely. This is observed in Fig. 17, which shows the
transfer characteristics for a ftanout of' I; that is, the
RTLoutput is supplying current to only one other RTL
input. The maximuim, typical, and minimum curves
illustrate the normal distribution of devices caused by
processing variations. Note that about 150 mV of
change in the input voltage is suflicient to cause the
output to switch completely. Figure 18 shows the transfer
characteristics for a maximuim RTL fanout of 5. Note
how the high level is much more negative due to the
loading of the five inputs. Figure 19 illustrates the high-
level output characteristics in the region of RTL input
voltages. The slope of the curve is simply the measure
of the pull-up resistor value (640 ohms).
Figure 2(0 illustrates the equivalent circuit and curve
for the gate output voltage. (Note, however, that the
Fig. 20 curve is based on a V,(c value of 3.6 volts, whereas
Figs. 16 -19 are based on a V,{( of 3.0 volts.) At a fanout
of 5 the curve becomes flat, giving a relatively constant
voltage drop across the 640-ohm resistor. There is now
about 3.9 mA available to be divided among the various
gate inputs. The input resistors help the various gate
inputs to share the input current evenly; otherwise a
low threshold gate would "hog" more than its share of
input current. Due to temperature variation, dilferencec
in absolute resistor values, and variations in d and input
640
f
- A>
Output
- f (f2)
l
640
--.- B
/

FIGURE 15. Gate operation with two outputs tied together.

FIGURE 14. Symbolic representations of Fig. 12 gate.
A FIGURE 16. RTL input characteristics. V., = 3.0 volts,
B
c
o H
T, =25°.
C _- *0= AtB+C - D

D _ b|

or
BO =ABC
A
B o-

1;=ABCD.:
D

52~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I II SpcCIAILuill OCI 11ii 197)

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 thresholds, RTL is limited to a worst-case fanout of 5.
Note that as fanout increases, the base overdrive de-
creases, which reduces energy noise immunity.
High voltage-noise immunity for 3-volt operation and
maximum fanout can be obtained from Fig. 18. It takes
a maximum input of 0.80 volt or less to cause a low-d
transistor to switch the output below a maximum
threshold. The worst output voltage is 0.90 volt at a fan-
out of 5. The result is a voltage-noise margin of greater
than 100 mV at 250C. Energy-noise immunity is better
than anticipated due to the low output impedance.
Low-level noise immunity is better because of the greater
dilference between the saturation voltage and the lowest
threshold. As temperature increases, the gate threshold
decreases Pt about 1.5 mV/°C, resulting in more constant
thresholds than found in DTL and TTL designs. Transfer
characteristics at a fanout of I and 5 versus temperature
are shown in Figs. 21(A) and (B). Note that the thresh-
olds and the high-level output decrease with increasing
temperature. This efTect is attributable to diffused resistor
values that increase with temperature and the "clamping"
effect of the gate inputs.
The basic RTL gate is easily fabricated into flip-flops
and complex functions. In fact, RTL design results in
the simplest and smallest-area bipolar method of ob-
taining complex functions. If many RTL gates are
fabricated on the same chip, all transistors will have the
same thresholds. Thus the "current hogging" problem
mentioned previously is eliminated. For this reason,
direct-coupled logic (RTL without input resistors) shows
excellent promise for LSI arrays. If comparable device
and processing technology are employed, the speed-
power product of RTL is actually better than that of
TTL-a factor that again shows promise for LSI func-
tions. In addition, the resistor values of the basic gate
(Fig. 12) are easily increased to reduce power dissipation.
An RTL version called milliwatt RTL has been used
extensively in low-power applications. Characteristics
are similar to and compatible with standard RTL at one
fifth the power dissipation.
Like any other family, RTL has its advantages, dis-
advantages, and areas of preferable application. These
are listed as follows for easy comparison with the other
flamilies:
RTL clisadCCantages
I. Low voltage-noise immunity

IMUIfSIii
~~~~~~~~ 10 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~~~~~~~~
~
2.0 ~ ~ ~ ~ 0

4 0~~~~~~~~~~~~~

Il .4 ul c .olt, 8

FIGURE 17. RTL transfer characteristics. V( t = 3.0 volts, FIGURE 20. Output voltage vs. fanout and equivalent cir-
0
TA= 25°C, fanout =1. cuit for a typical RTL device. (n = fanout.)
5.0 19)* fRT oupu cactrsics V
,fXX f f f f f f f f ~~~FIGUE 3.0 vok=0g
fl}ts,
lf d0;

i 0 0
42 4 0= 4 4.6

4 2 ) i.: 2 d _ 1.O to : <§f

d~~~~~~.4
4 4, 4

0 0.2 0.4 0.6 0.8 1. 2 3 4

Input voltage Fanout

GTAr2ct5 fInotut=citod-circuit
dil ,tycRTeiOgif fmI=ianus 53

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 -o -
0

4.,~~~~~~~~~~~~~~~~~~0
0
L I C ~E~~~~~~~~~~~0
I3 I
FIGURE 21. Modified RTL l
for three different tempera-
FanoutA-Fanout
tures.
MV/div.
= 1. B-
= 5. Scales: 200
l-
_ ---
Input voltage A B Input voltage

2. Relatively low fanout 10. Military and aerospace systems (pertains primarily
to R-1 3, a high-reliability specially specified form
Advantages of RTL)
1. Very low cost
2. Ease of design and manufacture DTL
3. Ease of use in system designs The schematic diagram shown in Fig. 22 represents
4. Very good speed-power product the first form of integrated diode-transistor logic and is a
5. Wide family of devices available. AND, OR, NAND, carryover from discrete design, where transistors were ex-
NOR, exclusive OR, exclusive NOR, flip-flops, and pensive compared with diodes. Circuit operation is rather
complex functions are now being manufactured simple. If one or more of the inputs are brought to ground
6. Smallest die size for a given amount of bipolar or a low level, current through the 2-kQ input resistor
circuitry will be shunted to ground, thereby eliminating base drive
7. Excellent promise for future bipolar LSI from the output transistor. Since this method keeps the
8. Ease of interface with discrete components transistor turned off, the output is maintained at a high
9. Relatively low noise generation level. A unique input condition occurs when all the
10. Capability of tying most devices together to per- inputs are high. Current will then flow through the 2-kQ
form the "implied AND" function input resistor and the two standoff diodes into the base
of the output transistor, turning it on. The saturation
Areas of alpplication voltage of the output is low-normally 0.2 volt.
1. Low-cost systems The X input simply stands for "expander," where
2. Counters additional diodes may be added to increase fan-in.
3. Instrumentation The 20-kQ pull-down resistor provides a discharge path
4. Small- to medium-size computers for stored charge in the output transistor, thus speeding
5. Medical electronics up the turn-off time of the transistor. The pull-down
6. Data sets and computer peripherals
7. Printers
8. Calculators
9. Systems that are intermixed with discrete transis-
tors FIGURE 23. Modified DTL gate design. For 6-ko resistor,
power dissipation = 8 mW, fanout = 8, propagation delay
= 30 ns, frequency = 12 MHz. For 2-kQ resistor, power
dissipation = 12 mW, fanout = 7, propagation delay =
25 ns, frequency =20 MHz.
FIGURE 22. Basic DTL gate design. Power dissipation =
10 mW, fanout = 4, propagation delay = 10 ns, 10-MHz 5- v
flip-flops.
1.6k

or

.2k 2.150kX 6

A 5 4 2JA1I
Oltput ^ _ ~~~~~~~~~~~~~~~~~~~~Output

X ~~~~~~~~-
2.0OV
54 IEEE spectrum OCTOBER 1970

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 A O
B
c O- ABCD 6k
or
D O y L 2k
or
A __
tfi
B
C O 4 = A+B+C+D

D
FIGURE 24. Modified DTL positive and negative logic - V Output
symbols. L -f (f)(f2)
6k
FIGURE 25. Modified DTL level table. or
2k
D C B A Out.
L L L L H 2

L L L H H
L L H L H
L L H H H
L H L L H FIGURE 26. DTL gate operation
L H L H H with two outputs tied together.
L H H L H
L H1 H H H
H L L L H reason the additional transistor is often referred to as a
H L L H H / saver. Thus the circuit modification provides a much
better ratio of base-drive current to input current. This
Fl L H L H improvement allows the fanout to be doubled and also
H L H H H improves testing yields.
H H L L H
A 5-kQ pull-down resistor, instead of the 20-kQ value,
takes up less area on the IC chip while still providing
H H L H H similar pull-down current. An important advantage to
H H H L H the user is that only one power supply is now required.
The output pull-up resistor can be either 2 kQ or 6 kQ
H H H H L for a convenient speed-power tradeoff. Figures 24 and
25 give the positive and negative logic symbols and a
level table, to describe both gate designs from a logic
point of view.
resistor also helps to keep the transistor turned off for Like RTL outputs, DTL outputs may be tied together
short positive-going input transients, thus aiding noise to perform additional logic through the "implied AND"
immunity. connection, which is illustrated in Fig. 26, with an exam-
The basic DTL gate design has been modified to lend ple in Fig. 27. The implied AND permits both NAND
itself more easily to IC processing and also to enhance and AND logic with DTL, which results in more flexibility
performance characteristics. This design, shown in Fig. than was present with RTL. Tying RTL NOR outputs
23, is called modified DTL. The design has greatly in- together effectively expands the inputs.
creased functionality and is largely responsible for the Although DTL input impedance is very high for a high-
wide acceptance of DTL. The input resistor has been level input (a reverse-biased diode), it is essentially the
split into two parts in the modified design. Typical input value of the input resistor for a low level. Input impedance
current drawn through an input diode is slightly more changes at the threshold level, which is two diode voltage
than 1 mA for the modified circuit and about 1.5 mA for drops above ground. Output impedance is 6 kQ or 2 kQ
the older circuit. On the other hand, the available base for a high output level and Rsat for a low level. Since the
drive for the output transistor is increased in the modified input characteristics and current-sinking capabilities of
circuit. DTL and TTL are very similar, their discussion will be
The input transistor acts as an emitter follower with postponed to the section devoted to TTL, which appears
collector current limited only by the 1 .6-kQ2 resistor. in Part II of this article.
Base drive in the modified circuit is approximately 1.7 mA Transfer characteristics for a typical DTL gate are
while only about 0.9 mA in the older circuit. Since the shown in Fig. 28. Note that as the input voltage is in-
modified circuit provides more base drive for the output creased from a low level, the high-level output will start
transistor (which, in turn, is required to sink a smaller to change at an input voltage of about 1.3 volts. At an
current from the gates it may be driving), the minimum input of 1.7 volts the output has completely switched to a
allowable A3 of the output transistors is lowered. For this low level. Noise immunity, from a voltage point of view,

Garrett Integrated-circuit digital logic families 55

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 is easily specified from the transfer characteristics. mine the specified voltage noise margin of the DTL circuit
VIL(max), the maximum input low-level voltage, and (930 series type).
VIH(min), the minimum input high-level voltage, are the Since the threshold voltage is equivalent to two diode
test voltages at which the worst-case output voltage voltage drops, changes will occur with temperature.
levels are measured. With these test inputs, VoH(min) and Threshold decreases with increasing temperature by
VOL(max), the minimum and maximum low-level output about 3 mV/°C. The resulting changes in worst-case
voltages, respectively, are obtained. These points deter- low-level noise immunity NIL and high-level noise
immunity NIH are as follows:
25°C (830 series)
VIL(max) = I.IOV VOH(min) = 2.60 V
VOL(.ax) = -0 . 45 V VH(min) = 1 .90 V
A NIL = 0.65V NIH 0.70V
B 75°C (830 series)

/ (AB) (AB)= (A+ B) (A + B) =AB + BA VIL(max) = 0.95 V VOH(min) = 2.50 V

A3 =AB VOL(mrax) = -0. 50 V VIH(min) = -1.80 V
NIL = 0.45 V NIH= 0.70 V
B / AB 125°C (930 series)

FIGURE 27. "Implied AND" example. VIL(max) = 0.80 V VOH(min) = 2.50 V

VOL(max) = -0 . 45 V VIH(min) = -2.00 V
NIL = 0.35 V NIH= 0.50V
FIGURE 28. Modified DTL transfer characteristic (25TC). Note how the noise immunity decreases with increasing
temperature.
5.0 DTL has many advantages and is used widely in the
industry. The various disadvantages, advantages, and
areas of application are as follows:
4.0
DTL disadvantages
| 3.0 1. Low noise immunity, especially in the high state
4- 3.0 |because of the high output impedance. (2-kS
> l pull-up is an improvement over 6-kQ pull-up)
aL \2. Rapid change in thresholds with temperature
2.0 Threshold1.5V 3. Rapid slowdown with capacitive loading
8
A Vtt h-3 mV/°C 4. Rather poor rate of complex-function introductions
5. Lower speed capabilities than those of some other
1.0 _ families
VOL max Advantages
- 0.45V
1.0 2.0
l'>
l 1. Output circuitry allows the implied AND. This can
3.0 4.0 5.0 result in significant savings
VI L(max) V IH(min)
= 1.0 = 1.90 Input voltage 2. Low power dissipation (especially with 6-kQ pull-
ups)
3. Compatibility with TTL (easily mixed)
FIGURE 29. A-Schematic diagram for DTL. B-Schema-
tic diagram for HTL, with passive pull-up. C-Schematic
diagram for HTL, with active pull-up.
V cc A B Vcc C Vcc

1.75k 6.0k 3.0k 15k 3.0k 15k 1.5k

>K A tCXSA
BA B

5.0k _ 5.0k X . k

56 IEEE spectrum OCTOB3ER 1970

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 4. Low cost the active pull-up does give appreciable better energy-
5. Ease of manufact1ire noise immunity because of its lower impedance. More-
6. Wide range of positive logic devices available, over. the output diode eliminites the requirement for a
inCliding AND. NAND. OR. NOR, and excIlIsive OR ..phase-splitter" transistor. which would drive the tmo
7. Ease of use in system designs output transistors out of phase: that is. only one transis-
8. Ease of interface with discrete circuits tor would be on at a time. This will be explained in the
9. Low noise generation TTL section. which appears in next month's instaillment.
10. Large number ofsources in the industry The output diode has the disadvantage of giving a low-
11. Good fanout level output of a diode voltage drop plus V,t of the tran-
sistor. Current sourcing and sinking characteristics are
. rensa (?/application given in Figs. 32 and 33 respectively. The major HTL
I. Small computers palraim1eters for the ,-saver type of design are as follows:
2. Calculators Tlemperature range - 30 to 75 C (special. 55 to 125 C)
3. Instrumentation Upper clock frequency - 3 MHz
4. Counters lV, =- 15, I volt (special. 18 volts)
5. Medical electronics Rise time (passive) -- 12()0 s. R0) to 90",
6. Computer electronics Rise time (active) l1() uls. i0",, to 90",,
7. Military systems [all time 3t) us. l0 to 90.
8. Control systems
9. Aerospace systems
10. Ground-support systemiis
HTL 150
There are many applications in noisy environments 135
13.5 --
where logic with appreciably greater noise ilnllunity
than DTL is a requirement. High-threshold logic has
been designed for these areas. Individual designs vary
to some extent between manufacturers, but this form of O
logic is charaicterized by higher supply voltages, high | HTL
noise immunity, and high thresholds obtained by adding >l
a Zener breakdown voltage to the normal circuit diode r- 5.0
drops. The circuit form is the same as DTL except for o DTL
the Zener. which replaces a diode. and increaised resistor
values, which prevent excessive power dissipation. l-O- noisemargin ~
YI" noise
~ rgn-__
Figure 29(A) repeats the basic DTL gate for comparison 1.5 l _ _-
to the HTL gate with a passive pull-up; see Fig. 29(B). VOL Oi
Figure 29(C) shows an HTL gate with an active pull-up, 0 1.5 5.0 6.5 8.5 13.5 15
which results in lower high-level output impedance. V[L 7.5 VIH
The HTL gate operation is the same as for DTL except Input voltage
for voltage levels. The input diode drop and emitter-- FIGURE 30. Worst-case noise margins. Temperature
base voltage of the d saver cancel out, giving a threshold -30°C to 750C, V-t= 15 volts.
dependent upon the Zener and the base -emitter drop
of the output transistor. The Zener, actually a base-
emitter junction operating in the breakdown avalanche FIGURE 31. HTL transfer characteristics. Active pull-up,
mode, has a voltage drop that is dependent on processing. TA = 25°C, fanout = 1, V,, = 15 volts.
For a 3()(-ohm-per-square base diffusion the "Zener"
breakdown will be approximately 6.9 volts. which when
added to the base-emitter turn-on potential gives a 7.5-
volt gate threshold. Some designs eliminatte the j3 saver 1.
and have a lower threshold, but the characteristics are
similar. The dlesigns shown in Fig. 29(B) and (C) permiit
ia worse case voltaige-noise inmutnity of 5 volts-- as can tloo
be seen fromi Fig. 30, which also shows the DTL transfer
characteristics for the satke of comparison. Thresholds are -
constant with temperature. since the Zener diode has a-
positive temperature characteristic that matches the
negative characteristic of the base-emitter junctioni. 00.
Actua.l HTL transfer characteristics are illustrated in 0
Fig. 31. Note the "~SqUare" characteristics and relatively
narrow threshold region.F 2'
The aictive pull-tip design has both advantages and 2.5
disaidvaintages. Since the high-level otutput impedance is
muitch lower than with the passive pull-tip, oLutpLtS
should not be tied together. Therefore. the "implied 0 .5 ; C. 1_.5 .-.0
AND" function is restricted to passive pull-ups. However, t . c

G;trrett- IntegrLteL-circuit digit;l logic I11milics 57

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.
 15.0 ~~~~~~~~~~~~~Adranitages
1. High voltage-noise immunity (6 volts typical, 5
12.5 ~~~~~~~~~~~~~~~volts
worst-case)
2. 13- to 14-volt logic swing
3. Slow propagation delay (about 90 ns), which results
o 10.0 l l l l in insensitivity to short noise pulses
4. The 15-volt power supply required is commnonly
7
c ll 5 l | i in industrial areas
0available
7.5 ~~~ ~ ~ ~ ~ ~ ~ ~ ~~5 30'C to 750C temperature range
6. Interfaces easily with discrete components
5 i87. High power-switching capability
5.0
~~~~~~~~~~~~~8.
Highest energy-noise immunity,
9. "Implied AND" capabilities with many fuinct ions,
2.5 ~~~~~~~~~~~~10.
Can be used to drive long lines with 6 v,olts of
common-mode noise imimunity
11. Interfaces eatsily with lineatr fUnctions suc:h as,
operationalamnplifiers and multipliers
2.0 4.0 6.0 8.0 10.0 12.0 12. Constant threshold versus temperature
DC oLJtput currenl_. .nY:!!;a mpeoes 13. Interfaces easily with electromechanic.al coIlpo-
FIGURE 32. HTL output voltage vs. output current. TA = nents
250C, Vcc = 15 volts. 14. New functions are being added to increase flexi-
bility
Areas of application
FIGURE 33. HTL output voltage vs. load current. TA =
25°C, V, = 15 volts. 1. Process control systems
2. Interface with linear circuits
12.5
~~~~~~~~~~~~~~3.
Transducer interfatce
4. Numerical control systemis
10.0 5. Industrial environments
6. M4otor control systems
7. Interfaice with discrete comiponents
° > 8. =Line driving and receiving
9. Replace relays
s 5.0 ~~~~~~~~~~~~~10.
Solenoid valve control
11. SCR circuits
2.5 ~~~~~~~~~~~~~12.
Telephone interface
13. Auitomatted machinery
14. Premade printed-circ uit boards for building-block
0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 y
DC load curient. mili8amperes Lane S. Garrett (M) joined Motorola Semiconductor Prod-
ucts in 1965 as a senior applications engineer. In 1967 he
became section manager of computer applications, ir
which capacity he worked on the application of integrated-
circuit technology to the computer field. In 1968 he moved
into production as project engineer for hybrid digital com-
Powser dissipattion 55miW ~
plex functions. From this position he became projec-
Fanout - 10 Zi_ (high) > 8 MI! manager of different IC families, including both standard
Propagation detlay 9) ns Z,, (low) - 15 kt. and custom lines. In 1969 he received his present position
ZX, (higih, active) 1.4 ki; Z. (low) ~30) olhms of training manager of digital IC product marketing. Prio!
Z,, (higih. passive= 15 k' Threshiold ~ 7.5 volts to joining Motorola he was with the U.S. Naval Air Develop-
V',, (active) 14. 3 volts V,,, (passive) 15 vol s ment Center in Johnsville, Pa., where he was project leader
V,,/ (active) I .0 volt lV,,/- (passive) 0.3 volt on the design and fabrication of a special-purpose high-
speed computer for testing analog-to-digital conversior
HTL circuits are linding use in areas that previously devices.
belonged to discretes. They can be used with electro- Mr. Garrett received the B.S.E.E. degree from Drexe!
mechaInical coiilponents and operate from the mech l cs aUniversity in 1962. He has done graduate
higher-University work at the
ano
of Pennsylvania
voltage supplies usually found in industrial environ- Pennsylvania State University.
ments. He received the M.S.E. degree
from Arizona State University ir
Hf71J fisadaniages_ June 1970. He has previously
I . Uneconomical for large processing systems bwritten numerous application.
2. Costs more to make than low-level logic because notes and training courses for
of the higher vaLtIes of resistors, which take up more Motorola. He is a registered
room on the chip professional engineer in the
3. Needs more functions for the industrial market of the American Management
4. Has relatively high power dissipation Association.

58 Gamrrmt -Id c-r.I icd -cirlit digitai logiti fltmilies

Authorized licensed use limited to: Universidad Nacional Autonoma De Mexico (UNAM). Downloaded on October 24,2020 at 08:04:59 UTC from IEEE Xplore. Restrictions apply.