EL320-Digital Design Lab # 01

Lab # 01
Introduction to Verilog HDL, Using Xilinx
Objective:
 To be familiar with logic gates.
 To understand the verilog coding.
 To learn about the environment for Verilog like ModelSim and Xilinx ISE.
 Introduction to FPGA kit.

Explanation:
We will use Verilog language to perform the upcoming labs in the Environment of MODELSIM or
XILINX ISE.

Verilog:
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital
system like a network switch or a microprocessor or a memory or a flip−flop. It means, by using a
HDL we can describe any digital hardware at any level. Designs, which are described in HDL are
independent of technology, very easy for designing and debugging, and are normally more useful
than schematics, particularly for large circuits.

Verilog supports a design at many levels of abstraction. The major two are −

 Behavioral level
 Gate level

Behavioral level:
This level describes a system by concurrent algorithms (Behavioural). Every algorithm is sequential,
which means it consists of a set of instructions that are executed one by one. Functions, tasks and
blocks are the main elements. There is no regard to the structural realization of the design.

Gate Level:
Within the logical level, the characteristics of a system are described by logical links and their timing
properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`).
The usable operations are predefined logic primitives (basic gates). Gate level modelling may not be
a right idea for logic design. Gate level code is generated using tools like synthesis tools and his
netlist is used for gate level simulation and for backend.

MODELSIM:
ModelSim is a powerful simulator that can be used to simulate the behavior and
performance of logic circuits. This gives a rudimentary introduction to functional
simulation of circuits, using the graphical waveform editing capability of ModelSim.
It discusses only a small subset of ModelSim features.The simulator allows the user
to apply inputs to the designed circuit, usually referred to as test vectors, and to
observe the outputs generated in response. The user can use the Waveform Editor
to represent the input signals as waveforms.

Usman jan 15p-6444 Section EE-B

EL320-Digital Design Lab # 01

XILINX ISE:
Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by
Xilinx for synthesis and analysis of HDL designs, enabling the developer to
synthesize ("compile") their designs, perform timing analysis, examine RTL
diagrams, simulate a design's reaction to different stimuli, and configure the
target device with the programmer.

Xilinx ISE is a design environment for FPGA products from Xilinx, and is tightly-coupled to the
architecture of such chips, and cannot be used with FPGA products from other vendors.The Xilinx ISE
is primarily used for circuit synthesis and design, while ISIM or the ModelSim logic simulator is used
for system-level testing.

FPGA KIT:
An FPGA is an array of logic gates (well, sort of—see below), and this array can
be programmed (actually, “configured” is probably a better word) in the
field, i.e., by the user of the device as opposed to the people who
designed it. Let’s take a closer look at these essential characteristics.

Logic gates (AND, OR, XOR, etc.) are the basic building blocks of
digital circuitry. It’s not surprising, then, that a digital device that is
intended to be highly configurable (that is, "field-programmable") would consist
of numerous gates that can be interconnected in a customizable way.

However, an FPGA is not a vast collection of individual Boolean gates. This would be a very
suboptimal way to provide configurable-logic functionality because it would not take advantage of
the fact that common operations can be implemented much more efficiently as fixed modules. The
same principle is evident in the world of discrete digital ICs. You can buy ICs that consist of AND
gates, OR gates, and so forth—but you wouldn’t want to build a shift register out of individual gates.
Instead, you would buy a shift register IC.

Checked by: __________________________________ Date: _________________

Marks: _______________________________________

Usman jan 15p-6444 Section EE-B