CT 222: HARDWARE DESCRIPTION

LANGUAGES AND PROGRAMMABLE

LOGIC
Instructor: Mr. Mwalongo M, R

(Assistant Lecturer)

Office No: AB 15 (Admin Block)

E-mail: mwalongomarko@gmail.com
 LECTURE 2:
VERILOG HARDWARE DESCRIPTION
LANGUAGE (HDL)
 HARDWARE DESCRIPTION
LANGUAGES
 HDLs provide a way to specify the design at a higher level

of abstraction to raise designer productivity.

 They were originally intended for documentation and
simulation, but are now used to synthesize gates directly
from the HDL.
 The two most popular HDLs are Verilog and VHDL.

 Verilog is less verbose and closer in syntax to C, while

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VHDL supports some abstractions useful for large team
 HARDWARE DESCRIPTION
LANGUAGES
 When coding in an HDL, it is important to remember that
you are specifying hardware that operates in parallel
rather than software that executes in sequence.
 There are two general coding styles. Structural HDL
specifies how a cell is composed of other cells or
primitive gates and transistors. Behavioral HDL specifies
what a cell does.
 A logic simulator simulates HDL code; it can report
whether results match expectations, and can display
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waveforms to help debug discrepancies.

 HARDWARE DESCRIPTION
LANGUAGES

 A logic synthesis tool is similar to a compiler for

hardware: it maps HDL code onto a library of gates
called standard cells to minimize area while meeting
some timing constraints.

 C and C++ themselves can be used as an HDL.L.

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 BASIC CONCEPTS OF VERILOG
 A HDL allows us to specify the components that

make up a digital system using words and symbols

instead of having to use a pictorial representation.
 Every component is identified by its input and

output ports, the logic function it performs and

timing characteristics such as delays and clocking.

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 BASIC CONCEPTS OF VERILOG

 The entire system is described using a set of rules and

keywords. The file is then processed with the language
compiler, and the output can be analyzed for proper
operations.

 Verification using an HDL is mandatory to validate a

system.

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 ARCHITECTURAL FEATURES
TIMING AND
Behavioral
DATAFLOW

Verification
Data storage & movement
RTL
State machine specification
Verificatio
n
Breakdown into netlist of gates
Synthesis
of gates
Verification
Use netlist to create logic
Logic design network
Simulation

Circiuts Cell-based design custom if

needed
Simulation

Physical Design Layout of masks

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Final Check

Tape ToBmy
BEHAVIORAL
 A typical design hierarchy is portrayed in the
previous slide.
 At the highest level is a behavioral description that
describes the system in terms of its architectural
features.

 This is abstract in that it does not contain any details

on how to implement the design.
 Once simulated and refined, the design moves down
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to the Register Transfer Level (RTL).

RTL

 An RTL description of a digital network

concentrates on how the data moves about the
system from unit to unit, and the main operations.
 State machines and sequential circuits can be
introduced at this level.

 Timing windows are checked and rechecked.

 Validation is primary objective. 10

SYNTHESIS

 In fully automated design, the RTL is sent through a

synthesis tool that produces a netlist of the hardware
components needed to actually build the system.
 The success or failure of the synthesis process often
depends upon the skill of the code writer.

 Not all HDL constructs can be synthesized.

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LOGIC DESIGN
 After the synthesis step, the netlist is used to design
the logic network.
 Verification at this level consists of simulations to
insure that the logic is correct.
 After validation, cell library can be used to design
the circuits.
 Components are wired together, and both the
electrical characteristics and the logic are verified 12
using simulation.
PHYSICAL DESIGN

 The cell instances and wirings are translated into

silicon patterns in the physical design phase.
 After verifying the layout, the design is at last
complete and sent to manufacturing for the first
silicon test chip.

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 Verilog HDL provides for descriptions of a digital
system at all of the levels listed.
 Every level is related to every other level, and the
design philosophy is linked by the different types of
code.
 Each level has its own coding style using certain sets
of commands and constructs.
 The concept that links the various levels is that of a
module. A verilog module is the description of a unit
that performs some function.
 Instantiations of simple modules are used to create
more complex modules.
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STRUCTURAL GATE-LEVEL MODELLING
 Consider a 4-input AOI circuit. The logic is
constructed using primitive AND and NOR gates
that take the inputs a, b, c, d and produce an output
of f=NOT(a.b + c.d)
 Keywords are boldface

 At the structural modelling level

The keywords are often primitive
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Logic operations (gates)
STRUCTURAL GATE-LEVEL MODELLING
 The keyword module defines the start of the listing
for a network that has the name AOI4.
 The last line of the listing indicates that the
description of the module is complete.
 The names of input and output “identifiers” are listed
in parentheses, with the output f first then the inputs
a, b, c and d.
 The next group of lines are the port keyword input
and output that identify the input and output 16

variables.
STRUCTURAL GATE-LEVEL MODELLING

 The wire keyword identifies w1 and w2 as internal values

that are needed to describe the network, but are not input
or output ports. A wire declaration is a datatype called a
net. A net value is determined by the output of the
driving gate.
 The structure of the logic is specified by the next three
lines. These are instances of primitive AND and NOR
gates that are part of the verilog language.
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STRUCTURAL GATE-LEVEL MODELLING
 A gate instance has the form

gate_name instance_name (out, in_1, in_2, in_3…);

Where instance_name is an optional specifier that is

used to correlate gates to their listing. In our
example we have named the gates G1, G2, and G3,
so these appear in the listing.

 A structural listing provides a unique one-to- one

correspondence with the components of a logic
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network.
STRUCTURAL GATE-LEVEL MODELLING

 Suppose that we start with the following module

description and then construct the logic diagram
from it.

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 IDENTIFIERS
 Identifiers are names of modules, variables, and
other objects that we can reference in the design.
 Identifiers consist of upper – and lowercase letters,
digits 0 through to 9, the underscore character (_),
and the dollar sign ($).
 The first character must be a letter or a underscore
in normal usage. An identifier must be a single
group of character for example: input_control_A 20

and not input control A. Verilog is case sensitive.

 VALUE SET
 The value set refers to the specific values that a
binary variable can have.
 Verilog provides four levels for the values needed to
describe hardware: 0, 1, x and z.
 0 and 1 levels are the usual binary values: logic 0 or
FALSE statement, logic 1 or TRUE statement.
 x represents an unknown value while z is the high-
impedance value. 21
 GATE PRIMITIVES

 Primitive logic function keywords provide the basis for

structural modeling at this level. Important operations
in verilog are and, nand, or, nor, xor, not and buf,
where buf is non inverting drive buffer.
 Since x and z are allowed, we must define how a gate
reacts to an expanded set of input stimuli.

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23
24
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 COMMENT LINE

 Comments are useful for documenting code.

 In the statement

xor(s_out, in_0, in_1);//This line produces s_out

 Everything to the right of // is ignored by
compiler.

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PORTS
 Ports are interface terminals that allow a module to
communicate with other modules. These correspond
to the input and output points on a library cell.

 All ports must be declared within a module listing.

Bidirectional port is declared with the syntax

inout IO_0, IO_1;

Where the identifiers IO_0 and IO_1 can be used as

either inputs or outputs to the module. 27
28
 Considering the NOR-based SR latch, new features
have been introduced.

 The first is the register (reg) datatype specification.

This datatype is one whose value is held until it is
overwritten by another value. In this case, this allows
for the values q and q_bar to be held for
communication to another port in a different module.
Note they are specified as both reg and output ports.
 The second is the multiple instancing of the nor gate
primitive using one line. Single line represents two 29

independent gates.
 GATE DELAYS
 The logic delay through a gate is sometimes modeled using a
single dalay time (propagation delay) from the input to the
output.

 Delays are specified in instantiations using the pound sign (#)

as in;
nand #(prop_delay) G1 (output, in_a, in_b);
Where prop_delay is the value of the delay.
 If the rise and fall times are known separately, they can be used
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by writing nand # (t_rise, t_fall) G1 (output, in_a, in_b);
GATE DELAYS
 The turn off delay can also be included as in:

nand #(t_rise,t_fall,t_off) G1 (output, in_a, in_b);

 The number of values in the #(listing) determines the
manner in which verilog interprets the information.

 Numerical values of gate delay values are specified as

integer values of an internal time step unit.
and #(4,2) A1 (out, A_in, B_in);
Assigns t_rise = 4 units and t_fall = 2 units.
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 Relative units are sufficient for a broad class of simulations, so it

is not necessary to use absolute time values (i.e., seconds)

 If numerical values are desired, then one uses a compiler

directive of the form

‘timescale t_unit/t_precision
in the listing.

 t_unit and t_precision can have values of 1,10,or 100 followed

by a time scaling unit of s, ms, us, ns, ps or fs. The t_unit gives
the time scale, while t_precision give the resolution.
‘timescale 1ns/100ps
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If a gate instance is written as xor #(10)(out, A_0, A_1); The
 GATE DELAYS

 Gate delays allow us to monitor the response of a

network in a dynamic environment.

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34
 The verilog listing in the previous slide simulates the module shown in
the figure of slide 33.

 It introduces the concept of a stimulus module that provides the signals.

 The first listing for module DelayEx has nothing new in it except for the
delay specifications.

 The stimulus module allows us to “test” the module DelayEx by

defining the inputs using Verilog syntax.

 For the stimulus, we define variables of A, B, and C as reg values,

while OUT is a wire. The module is instantiated into the stimulus by
the lines

// The circuit instantiation is next

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DelayEx G1 (OUT, A, B, C);

 The next group of statements specify the inputs. The initial

directive establishes the zero time values using the begin…end

structure. Embedded within this section is the system output
command.

$monitor ($time, “A=%b, B=%b, C=%b, OUT=%b”, A, B, C,

OUT);

Where the dollar sign indicates a compiler directive. This provides

outputs of A, B, C, and OUT every time one of the variables
changes.
 The notation a=%b means the variable a is to be shown in binary

format. 36

 The final directive #3 indicates that the simulation is completed at

 This example provides an idea of how to build a
testbench for Verilog code. Once the network is
defined, different stimulus modules can be written to
test the logic.
 The stimulus module is usually separate from the logic
module so that the inputs can be changed without
affecting the logic. The Verilog work environment
allows the two to be linked during the simulation.
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 NUMBER SPECIFICATION
 In the delay example, input stimuli were defined via statements
such as
 A=1; B=0; C=0;

 These are interpreted as default binary values. Values can be

specified in base-r for radix values of 2 (binary, b), 8(octal, o),
10 (decimal, d), and 16 (hexadecimal, h) using a format of
<size>’<base designator><value>
 with <size> a decimal number indicating the number of bits in
the number. Some examples are;
1’b0 // 1-bit number with a value of 0
4’b1011 //4-bit binary word with a value of 1011
16’h1a3 //16-bit number with a value of hexadecimal 1a36 38
6 //3-bit number with a decimal value of 4 = 100₂
3’d4
 Values can be declared in a listing. For example, the
code
reg reset; initial
begin
reset = 1’b1; //initialize reset to a
value of 1 #10 reset = 1’b0;
/*reset to 0 after 10 time units*/
end

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THANK YOU!!!!!!!!!!

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