FPGA (Field Programmable Gate Array)

•FPGA are special form of programmable devices with higher densities and complexities as compared to SPLDs and CPLDs.
•In SPLDs, programming technique may be either through Mask type or through CAD tool.
•In CPLDs it is mostly through CAD tool and in FPGA programming is entirely through CAD tool.
•Logic chips that are programmed through mask-based technologies are called Mask Programmable Gate Arrays (MPGAs).
•MPGAs consist of an array of pre-fabricated transistors that can be customized into the user‟s logic circuit by connecting the
transistors with custom wires.
•This means that in order for a user to employ an MPGA a large setup cost is involved and manufacturing time is long

1. FPGA configuration is performed through programming by the end user using CAD tool.
2. Programmable switch employed here is either SRAM or anti-fuse.
3. FPGA has extremely high logic capacity and complexity level found in each low level logic blocks.
4. Memory blocks exist as in-built structure within chip, so, a full-fledged processor may be implemented using FPGA.
5. Presence of internal clock source within FPGA eliminates the need of external oscillator while designing sequential
circuit.
6. A single FPGA can replace thousands of discrete components by incorporating millions of logic gates in a single
integrated circuit (IC) chip.

Unlike processors, FPGAs use dedicated hardware for processing logic and do not have an operating system. FPGAs
are truly parallel in nature so different processing operations do not have to compete for the same resources. As a
result, the performance of one part of the application is not affected when additional processing is added.

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Switching technologies: FPGAs are based on an array of logic modules and a supply of uncommitted
wires to route signals. In some gate arrays these wires are connected by a mask design during
manufacture. In FPGAs, however, these wires are connected by the user and therefore must use an
electronic device to connect them. Three types of devices have been commonly used to do this

1. SRAM based - discussed earlier

2. Anti-fuse

When FPGAs are powered off, configuration bits stored in RAM of FPGAs are automatically erased.

Next time when power comes, FPGA cannot run since the programmable switches have no more defined
status, hence the connectivity too.

Thus, configuration bits need to be reloaded every time the system is powered up. This reloading may be
done by JTAG cable either from some computer or from other equivalent devices (like E2PROM etc.), or
there may be an automatic loader for this purpose.

Lattice semiconductor, therefore, has constructed a two layer memories, the top layer being the E2PROM
containing the program (or, configuration bits permanently). The bottom layer (or, running layer) containing
SRAM reloads every time the power comes up, the configuration bits from the top layer and runs
subsequently.

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Anti-fuse

•Anti-fuses are originally open circuits

•and take on low resistance only when programmed.
•Anti-fuses are suitable for FPGAs because they can be built using modified CMOS technology. x

Actel’s anti-fuse structure, known as PLICE

other anti-fuses rely on metal for conductors, with amorphous

silicon as the middle layer.

Vialink offers a very low on-resistance of about 50 ohms (PLICE is about 300 ohms) and parasitic capacitance.

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Table: Summary of Programming Technologies

FPGA Structure :
The internal resources of an FPGA chip consist of a matrix of configurable logic blocks
(CLBs) surrounded by a periphery of I/O blocks. Signals are routed within the FPGA
matrix by programmable interconnect switches and wire routes.

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Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as
complex as that of a microprocessor. It can used to implement different combinations of combinational and sequential logic
functions.
Routing in FPGAs consists of wire segments of varying lengths which can be interconnected via electrically programmable
switches. Density of logic block used in an FPGA depends on length and number of wire segments used for routing.

There are four main categories of FPGAs

currently commercially available.

1. Symmetrical array
2. Row-based
3. Hierarchical PLD
4. Sea-of-gates

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43
44
 FPGA logic block architecture: a comparative study of various technologies adopted

Current commercial FPGAs employ logic blocks that are based on one or more of the following:
1. Transistor pairs
2. Basic small gates auch as two input NANDs or Exclusive Ors
3. Multiplexers
4. Look up tables (LUTs)
5. Wide fan in AND-OR structure

1. Transistor pairs
The FPGA from Crosspoint Solutions uses a single transistor pair in the logic block

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Principle of operation :
1. when a=1, „s‟ is connected to „t‟; but „p' decoupled from „q‟.
2. when b=1, „t‟ is connected to „u‟; but „q' decoupled from „r‟.
3. thus when a.b=1, „s‟ is connected to „u‟; but „p' decoupled from „r‟
4. but „u‟, „r‟, and „p' being connected together are grounded as „s' is zero.
5. It means „m‟ is also grounded.
6. Hence „w‟ is connected to „v'. As w=1 (being connected to +5V), v=1 hence f=1. Thus when ab=1, f=1.
7. when c=0, „z‟ is connected to „w‟ (through transistor 5/); i.e., z=1 hence f=1. Thus when c=0, f=1

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 2. Using basic small gates:

3. Multiplexer:

Actel Act-1 logic block is that consists of three multiplexers and one logic gate and has a total of 8 inputs and one output.

By setting each variable to a input signal, or to a constant, 702 logic

functions can be realized.

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Note that

1. Multiplexer based logic blocks have the advantage of providing a large degree of functionality for a relatively
small number of transistors.
2. This is however, achieved at the expense of a large number of inputs (eight in case of Actel and 14 in case of
QuickLogic), which when utilized place high demands on routing resources.
3. Such blocks are therefore more suited to FPGAs that use programmable switches of small size such as
antifuses

4. Look up tables
1. A look up table is an array of output against another array of inputs combinations with one to one correspondence
between them.
2. SRAM is used mainly as programmable switch. The truth table for a k-input logic function is stored in 2K1
SRAM.
3. The address lines of the SRAM function as inputs and the output of the SRAM provides the value of the logic
function.

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 The advantage
k
high functionality – a k-input LUT can implement any function of k-inputs and there are 22

such functions.

The disadvantage
• The disadvantage is that they are unacceptably large for more than about five inputs since the number of
memory cell needed for a k input look up table is 2k.
• While the number of functions that can be implemented increases very fast, those additional functions are not
commonly used in logic designs and are also difficult to exploit for a logic synthesis tool. Hence it is often the
case that a large LUT will be largely under-utilized.

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5. Wide fan in AND-OR structure

•The architecture has evolved from PLA based architecture of traditional PLDs
•The logic block consists of wide fan in (20 to over 100 inputs) AND gates feeding into an OR gate with three to eight inputs.

Any floating gate transistor based programmable

switch is used.

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•The advantage is that the wide AND gate can be used to form logic functions with few levels of logic blocks reducing
the need for programmable interconnect.

Disadvantage
•It is difficult however to make efficient use of all of the inputs to all of the gates resulting loss of density.
•PULL UP devices consume significant amount of power.
•To mitigate this, each gate in the MAX7000 series block can be programmed to consume about 60% less power but
at the expense of about 40% increase in delay.

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 •Nowadays logic blocks of FPGAs consists features which are the result of combination of various architectures.
•As an example Altera FLEX 8000 contains logic element that consists of LUTs, sequential circuit (Flipflop) and
multiplexers. AT&T ORCA FPGA contains LUTs, multiplexers and sequential circuit.

Xilinx SRAM-based FPGAs

• Xilinx introduced first FPGA family, XC2000 series, in about 1985.
• now offer three more generations: XC3000, XC4000, and XC5000, out of which XC4000 family is most popular
and is under consideration for the present illustration purpose.
• XC5000 is cheaper but similar with XC4000 although with same sacrifice in speed.
• These FPGAs are SRAM based. But Xilinx has recently introduced an FPGA family based an anti-fuses, called
the XC8100.
• A new version of this family, the 4000E, has the additional feature that the RAM can be configured as a dual part
RAM with a single write part and two read parts.

Features
• The basic structure of the Xilinx is array based.
• The Xilinx4000 family devices range in capacity from about 2000 to more than 15000 equivalent gates.
• The XC4000 features a logic block, called a Configurable Logic Block (CLB) that is based on look-up tables (LUTs).
• Constructed a two layer memories, the top layer being the E2PROM containing the program (or, configuration bits
permanently).
• The bottom layer (or, running layer) containing SRAM reloads every time the power comes up, the configuration bits
from the top layer and runs afterwards.

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•The XC4000 CLB contains three separate LUTs, as shown. There are two 4-input LUTs that are led by CLB inputs,
And the third LUT can be used in combination with the other two.
•This arrangement allows the CLB to implement a wide range of logic functions of upto nine inputs, two separate
functions of four inputs or other possibilities.
•Each CLB also contains two flipflops with which sequential circuit can also be implemented.
•The XC4000 chips have “system oriented” features. For instance, each CLB contains circuitry that allows it to
efficiently perform arithmetic (ie., a circuit that can implement a fast carry operation for adder like circuits).
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•The LUTs in a CLB can be configured as read / write RAM cells.
•Besides logic, the other key feature that characterizes an FPGA is its interconnect structure. The XC4000 interconnect
is arranged in horizontal and vertical channels.
•Each channel contains some number of short wire segment that span a single CLB ( the number of segments in each
channel depends on a specific part number), larger segments that span two CLBs, and very long segments that span
the entire length or width of the chip.

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 Programmable switches are available to connect the inputs and outputs of the CLBs to the wire segments, or to
connect one wire segment to another.
The speed performance of an implemented circuit depends in part on how the wire segments are allocated to individual
signals by CAD tools and therefore may vary from the specification in initial design entry.

Disadvantage
1. Loading of E2PROM is slow.
2. Loading of SRAM layer from E2PROM is slow because of slow speed of RAM.
3. SRAM cells themselves are not radiation hardened.
4. Hence, Quicklogic has removed SRAM layer and developed fast E2PROM, a costly alternative used many wheres,
e.g., in space applications.

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