CPLD & FPGA ARCHITECTURES

Classification of PLDs
• The classification of PLDs is given below.
 Simple Programmable Logic Device [SPLD]

• As the name suggests SPLD has a simple

architecture. PROM is a best example for
SPLD.
• SPLD is capable of implementing hundreds of
gates and normally programmed by the user by
using inexpensive programmers.
• The main limitation of SPLDs is their low
logic capacities due to the restricted nature of
AND-OR planes.
 Complex Programmable Logic Devices
(CPLDs)
• The CPLD is the complex programmable Logic
Device which is more complex than the SPLD.
• CPLDs were pioneered by Altera, first in their
family of chips called Classic EPLDs, and then
in three additional series, called MAX 5000, MAX
7000 and MAX 9000.
• This is build on SPLD architecture and creates a
much larger design.
• SPLD can be used to integrate the functions of a
number of discrete digital ICs into a single device
• CPLD can be used to integrate the functions of a
number of SPLDs into a single device.
• CPLD architecture is based on a small number of
logic blocks and a global programmable
interconnect.
• Instead of relying on a programming unit
configure chip , it is advantageous to be able to t
perform the programming while the chipo is still
attached to its circuit board.
• This method of programming is known is called In-
System programming (ISP).
• It is not usually provided for PLAs (or) PALs , but it
is available for the more sophisticated chips known
as Complex programmable logic device.
CPLD architecture

LAB – Logic Array Block / uses PALs

PIA – Programmable InterconnectArray
• The CPLD consists of a number of logic blocks or
functional blocks, each of which contains a macro
cell and either a PLA or PAL circuit arrangement.
• The macro cell provides additional circuitry to
accommodate registered or nonregistered outputs,
along with signal polarity control.
• Polarity control provides an output that is a true
signal or a complement of the true signal.
• The actual number of logic blocks within a CPLD
varies ,the more logic blocks available, the larger the
design that can be configured.
• In the center of the design is a global
programmable interconnect.
• This interconnect allows connections to the
logic block macrocells and the I/O cell arrays
(the digital I/O cells of the CPLD connecting to
the pins of the CPLD package).
• The programmable interconnect is usually
based on either array-based interconnect or
multiplexer-based interconnect
• Multiplexer-based interconnect uses digital
multiplexers connected to each of the macrocell
inputs within the logic blocks.
• Specific signals within the programmable
interconnect are connected to specific inputs of the
multiplexers.
• It would not be practical to connect all internal
signals within the programmable interconnect to
the inputs of all multiplexers due to size and
speed of operation
 FIELD PROGRAMMABLE GATE ARRAYS

• The concept of FPGA was emerged in 1985

with the XC2064TM FPGA family from Xilinx .
• The “FPGA is an integrated circuit that
contains many (64 to over 10,000) identical
logic cells that can be viewed as standard
components.”
• The individual cells are interconnected by a
matrix of wires and programmable switches.
• Unlike CPLDs, FPGAs contain neither AND nor
OR planes
• Each logic block in an FPGA has a small
number of inputs and one output.
• A look up table (LUT) is the most commonly
used type of logic block used within FPGAs.
• There are two types of FPGAs.(i) SRAM based
FPGAs and (ii) Anti-fuse technology
based(OTP).
• Every FPGA consists of the following
elements.
• Configurable logic blocks(CLBs)
• Configurable input output blocks(IOBs)
• Two layer metal network of vertical and
horizontal lines for interconnecting the CLBS.
Which are called Programmable
Interconnects.
FPGA-Architecture
Block Diagram
• The periphery of the Logic Cell Array is made
up of user programmable input/output blocks
(IOBs).
• Each block can be programmed independently
to be an input ,an output or bi-directional pin
with three state control.
• Each IOB also includes flip-flops that can be
used to buffer inputs and outputs.
 Programmable Interconnect
• In FPGAs three types of metal resources are
provided to fulfill various network
interconnect requirements. They are
• General Purpose Interconnect
• Direct Connection
• Long lines (multiplexed busses and wide AND
gates)
 General Purpose Interconnect
• It consists of a grid of five horizontal and
five vertical metal segments located between
the rows and columns of logic and IOBs.
• Each segment is the height or width of a
logic block.
• Switching matrices join the ends of these
segments and allow programmed
interconnections between the metal grid
segments of adjoining rows and columns.
• The switches of an un-programmed device are
all non-conducting.
• The connections through the switch matrix
may be established by the automatic routing
or by selecting the desired pairs of matrix pins
to be connected or disconnected.
• The interconnect buffers are available to
propagate signals in either direction on a given
general interconnect segment.
• These bidirectional (bidi) buffers are found
adjacent to the switching matrices, above and
to the right.
 Direct Interconnect
• Direct interconnect provides the most
efficient implementation of networks between
adjacent CLBs or I/O Blocks.
• Signals routed from block to block using the
direct interconnect exhibit minimum
interconnect propagation and use no general
interconnect resources.
 Long lines
• The Long lines bypass the switch matrices
and are intended primarily for signals that
must travel a long distance, or must have
minimum skew among multiple destinations.
• Long lines, run vertically and horizontally the
height or width of the interconnect area.
• Each interconnection column has three
vertical Long lines, and each interconnection
row has two horizontal Long lines.
 Programming Technologies
• There are a number of programming technologies
that have been used for reconfigurable
architectures.
• Each of these technologies have different
characteristics and have significant effect on the
programmable architecture.
Some of the well-known technologies are
(i).SRAM Based Programming Technology
(ii).Flash Programming Technology(EEPROM) ,
and (iii) Anti-fuse based Programming Technology
 SRAM-Based Programming Technology
• Static memory cells are the basic cells used for
SRAM-based FPGAs.
• Most commercial vendors like XILINX, Lattice
and Altera etc.use static memory (SRAM)
based programming technology in their
devices.
• These devices use static memory cells which
are divided throughout the FPGA to provide
configurability.
• There are two primary uses for the SRAM cells.
Most of them are used to set the select lines to
multiplexers that steer interconnect signals.
• The majority of the remaining SRAM cells are
used to store the data in the lookup-tables (LUTs)
that are typically used in SRAM-based FPGAs to
implement logic functions.
• Historically, SRAM cells were used to control the
tri-state buffers and simple pass transistors that
were also used for programmable interconnect.
• SRAM-based programming technology has
become the dominant approach for FPGAs
because of its re-programmability and the use
of standard CMOS process technology and
therefore leading to increased integration,
higher speed and lower dynamic power
consumption of new process with smaller
geometry.
• There are however a number of drawbacks
associated with SRAM-based programming
technology.
• For example an SRAM cell requires 6 transistors
which makes this technology costly in terms of
area compared to other programming
technologies.
• Further SRAM cells are volatile in nature and
external devices are required to permanently store
the configuration data.
• These external devices add to the cost and area
overhead of SRAM-based FPGAs.
 Flash Programming Technology
• An important alternative to the SRAM-based
programming technology is the use of flash or
EEPROM based programming technology. This
technology inject charge onto a gate that “floats”
above the transistor.
• This approach is used in flash or EEPROM memory
cells. These cells are non-volatile; they do not lose
information when the device is powered down.
• With modern IC fabrication processes, it has become
possible to use the floating gate cells directly as
switches.
• An EPROM transistor looks like a normal MOS
transistor except it has a second, floating, gate.
• Applying a programming voltage VPP (usually
greater than 12 V) to the drain of the n- channel
EPROM transistor programs the EPROM cell
• A high electric field causes electrons flowing
toward the drain to move so fast they “jump”
across the insulating gate oxide where they are
trapped on the bottom, floating gate.
• Electrons trapped on the floating gate raise the
threshold voltage of the n- channel EPROM
transistor
• Once programmed, an n- channel EPROM device
remains off even with VDD applied to the top
gate

Floating gate MOSFET diagrams

• An un programmed n- channel device will turn
on as normal with a top-gate voltage of VDD.
• Exposure to an ultraviolet (UV) lamp will erase
the EPROM cell. An absorbed light quantum
gives an electron enough energy to jump from
the floating gate
• Programming an EEPROM transistor is similar
to programming an UV-erasable EPROM
transistor, but the erase mechanism is
different.
• Floating gate MOSFETs are to be placed in the
place of fuses in fusible link technology.
EEPROM offer users excellent capabilities and
performance.
• Only one external power supply is required
since the high voltage for program/erase is
internally generated
• Electrons trapped in a floating gate will modify
the characteristics of the cell, and so a logic “0”
or a logic “1” will be stored.
• Flash-based programming technology is also
more area efficient than SRAM-based
programming technology.
• Flash-based programming technology has its
own disadvantages also.
• Unlike SRAM-based programming technology,
flash based devices cannot be
reconfigured/reprogrammed an infinite
number of times.
• Also, flash-based technology uses non-
standard CMOS process.
 Anti-fuse Programming Technology
• An alternative to SRAM and floating
gate-based technologies is anti fuse
programming technology.
• This technology is based on structures
which exhibit very high-resistance under
normal circumstances but can be
programmably “blown” (in reality,
connected) to create a low resistance link.
• An anti-fuse is a two terminal device with an
unprogrammed state presenting a very high
resistance between its terminals.
• When a high voltage (from 11 to 20 volts,
depending on the type of anti-fuse) is applied
across its terminals the anti-fuse will “blow”
and create a low resistance link.
• This link is permanent.
• Programming an anti-fuse requires extra
circuitry to deliver the high programming
voltage and a relatively high current of 5 mA
or more.
• This is done in through fairly sizable pass
transistors to provide addressing to each anti-
fuse.
• Anti-fuse technology is used in the FPGA‟s
from Actel , Quick logic , and Cross point
• A major advantage of the anti-fuse is its
small size, little more than the cross-section
of two metal wires.
• But this advantage is limited by the large size
of the necessary programming transistors,
which handle large currents, and the
inclusion of isolation transistors that are
sometimes needed to protect low voltage
transistors from high programming voltages.
• A second major advantage of an anti-fuse is its
relatively low series resistance.
• The on-resistance of the ONO anti-fuse is 300
to500 ohms, while the amorphous silicon anti-
fuse is 50 to100 ohms.
• Additionally, the parasitic capacitance of an
un programmed amorphous anti-fuse is
significantly lower than for other programming
technologies
• The limitations of this technology are , this
technology does not make use of standard CMOS
process.
• Also, anti-fuse programming technology based
devices cannot be reprogrammed.
• The ideal technology should be re-
programmable, non-volatile, and that uses a
standard CMOS process.
• But it is clear that none of the above
technologies satisfy these conditions
 Comparison of Programming Technologies

Inspites of all the advantages and disadvantages, the

SRAM-based programming technology is the most
widely used programming technology. The main
reason is its use of standard CMOS process .Due to this
reason it is expected that this technology will continue
to dominate the other two programming technologies