7.

2 Programmable Logic Devices

¶
Combinational logic circuits can be constructed from programmable logic devices (PLDs). The
general idea is illustrated in Figure 7.2.1 for two input variables and two output functions of
these variables.

Figure 7.2.1. Simplified circuit for a programmable logic array.

Each of the input variables, both in its uncomplemented and complemented form, are inputs to
AND gates through fuses. (The S-shaped lines in the circuit diagram represent fuses.) The fuses
can be “blown” or left in place in order to program each AND gate to output a product. Since
every input, plus its complement, is input to each AND gate, any of the AND gates can be
programmed to output a minterm.

The products produced by the array of AND gates are all connected to OR gates, also through
fuses. Thus, depending on which OR-gate fuses are left in place, the output of each OR gate is a
sum of products. There may be additional logic circuitry to select between the different outputs.
We have already seen that any Boolean function can be expressed as a sum of products, so this
logic device can be programmed by “blowing” the fuses to implement any Boolean function.

PLDs come in many configurations. Some are pre-programmed at the time of manufacture.
Others are programmed by the manufacturer. And there are types that can be programmed by a
user. Some can even be erased and reprogrammed. Programming technologies range from
specifying the manufacturing mask (for the pre-programmed devices) to inexpensive electronic
programming systems. Some devices use “antifuses” instead of fuses. They are normally open.
Programming such devices consists of completing the connection instead of removing it.

There are three general categories of PLDs:

Programmable Logic Array (PLA)
Both the AND gate plane and the OR gate plane are programmable.

Read Only Memory (ROM)

Only the OR gate plane is programmable.

Programmable Array Logic (PAL)

Only the AND gate plane is programmable.

7.2.1 Programmable Logic Array (PLA)

¶
A programmable logic array is typically larger than the one shown inFigure 7.2.1, which is
already complicated to draw. To simplify the drawing, it is typical to use a diagram as shown
in Figure 7.2.2 to specify the design.
This diagram deserves some explanation. Note in Figure 7.2.1 that each input variable and its
complement is connected to the inputs of all the AND gates through a fuse. The AND gates have
multiple inputs—one for each variable and its complement. In Figure 7.2.2 we use one horizontal
line leading to the input of each AND gate to represent multiple wires, one for each variable and
its complement. So each AND gate in Figure 7.2.2 has eight inputs even though we draw only
one line.

Figure 7.2.2. The horizontal lines to the AND gate inputs represent multiple wires—one for each
input variable and its complement. The vertical lines to the OR gate inputs also represent
multiple wires—one for each AND gate output. The dots represent connections.

The dots at the intersections of the vertical and horizontal line represent places where the fuses
have been left intact. For example, the three dots on the topmost horizontal line indicate that
there are three inputs left connected to that AND gate. The output of the topmost AND gate is:
w′⋅y⋅zw′⋅y⋅z
Referring again to Figure 7.2.1, we see that the output from each AND gate is connected to each
of the OR gates. Therefore, the OR gates also have multiple inputs—one for each AND gate—
and the vertical lines leading to the OR gate inputs represent multiple wires. The PLA
in Figure 7.2.2 has been programmed to provide the three functions:
F1(w,x,y,z)=w′⋅y⋅z+w⋅x⋅z′F2(w,x,y,z)=w′⋅x′⋅y′⋅z′F3(w,x,y,z)=w′⋅y⋅z+w⋅x⋅z′(7.2.1)(7.2.
2)(7.2.3)(7.2.1)F1(w,x,y,z)=w′⋅y⋅z+w⋅x⋅z′(7.2.2)F2(w,x,y,z)=w′⋅x′⋅y′⋅z′(7.2.3)F3(w,
x,y,z)=w′⋅y⋅z+w⋅x⋅z′

7.2.2 Read Only Memory (ROM)

¶
Read only memory can be implemented as a programmable logic device where only the OR
plane can be programmed. The AND gate plane is wired to provide all the minterms. Thus, the
inputs to the ROM can be thought of as addresses. Then the OR gate plane is programmed to
provide the bit pattern at each address.
For example, the ROM diagrammed in Figure 7.2.3 has two inputs, $a_1$ and $a_0$.

Figure 7.2.3. Eight-byte Read Only Memory (ROM). The “××” connections represent
permanent connections. Each AND gate can be thought of as producing an address. The eight
OR gates produce one byte. The connections (dots) in the OR plane represent the bit pattern
stored at the address.

The AND gates are wired to give the minterms:

minterm address
a′1a′0a1′a0′ 0000
a′1a0a1′a0 0101
a1a′0a1a0′ 1010
a1a0a1a0 1111
And the OR gate plane has been programmed to store the four characters (in ASCII code):
minterm address contents
a′1a′0a1′a0′ 0000 ‘00’
a′1a0a1′a0 0101 ‘11’
a1a′0a1a0′ 1010 ‘22’
a1a0a1a0 1111 ‘33’

You can see from this that the terminology “Read Only Memory” is perhaps a bit misleading. It
is actually a combinational logic circuit that has been hard wired. Strictly speaking, memory has
a state that can be changed by inputs. (See Section 7.3.)

7.2.3 Programmable Array Logic (PAL)

¶
In a Programmable Array Logic (PA) device, each OR gate is permanently wired to a group of
AND gates. Only the AND gate plane is programmable. The PAL diagrammed
in Figure 7.2.4 has four inputs. It provides two outputs, each of which can be the sum of up to
four products. The “××” connections in the OR gate plane show that the top four AND gates are
summed to produce F1F1 and the lower four to produce F2.F2. The AND gate plane in this
figure has been programmed to produce the two functions:
F1(w,x,y,z)=w⋅x′⋅z+w′⋅x+w⋅x⋅y′+w′⋅x′⋅y′⋅z′F2(w,x,y,z)=w′⋅y⋅z+w⋅x⋅z′+w⋅x⋅y⋅z+w⋅x⋅
y′⋅z′(7.2.4)(7.2.5)(7.2.4)F1(w,x,y,z)=w⋅x′⋅z+w′⋅x+w⋅x⋅y′+w′⋅x′⋅y′⋅z′(7.2.5)F2(w,x,y,z
)=w′⋅y⋅z+w⋅x⋅z′+w⋅x⋅y⋅z+w⋅x⋅y′⋅z′

Figure 7.2.4. Two-function Programmable Array Logic (PAL). The “××” connections represent
permanent connections. Each AND gate can be thought of as producing an address. The eight
OR gates produce one byte. The connections (dots) in the OR plane represent the bit pattern
stored at the address.
Programmable Logic Devices (PLDs) are the integrated circuits. They
contain an array of AND gates & another array of OR gates. There are three
kinds of PLDs based on the type of array(s), which has programmable
feature.

 Programmable Read Only Memory

 Programmable Array Logic

 Programmable Logic Array

The process of entering the information into these devices is known

as programming. Basically, users can program these devices or ICs
electrically in order to implement the Boolean functions based on the
requirement. Here, the term programming refers to hardware programming
but not software programming.

Programmable Read Only Memory (PROM)

Read Only Memory (ROM) is a memory device, which stores the binary
information permanently. That means, we can’t change that stored
information by any means later. If the ROM has programmable feature,
then it is called as Programmable ROM (PROM). The user has the
flexibility to program the binary information electrically once by using PROM
programmer.

PROM is a programmable logic device that has fixed AND array &
Programmable OR array. The block diagram of PROM is shown in the
following figure.
Here, the inputs of AND gates are not of programmable type. So, we have
to generate 2n product terms by using 2n AND gates having n inputs each.
We can implement these product terms by using nx2n decoder. So, this
decoder generates ‘n’ min terms.

Here, the inputs of OR gates are programmable. That means, we can

program any number of required product terms, since all the outputs of
AND gates are applied as inputs to each OR gate. Therefore, the outputs of
PROM will be in the form of sum of min terms.

Example
Let us implement the following Boolean functions using PROM.

A(X,Y,Z)=∑m(5,6,7)A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each function is
having three variables X, Y & Z. So, we require a 3 to 8 decoder and two
programmable OR gates for producing these two functions. The
corresponding PROM is shown in the following figure.
Here, 3 to 8 decoder generates eight min terms. The two programmable OR
gates have the access of all these min terms. But, only the required min
terms are programmed in order to produce the respective Boolean functions
by each OR gate. The symbol ‘X’ is used for programmable connections.

Programmable Array Logic (PAL)

PAL is a programmable logic device that has Programmable AND array &
fixed OR array. The advantage of PAL is that we can generate only the
required product terms of Boolean function instead of generating all the min
terms by using programmable AND gates. The block diagram of PAL is
shown in the following figure.
Here, the inputs of AND gates are programmable. That means each AND
gate has both normal and complemented inputs of variables. So, based on
the requirement, we can program any of those inputs. So, we can generate
only the required product terms by using these AND gates.

Here, the inputs of OR gates are not of programmable type. So, the number
of inputs to each OR gate will be of fixed type. Hence, apply those required
product terms to each OR gate as inputs. Therefore, the outputs of PAL will
be in the form of sum of products form.

Example
Let us implement the following Boolean functions using PAL.

A=XY+XZ′A=XY+XZ′
A=XY′+YZ′A=XY′+YZ′
The given two functions are in sum of products form. There are two product
terms present in each Boolean function. So, we require four programmable
AND gates & two fixed OR gates for producing those two functions. The
corresponding PAL is shown in the following figure.
The programmable AND gates have the access of both normal and
complemented inputs of variables. In the above figure, the inputs X, X′X′,
Y, Y′Y′, Z & Z′Z′, are available at the inputs of each AND gate. So, program
only the required literals in order to generate one product term by each
AND gate. The symbol ‘X’ is used for programmable connections.
Here, the inputs of OR gates are of fixed type. So, the necessary product
terms are connected to inputs of each OR gate. So that the OR gates
produce the respective Boolean functions. The symbol ‘.’ is used for fixed
connections.

Programmable Logic Array (PLA)

PLA is a programmable logic device that has both Programmable AND array
& Programmable OR array. Hence, it is the most flexible PLD. The block
diagram of PLA is shown in the following figure.
Here, the inputs of AND gates are programmable. That means each AND
gate has both normal and complemented inputs of variables. So, based on
the requirement, we can program any of those inputs. So, we can generate
only the required product terms by using these AND gates.

Here, the inputs of OR gates are also programmable. So, we can program
any number of required product terms, since all the outputs of AND gates
are applied as inputs to each OR gate. Therefore, the outputs of PAL will be
in the form of sum of products form.

Example
Let us implement the following Boolean functions using PLA.

A=XY+XZ′A=XY+XZ′
B=XY′+YZ+XZ′B=XY′+YZ+XZ′
The given two functions are in sum of products form. The number of
product terms present in the given Boolean functions A & B are two and
three respectively. One product term, Z′XZ′X is common in each function.
So, we require four programmable AND gates & two programmable OR
gates for producing those two functions. The corresponding PLA is shown in
the following figure.
The programmable AND gates have the access of both normal and
complemented inputs of variables. In the above figure, the inputs X, X′X′,
Y, Y′Y′, Z & Z′Z′, are available at the inputs of each AND gate. So, program
only the required literals in order to generate one product term by each
AND gate.
All these product terms are available at the inputs of each programmable
OR gate. But, only program the required product terms in order to produce
the respective Boolean functions by each OR gate. The symbol ‘X’ is used
for programmable connections.