Module-05

Q1. What are PLDs?

Ans.- Programmable Logic Devices PLDs are the integrated circuits. They contain an array of AND gates
& another array of OR gates.

An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to
perform different functions is called a Programmable Logic Device (PLD).

The internal logic gates and/or connections of PLDs can be changed/configured by a

programming process.

One of the simplest programming technologies is to use fuses. In the original state of the device,
all the fuses are intact.

Programming the device involves blowing those fuses along the paths that must be removed in
order to obtain the particular configuration of the desired logic function.

PLDs are typically built with an array of AND gates (AND-array) and an array of OR gates (OR-
array).

Q2. What are advantages of PLDs?

Ans.-

Advantages of using PLDs:

Advantages of using PLDs are less board space, faster, lower power requirements (i.e., smaller
power supplies), less costly assembly processes, higher reliability (fewer ICs and circuit
connections means easier troubleshooting), and availability of design software.

There are three fundamental types of standard PLDs: PROM, PAL, and PLA.

A fourth type of PLD, which is discussed later, is the Complex Programmable Logic Device
(CPLD), e.g., Field Programmable Gate Array (FPGA).
A typical PLD may have hundreds to millions of gates.
In order to show the internal logic diagram for such technologies in a concise form, i t is necessary
to have special symbols for array logic.
Figure shows the conventional and array logic symbols for a multiple input AND and a multiple
input OR gate.
Q3. What are limitations of specific ICs?

Ans:-

Problems of using standard ICs in logic design are that they require hundreds or thousands of
these ICs, considerable amount of circuit board space, a great deal of time and cost in inserting,
soldering, and testing. Also require keeping a significant inventory of ICs.

Q4. Explain types of PLDs

Ans-

The three fundamental types of PLDs differ in the placement of programmable connections in the
AND-OR arrays. Figure shows the locations of the programmable connections for the three types.
The PROM (Programmable Read Only Memory) has a fixed AND array (constructed as a decoder)
and programmable connections for the output OR gates array. The PROM implements Boolean
functions in sum-of-min terms form.

The PAL (Programmable Array Logic) device has a programmable AND array and fixed
connections for the OR array.

The PLA (Programmable Logic Array) has programmable connections for both AND and OR
arrays. So it is the most flexible type of PLD.

The process of entering the information into these devices is known as programming. Basically, users
can program these devices or ICs electrically in order to implement the Boolean functions based on the
requirement. Here, the term programming refers to hardware programming but not software
programming.

Q5. Explain the working of PROM as PLD.

Ans.-

Read Only Memory (ROM) is a memory device, which stores the binary information permanently. That
means, we can’t change that stored information by any means later. If the ROM has programmable
feature, then it is called as Programmable ROM (PROM). The user has the flexibility to program the
binary information electrically once by using PROM programmer.

PROM is a programmable logic device that has fixed AND array & Programmable OR array. The block
diagram of PROM is shown in the following figure.
Here, the inputs of AND gates are not of programmable type. So, we have to generate 2n product terms by
using 2n AND gates having n inputs each. We can implement these product terms by using nx2n decoder.
So, this decoder generates ‘n’ min terms.

Here, the inputs of OR gates are programmable. That means, we can program any number of required
product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the
outputs of PROM will be in the form of sum of min terms.

Example

Let us implement the following Boolean functions using PROM.

A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)

The given two functions are in sum of min terms form and each function is having three variables X, Y &
Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two functions.
The corresponding PROM is shown in the following figure.
Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of all
these min terms. But, only the required min terms are programmed in order to produce the respective
Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections.

Q6. Explain the basics of Programmable Array Logic (PAL) in logic implementation.

Ans.-

PAL is a programmable logic device that has Programmable AND array & fixed OR array. The advantage
of PAL is that we can generate only the required product terms of Boolean function instead of generating
all the min terms by using programmable AND gates. The block diagram of PAL is shown in the
following figure.

Here, the inputs of AND gates are programmable. That means each AND gate has both normal and
complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So,
we can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are not of programmable type. So, the number of inputs to each OR gate will
be of fixed type. Hence, apply those required product terms to each OR gate as inputs. Therefore, the
outputs of PAL will be in the form of sum of products form.

Example

Let us implement the following Boolean functions using PAL.

A=XY+XZ′
A=XY′+YZ′

The given two functions are in sum of products form. There are two product terms present in each
Boolean function. So, we require four programmable AND gates & two fixed OR gates for producing
those two functions. The corresponding PAL is shown in the following figure.

The programmable AND gates have the access of both normal and complemented inputs of variables. In
the above figure, the inputs X, X′, Y, Y′, Z & Z′, are available at the inputs of each AND gate. So,
program only the required literals in order to generate one product term by each AND gate. The symbol
‘X’ is used for programmable connections.

Here, the inputs of OR gates are of fixed type. So, the necessary product terms are connected to inputs of
each OR gate. So that the OR gates produce the respective Boolean functions. The symbol ‘.’ is used for
fixed connections.

Q7.- Explain the working of Programmable Logic Array (PLA) with a suitable example.

Ans.-
PLA is a programmable logic device that has both Programmable AND array & Programmable OR array.
Hence, it is the most flexible PLD. The block diagram of PLA is shown in the following figure.

Here, the inputs of AND gates are programmable. That means each AND gate has both normal and
complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So,
we can generate only the required product terms by using these AND gates.

Here, the inputs of OR gates are also programmable. So, we can program any number of required product
terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of
PAL will be in the form of sum of products form.

Example

Let us implement the following Boolean functions using PLA.

A=XY+XZ′
B=XY′+YZ+XZ′

The given two functions are in sum of products form. The number of product terms present in the given
Boolean functions A & B are two and three respectively. One product term, Z′X is common in each
function.

So, we require four programmable AND gates & two programmable OR gates for producing those two
functions. The corresponding PLA is shown in the following figure.
The programmable AND gates have the access of both normal and complemented inputs of variables. In
the above figure, the inputs X, X′, Y, Y′, Z & Z’, are available at the inputs of each AND gate. So,
program only the required literals in order to generate one product term by each AND gate.

All these product terms are available at the inputs of each programmable OR gate. But, only program
the required product terms in order to produce the respective Boolean functions by each OR gate. The
symbol ‘X’ is used for programmable connections.

Q8.- Explain the concept of CPLD as a logic device.

Ans.-
Complex Programmable Logic Device (CPLD) is one of the PLD. It is used for the implementation of the
logical circuits.
The basic AND-OR structure of PLDs could not be scaled to layer sizes. Hence for scaling larger designs
Complex PLD (CPLD) is required. A typical CPLD is a collection of multiple PLDs and an
interconnection structure, all on the same chip.

Need of CPLD
 The Programmable Logic Devices (PLDs) such as PLAs and PALs have limited number of
inputs, product terms and outputs. These devices can support up to about 32 total number of
inputs and outputs only.
 For implementation of circuits that require more inputs and outputs than that are available in a
single SPLD chip, either multiple SPLD chips can be employed. But this has also some
limitations.
  To overcome these limitations, more sophisticated chip like CPLD is needed to design the digital
circuits.
Concept of CPLD
 The complexity of any digital IC chip can be specified in terms of number of equivalent 2-input
NAND gates.
 A typical PAL has 8 macro cells, if each macro cell represents about 20 equivalent gates, than the
PAL can accommodate a circuit that needs up to about 160 gates.
 For a circuit requiring very large number of gates, CPLDs having large number of macrocells
(say 512 macro cells) can implement circuits of up to about 10 thousand equivalent gates i.e. they
are similar to SPLDs except that the CPLD is equivalent of 2 to 64 SPLDs.

General structure of a CPLD

 A CPLD typically contains from tens to a few hundred macrocells.
 They are as fast as PLAs but more
 They are digital ICs that are just like a large number of PALs in a single silicon chip connected to
each other through a cross point switch.
Architecture of CPLD
 Architecture (Block diagram) of CPLD
 It consists of a number of PAL like blocks, input/output blocks and a set of interconnection wires.
 The PAL like blocks are connected to a set of interconnection wires and to an input/output block.
 The input block is used to drive signals to the pins of the CPLD at the appropriate voltage levels
with the appropriate current.
 A PAL-like block (also called functional block) usually consists of 16 macro cells.
 Each macro cell consists of an AND-OR configuration, an EX-OR gate a flip-flop, a multiplexer
and a tristate buffer.