Programmable Logic Devices

Chapter 10
 PLD Arrays and Classification
• Programmable Logic devices (PLD’s) are used
in many applications to replace SSI (Small
scale integration) and MSI (Medium-scale
integration) circuits.
• They save space and reduce the actual
number of cost of devices in a given design.
• PLD consist of large array of AND gates and OR
gates that can be programmed to achieve
specified logic function.
 Programmable Logic
•Programmable Logic Devices (PLDs) are ICs with a
large number of gates and flip flops that can be
configured with basic software to perform a specific
logic function or perform the logic for a complex circuit.
Major types of PLDs are:
• SPLD: (Simple PLDs) are the earliest type of array logic
used for fixed functions and smaller circuits with a limited
number of gates. (The PAL and GAL are both SPLDs).
• CPLD: (Complex PLDs) are multiple SPLDs arrays and
inter- connection arrays on a single chip.
• FPLD: (Field Programmable Gate Array) are a more
flexible arrangement than CPLDs, with much larger
capacity.
 SPLD: The PAL
• A PAL (programmable array logic) consists of a programmable
array of AND gates that connects to a fixed array of OR gates.
• Generally, PALs are implemented with fuse process
technology and are, therefore, one-time programmable (OTP).
• The PAL structure allows any sum-of-products (SOP) logic
expression with a defined number of variables to be
implemented.
• A simple PAL structure is shown in Figure 10–1 for two input
variables and one output; most PALs have many inputs and
many outputs.
• A programmable array is essentially a grid or matrix of
conductors that form rows and columns with a programmable
link at each cross point.
 SPLD: The PAL
• Each programmable link, which is a fuse in the case
of a PAL, is called a cell.
• Each row is connected to the input of an AND gate,
and each column is connected to an input variable
or its complement.
• By programming the presence or absence of a fuse
connection, any combination of input variables or
complements can be applied to an AND gate to
form any desired product term.
• The AND gates are connected to an OR gate,
creating a sum-of-products (SOP) output.
SPLD: The PAL
 Implementing a Sum-of-Products Expression
• An example of a simple PAL is programmed as
shown in Figure 10–2 so that the product term
AB is produced by the top AND gate, AB’ is
produced by the middle AND gate, and A’B’ is
produced by the bottom AND gate.
• The final output from the OR gate is the SOP
expression,
Implementing a Sum-of-Products Expression
 SPLD: The GAL
• The GAL is essentially a PAL that can be
reprogrammed. It has the same type of AND/
• OR organization that the PAL does. The basic
difference is that a GAL uses a
reprogrammable process technology, such as
EEPROM(E2CMOS), instead of fuses, as shown
in Figure 10–3.
The GAL
 Simplified Notation for PAL/GAL Diagrams
• Actual PAL and GAL devices have many AND and OR gates in
addition to other elements and are capable of handling many
variables and their complements.
• Most PAL and GAL diagrams that you may see on a data sheet
use simplified notation, as illustrated in Figure 10–4, to keep
the schematic from being too complicated.
• PALs and GALs have a large number of programmable
interconnection lines, and each AND gate has multiple inputs.
• Typical PAL and GAL logic diagrams represent a multiple input
AND gate with an AND gate symbol having a single input line
with a slash and a digit representing the actual number of
inputs.
• Figure 10–4 illustrates this for the case of 2-input AND gates.
Simplified Notation for PAL/GAL Diagrams
EXAMPLE 10–1
• Show how a PAL is programmed for the
following 3-variable logic function:

Solution

• The programmed array is shown in Figure 10–5.

The intact fusible links are indicated by small
red Xs. The absence of an X means that the fuse
is open.
Solution
 PAL/GAL General Block Diagram

FIGURE 10–6 General block diagram of a PAL or GAL.

 Macrocells
• A macrocell generally consists of one OR gate
and some associated output logic. The
macrocells vary in complexity, depending on
the particular type of PAL or GAL. A macrocell
can be configured for combinational logic,
registered logic, or a combination of both.
• Registered logic means that there is a flip-flop
in the macrocell to provide for sequential logic
functions.
 Classification of PLDs
• PLDs are classified according to their
architecture, which is basically the internal
functional arrangement of the elements that
give a device its particular operating
characteristic.
 Types of PLDs
• There are four types of PLDs.
1. Programmable Read-Only Memory (PROM)
2. Programmable Logic Array (PLA)
3. Programmable Array Logic (PAL)
4. Generic Array Logic (GAL)
 Programmable Read-Only Memory
(PROM)
• The PROM consist of a set of fixed (nonprogrammable)
AND gates as a decoder or a programmable OR array.
• PROM is used as addressable memory and not as a logic
device because of limitation imposed of fixed AND gate.
 Programmable Logic Array (PLA)
• PLA is a PLD that consist of programmable AND array and
programmable OR array.
• It was developed to overcome some limitations of PROM.
• PLA is also called FPLA (Field programmable Logic Array),
because the user in the field, not the manufacturer,
programs it.
 Programmable Logic Array (PAL)
• PAL was developed in order to overcome certain
disadvantages of the PLA, such as longer delays due to
additional fusible links that result from using two
programmable arrays and more circuit complexity.
• The basic PAL consist of programmable AND array and a
fixed OR array with output logic,
• PAL is one-time programmable logic device and is
implemented with bipolar technology (TTL or ECL).
 Generic Array Logic (GAL)
• Like a PAL, it has programmable AND array and a fixed OR
array with programmable output logic.
• The two main difference between PAL and GAL is that (a)
The GAL is reprogrammable (b) the GAL has
programmable output configration.
• It can be reprogrammed again and again because it uses
EECOMS(Electrically erasable CMOS) technology instead
of bipolar and fusible links.