REALIATION OF LOGIC CIRCUIT TO GENERATE r’s COMPLEMENT USING

LOGIC GATES

To design a logic circuit that generates the RS complement using logic gates,
you'll need to understand the RS complement operation and then translate it
into a circuit using basic logic gates like AND, OR, and NOT gates. Here's a
step-by-step guide to help you create the logic circuit:

Understanding RS Complement
RS complement is also known as 1's complement. It's the operation of flipping
all the bits of a binary number. For example:

 RS complement of 1010 is 0101

 RS complement of 1100101 is 0011010

Circuit Design
We'll design a circuit that takes an input binary number and generates its RS
complement.

Inputs:

 A, B, C, D (for a 4-bit binary number)

Outputs:

 ‾A, ‾B, ‾C, ‾D (RS complement of the input)

Logic Gates:
1. NOT Gate: Inverts the input.
2.
3. AND Gate: Performs logical AND operation.
4.
5. OR Gate: Performs logical OR operation.
Circuit Diagram:
luaCopy code
_______ A ----| | | NOT | --|\ |_____| | AND ------\ | \ _______ | OR ----|\ B ----| | | | OR ---- Output A' | NOT | --|/
|/ |_____| | | _______ _______ OR ---- Output B' C ----| | | | | | NOT | --| _|___ | |_____| | | | | | | | | | AND |
__________| | | | D --------------|___|___|

Circuit Explanation:

1. Each input bit �,�,�,�A,B,C,D goes through a NOT gate to get its
complement.
2. The complemented inputs are then passed through AND gates along
with the original inputs.
3. The output of each AND gate is then fed into an OR gate, which
combines all the results to generate the RS complement of the input.

Lab Procedure:
1. Assemble the required logic gates (NOT, AND, OR).
2. Connect them according to the circuit diagram.
3. Test the circuit with different input combinations to verify the output
matches the expected RS complement.
4. Document the procedure and results in your lab manual.

This circuit will effectively generate the RS complement of a 4-bit binary

number. Make sure to properly understand each logic gate's functionality and
how they combine to achieve the desired output.

realization of given boolean function using universal gates and minimizing the same compare
the gate count before and after minimization

Certainly! Let's suppose we have the given Boolean function

�(�,�,�)=Σ(1,2,3,4,5,6,7)F(A,B,C)=Σ(1,2,3,4,5,6,7). We'll first implement it using
universal gates (specifically NAND gates), and then we'll minimize the function to reduce the
gate count
Given Function:

�(�,�,�)=Σ(1,2,3,4,5,6,7)F(A,B,C)=Σ(1,2,3,4,5,6,7)

Truth Table:
A

1
F

In Boolean Algebra, the NAND and NOR gates are called universal gates because any
digital circuit can be implemented by using any one of these two i.e. any logic gate can
be created using NAND or NOR gates only.
Every logic gate has a representation symbol. The below image shows a graphical
representation of all logic gates.
 Graphical representation of logic gates.

1. Implementation of AND Gate using Universal gates.

a) Using NAND Gates

The AND gate can be implemented by using two NAND gates in the below fashion:

b) Using NOR Gates

Implementation of AND gate using only NOR gates as shown below:

2. Implementation of OR Gate using Universal gates.

a) Using NAND Gates

The OR gate can be implemented using the NAND gate as below:
b) Using NOR Gates
Implementation of OR gate using two NOR gates as shown in the picture below:

3. Implementation of NOT Gate using Universal gates.

a) Using NAND Gates

b) Using NOR Gates

4. Implementation of XOR Gate using Universal gates.

a) Using NAND Gates

b) Using NOR Gates

5. Implementation of XNOR Gate using Universal gates.

a) Using NAND Gate

b) Using NOR Gate

6. Implementation of NOR Gate using NAND Gates

7. Implementation of NAND Gate using NOR Gates

Implementing Using NAND Gates (without minimization):

We can directly implement the function using NAND gates for each term in the sum of
minterms.

�(�,�,�)=�′�′�′+�′�′�+�′��′+�′��+��′�′+��′�+���
′F(A,B,C)=A′B′C′+A′B′C+A′BC′+A′BC+AB′C′+AB′C+ABC′

Each term can be implemented using 3 NAND gates (2 for negated inputs and 1 for the NAND
operation itself), totaling 7×3=217×3=21 NAND gates.

Minimization:
Now, let's minimize the function using Boolean algebra to reduce the gate count.

�(�,�,�)=�′�′�′+�′�′�
F(A,B,C)=A′B′C′+A′B′C+A′BC′+A′BC+AB′C′+AB′C+ABC′

Applying Boolean algebraic manipulations, we can simplify this expression:

�(�,�,�)=�′�′+�′(�′�′+��′)+��′�′F(A,B,C)=A′B′+C′(A′B′+AB′)
+AB′C′ �(�,�,�)=�′�′+�′
F(A,B,C)=A′B′+C′(1)+AB′C′ �(�,�,�)=�′�′+�′+��′�′F(A,B,C)=A′B′+C′
+AB′C′
Implementing Minimized Function Using NAND Gates:

1. Calculate �′�′A′B′, ��′AB′, and ��′�′AB′C

 A′B′=NAND(NAND(A,A),NAND(B,B))
 ��′=NAND(NAND(�,�),NAND(�,�))AB
′=NAND(NAND(A,B),NAND(A,B))
 ��′�′=NAND(NAND(�,�),�)AB′C′=NAND(NAND(A,B),C)
2. Calculate �′+��′�′C′+AB′C′:
 �′+��′�′=NAND(NAND(�,�),NAND(NAND(�,�),�))C′+AB′C
′=NAND(NAND(C,C),NAND(NAND(A,B),C))

Gate Count After Minimization:

After minimization, we have 44 NAND gates.

Conclusion:

By minimizing the function, we reduced the gate count from 2121 to 44. This highlights the
importance of minimizing Boolean functions in logic circuit design to optimize the utilization of
resources.

 design and realize full adder circuit using gates/universal gates with output manual
To design and realize a full adder circuit using basic logic gates or universal gates, we first need
to understand its truth table and logic. A full adder takes three inputs: A, B, and Carry-in (Cin),
and produces two outputs: Sum (S) and Carry-out (Cout)

Truth Table:

� � Cin Sum (�)Cout 0000000110010100110110010101011100111111