INDEX

Exp. Experiment Exp. Date Sub.Date Remarks

No.
1 Design CMOS Inverter Using 24/08/2020 29/08/2020
SymicaDE tool
2 Design XOR Gate Using 01/09/2020 08/09/2020
SymicaDE tool
3 Design NAND and Nor Gate 09/09/2020 16/09/2020
using SymicaDE tool
4 Design and simulate NAND gate 16/09/2020 23/09/2020
using Pseudo NMOS logic
5 Design and simulate the ring 23/09/2020 30/09/2020
oscillator using SymicaDE
6 Design and simulate 6T RAM 30/09/2020 07/10/2020
using SymicaDE
7 Design and simulate 2x1 MUX 07/10/2020 14/10/2020
using SymicaDE
8 Design and simulate D flip flop 04/11/2020 11/11/2020
master slave using SymicaDE
9 Design and simulate CS 11/11/2020 18/11/2020
Amplifier using Symica DE
10 Design and simulate Current 18/11/2020 25/11/2020
Mirror using Symica DE
Date:24/08/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 1

Aim: To design and simulate CMOS inverter using SymicaDE tool.

Tools Used: SymicaDE

Theory:
It consists of PMOS and NMOS FET. The input Vin serves as the gate voltage for both
transistors. When a high voltage (Vdd) is given at input terminal of the inverter, the PMOS
becomes open circuit and NMOS switched OFF so the output will be pulled down to Vss.

Fig. 1.1: Circuit Diagram of CMOS Inverter

Truth Table:

Table 1.1: Truth Table of CMOS Inverter

Vin Vout
0 1
1 0

Design and Simulation:

Fig. 1.2: Circuit Diagram for testing the INVERTER circuit

Table 1.2: Design specifications of CMOS Inverter

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS:W/L 720nm/180nm
VDD 1.8V
Input Signal(Pulse) V1=1.8V,V2=0,Time Period=100ns,Pulse Width=50ns
Observations:
Transient Analysis:

Fig. 1.3: Transient result of CMOS Inverter output

Simulated Propagation Delay=6.02111e-009

Result: CMOS Inverter circuit has been successfully designed using Symica DE tool.
Date:01/09/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 2

Aim: To design and simulate XOR Gate using SymicaDE tool.

Tools Used: SymicaDE

Theory:
XOR Gate is a digital logic gate that gives a true (1 or HIGH) output when the number of true
inputs is odd.An XOR gate implements an exclusive or,that is ,a true output results if
one,and only one,of the inputs to the gate is true,If both inputs are false(0 or Low) or both
are true ,a false output results.XOR represents the inequality function, i.e, the output is true
if the inputs are nit alike otherwise the output is false.

Fig 2.1: Circuit Diagram of XOR using CMOS

Table 2.1: Truth Table of XOR Gate

A B Y=A Xor B
0 0 0
0 1 1
0 0 1
1 1 0
Design and Simulation:

Fig. 2.2: Circuit Diagram of XOR Gate using CMOS

Fig. 2.3: Circuit Diagram for testing the XOR Gate above
Table 2.2: Design specifications of XOR gate

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS:W/L 720nm/180nm
VDD 1.8V
Input Signal(Pulse V1) V1=1.8V,V2=0,Time Period=100ns,Pulse Width=49ns
Input Signal(Pulse V2) V1=1.8V,V2=0,Time Period=200ns,Pulse Width=99ns

Observations:
Transient Analysis:

Fig. 2.4: Transient result of XOR Gate output

Simulated Propagation Delay w.r.t input A=3.02498e-009

Simulated Propagation Delay w.r.t input B=3.02498e-009

Result: XOR Gate has been successfully designed using Symica DE tool.
Date:08/09/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 3

Aim: To design and simulate NAND and NOR Gate using SymicaDE tool.

Tools Used: SymicaDE

Theory:
The NAND (Not – AND) gate has an output that is normally at logic level 1 and only goes
LOW to logic level 0 when ALL of its inputs are at logic level 1. The Logic NAND Gate is the
reverse or Complementary form of the AND gate.

The inclusive NOR (Not-OR) gate has an output that is normally at logic level 1 and only goes
LOW to logic level 0 when ANY of its inputs are at logic level 1. The Logic NOR Gate is the
reverse or Complementary form of the inclusive OR gate.

Fig 3.1: Circuit Diagram of NAND and NOR Gate using CMOS

Table 3.1: Truth Table of NAND Gate

A B Y=A Nand B
0 0 1
0 1 1
1 0 1
1 1 0
Table 3.2: Truth Table of NOR Gate

A B Y=A Nor B
0 0 1
0 1 0
1 0 0
1 1 0

Design and Simulation:

Fig. 3.2: Circuit Diagram of NAND Gate using CMOS

Fig. 3.3: Circuit Diagram of NOR Gate using CMOS

Table 3.2: Design specifications of NAND and NOR gate

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS:W/L 720nm/180nm
VDD 1.8V
Input Signal(Pulse V1) V1=1.8V,V2=0,Time Period=100ns,Pulse Width=49ns
Input Signal(Pulse V2) V1=1.8V,V2=0,Time Period=200ns,Pulse Width=99ns

Observations:
NAND Gate:

Transient Analysis:

Fig. 3.4: Transient result of NAND Gate output

Simulated Propagation Delay w.r.t input A=3.20349e-009

Simulated Propagation Delay w.r.t input B=2.98127e-009

NOR Gate:

Transient Analysis:
Fig. 3.5: Transient result of NOR Gate output

Simulated Propagation Delay w.r.t input A=1.45445e-009

Simulated Propagation Delay w.r.t input B=1.23222e-009

Result: NAND and NOR Gate has been successfully designed using Symica DE tool.
Date:16/09/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 4

Aim: To design and simulate NAND gate using Pseudo NMOS logic.

Tools Used: SymicaDE

Theory:
In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output
which is false only if all its inputs are true; thus its output is complement to that of an AND
gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is
LOW (0), a HIGH (1) output results. A NAND gate is made using transistors and junction
diodes. By De Morgan's theorem, a two-input NAND gate's logic may be expressed
as AB=A+B, making a NAND gate equivalent to inverters followed by an OR gate.

Fig 4.1: Symbol of NAND gate

Table 4.1: Truth Table of NAND Gate

A B Y=A Nand B
0 0 1
0 1 1
1 0 1
1 1 0

Design and Simulation:

Fig 4.2: Circuit Diagram of Nand Gate using Pseudo NMOS logic

Fig. 4.3: Circuit Diagram for the simulation of NAND Gate above

Table 4.2: Design specifications of NAND gate

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 400nm/180nm
PMOS:W/L 400nm/180nm
VDD 1.8V
Input Signal(Pulse V1) V1=1.8V,V2=0,Time Period=100ns,Pulse Width=50ns
Input Signal(Pulse V2) V1=1.8V,V2=0,Time Period=200ns,Pulse Width=100ns
Observations:
Comparison Table :

Table 4.3: Comparison between Nand Gate using CMOS logic and pseudo NMOS logic

S.no. Property Nand Gate using CMOS Nand Gate using Pseudo
logic NMOS logic
1 Delay ~=3ns ~=5ns
2 Swing 0V-1.8V 0.5V-1.8V
3 Number of transistors 4 3

Transient Analysis:

Fig. 4.4: Transient result of NAND Gate output using pseudo NMOS logic

Simulated Propagation Delay w.r.t input A=5.64729e-009

Simulated Propagation Delay w.r.t input B=5.42507e-009

Result: NAND Gate using pseudo NMOS logic has been successfully designed using Symica
DE tool and compared with NAND Gate using CMOS logic.
Date:23/09/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 5

Aim: To design and simulate the Ring oscillator using SymicaDE tool.

Tools Used: SymicaDE

Theory:
Ring oscillator is widely used to generate sinusoidal signal in numerous applications. Today’s
most of the ac devices make use of ring oscillator due to several key advantages. Ring
oscillator is very simple in design and operates over a wide range of source and input
voltages (provided the source voltage is fixed).

Fig 5.1: Ring oscillator circuit

Fig 5.2: Output waveform of ring oscillator

Design and Simulation:

Fig 5.3: Circuit Diagram of Ring oscillator using 3 inverters

Table 5.1: Design specifications of ring oscillator

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS:W/L 720nm/180nm
VDD 1.8V
Initial Voltage(Out) 1.8V

Observations:
Transient Analysis:

Fig. 5.4: Transient result of ring oscillator

Delay of inverter: 6.02ns

Frequency of oscillation by simulation:1/(64.795-28.492)=1/34.303=29.15MHz

Frequency of oscillation by calculation:1/2*3.14*6.02=26.45MHz

Result: Ring Oscillator has been successfully designed using Symica DE tool.
Date:07/10/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 6

Aim: To design and simulate 6T RAM using SymicaDE tool.

Tools Used: SymicaDE

Theory:
Static random access memory (SRAM) can retain its stored information as long as power is
supplied. This is in contrast to dynamic RAM (DRAM) where periodic refreshes are necessary
or non-volatile memory where no power needs to be supplied for data retention, as for
example flash memory. The term ``random access'' means that in an array of SRAM cells
each cell can be read or written in any order, no matter which cell was last accessed.

Fig 6.1: 6T SRAM circuit

Table 6.1:Truth Table of 6T SRAM

Operation BL BLbar WL
Read 1 1 1
Write(1) 1 0 1
Write(0) 0 1 1

Design and Simulation:

Fig 6.2: Circuit Diagram of 6T SRAM

Table 6.2: Design specifications of 6T SRAM

Parameters Values
CMOS technology PTM 130nm
NMOS:W/L (M4,M5) 360nm/180nm
NMOS: W/L(M0,M1) 720nm/180nm
PMOS:W/L 360nm/180nm
VDD 1.8V
Input signal BL V1=0V,V2=1.8V,time Period=100ns,Pulse Width=50ns
Input signal BLbar V1=0V,V2=1.8V, Time Period =10ns Pulse Width=5ns
(For Read)
Input Signal BLbar V1=1.8V,V2=0,Time Period=19ns,Pulse width =5ns
(For Write)
Input Signal WL V1=0V, V2=1.8V,Time Period=12ns,Pulse Width=6ns

Observations:

Transient Analysis:

For Read:
Fig. 6.3: Transient result of 6T SRAM in read mode

For Write:

Fig. 6.4: Transient result of 6T SRAM in write mode

Result: 6T SRAM has been successfully designed using Symica DE tool.

Date:07/10/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 7

Aim: To design and simulate 2X1 MUX using SymicaDE tool.

Tools Used: SymicaDE

Theory:
Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds and
as such, the device we use to do just that is called a Multiplexer.

Fig 7.1: Circuit Diagram of 2X1 MUX using OR, AND and NOT Gates

Table 7.1: Truth Table of 2x1 MUX

S I0 I1 Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Design and Simulation:

Fig. 7.2: Circuit Diagram of 2X1 MUX

Fig. 7.3: Circuit Diagram for testing the 2X1 MUX above
Table 7.2: Design specifications of 2X1 MUX

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS:W/L 720nm/180nm
VDD 1.8V
Input Signal(S) V1=1.8V,V2=0V,Time Period=100ns,Pulse Width=50ns
I0 Vdc=1.8V
I1 Vdc=0V

Observations:
Transient Analysis:

Fig. 7.4: Transient result of 2X1 MUX

Simulated Propagation Delay w.r.t input S=1.81271e-010s

Result:2X1 MUX has been successfully designed using Symica DE tool.

Date:04/11/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 8

Aim: To design and simulate D flip flop using SymicaDE tool.

Tools Used: SymicaDE

Theory:
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that
ensures that inputs S and R are never equal to one at the same time. The D-type flip flop are
constructed from a gated SR flip-flop with an inverter added between the S and the R inputs
to allow for a single D (Data) input.

Fig 8.1: Circuit Diagram of D Flip Flop

Table 8.1: Truth Table of D flip flop

Design and Simulation:

Fig. 8.2: Circuit Diagram of D-flip flop

Fig. 8.3: Circuit Diagram of Master Slave D-flip flop using D flip flop above
Table 8.2: Design specifications of D flip flop

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS:W/L 720nm/180nm
VDD 1.8V
Clk V1=1.8V,V2=0V,Time Period=50ns,Pulse Width=25ns
D V1=1.8V,V2=0V,Time Period=200ns,Pulse Width=60ns

Observations:
Transient Analysis:

Fig. 8.4: Transient result of D flip flop

Result: Master Slave D flip flop has been successfully designed using Symica DE tool.
Date:18/11/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 9

Aim: To design and simulate CS Amplifier using SymicaDE tool.

Tools Used: SymicaDE

Theory:
When the input signal is applied at the gate terminal and source terminal, then the output
voltage is amplified and obtained across the resistor at the load in the drain terminal. This is
called a common source amplifier. Here source acts as a common terminal between the
input and output. It is also known as a voltage amplifier or a transconductance amplifier. It
produces current gain and voltage gain according to the input impedance and output
Impedance. To produce voltage gain along with high input impedances FET’s are used in
these circuits.

Fig. 9.1: Circuit Diagram of CS Amplifier

Design and Simulation:

Fig. 9.2: Circuit Diagram of CS amplifier using resistance

Fig 9.3: Circuit Diagram of CS amplifier using diode connected load

Table 9.1: Design specifications of CS amplifier

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 200nm/180nm
PMOS:W/L 200nm/180nm
VDD 1.8V
Input Signal(Sinusoid) Vdc=0.9V va= 0.9V freq=500M

Observations:
DC Analysis:

Fig. 9.4: DC result of CS amplifier when resistance is acting as load

Fig. 9.5: DC result of CS amplifier with diode connected load

DC transconductance of CS amplifier (resistance as load)=990uA/volt

DC transconductance of CS amplifier (diode connected load )=220uA/volt

DC Gain of CS amplifier(resistance as load) =-990m

DC Gain of CS amplifier(diode connected load) =-4.994

Result: CS amplifier circuit has been successfully designed using Symica DE tool.
Date:25/11/2020

Advanced VLSI Design Lab(EC17203)

EXPERIMENT NO. 10

Aim: To design and simulate Current Mirror using SymicaDE tool.

Tools Used: SymicaDE

Theory:
A current mirror is a circuit designed to copy a current through one active device by
controlling the current in another active device of a circuit, keeping the
output current constant regardless of loading. The current being "copied" can be, and
sometimes is, a varying signal current.

Wilson current mirror circuit uses three active devices that accept the current across its
input and provide the exact copy or mirrored copy of the current to its output.

Fig. 10.1: Circuit Diagram of Wilson Current Mirror

Design and Simulation:

Fig. 10.2: Circuit Diagram of Current Mirror with resistive load

Fig. 10.3: Circuit Diagram of Current mirror with active load

Table 10.1: Design specifications of Current Mirror

Parameters Values
CMOS technology PTM 130nm
NMOS: W/L 400/180nm
PMOS:W/L 200nm/180nm
VDD 1.8V
Observations:
DC Analysis:

Fig. 10.4: DC result of Current Mirror with resistive load

Fig. 10.5: DC result of Current mirror with active load

Result: Current Mirror has been successfully designed using Symica DE tool.