UNIVERSITY OF ENGINEERING AND TECHNOLOGY LAHORE

(NAROWAL CAMPUS)

Computer Architecture

Lab manual

Submitted to:

Osama bin Naeem

Submitted by:
*Muhammad Owais (2019-EE-616)
Rashid Sharif (2019-EE-632)
Abdullah (2019-EE-613)

Department of Electrical Engineering

University of Engineering & Technology Lahore – NWL Campus

 Experiment 1

Write down the procedure to install the xilinx IDE.

1. In first step, go to the website named getinto pc.

2. In second step, after downloading the file it is the time to run the license file.

3. Same step will be followed as the above in this step.

4. In this step, installation will start and in next steps only the directories have
to be given and it will be installed.
 Experiment 2

Design all basic logic gates in Verilog and verify their truth table also.

Objective

Implement logic gates in Verilog to verify their truth table.

Theory

Introduction

Boolean functions may be practically implemented by using electronic gates. The

following points are important to understand.

 Electronic gates require a power supply.

 Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and
5V representing logic 0 and logic 1 respectively.
 The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V
and 5V representing logic 0 and logic 1 respectively. In general, there is only
one output to a logic gate except in some special cases.
 There is always a time delay between an input being applied and the output
responding.

Truth Tables

Truth tables are used to help show the function of a logic gate. If you are unsure
about truth tables and need guidence on how go about drawning them for individual
gates or logic circuits then use the truth table section link.

Logic gates

Digital systems are said to be constructed by using logic gates. These gates are the
AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are
described below with the aid of truth tables.
AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind
that this dot is sometimes omitted i.e. AB

OR gate

The OR gate is an electronic circuit that gives a high output (1) if one
or more of its inputs are high. A plus (+) is used to show the OR
operation.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter. If the input variable is A,
the inverted output is known as NOT A. This is also shown as A', or A with
a bar over the top, as shown at the outputs. The diagrams below show two
ways that the NAND logic gate can be configured to produce a NOT gate. It
can also be done using NOR logic gates in the same way.

NAND gate
 This is a NOT-AND gate which is equal to an AND gate followed by a
NOT gate. The outputs of all NAND gates are high if any of the inputs
are low. The symbol is an AND gate with a small circle on the output.
The small circle represents inversion.

NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a

NOT gate. The outputs of all NOR gates are low if any of the inputs
are high.
The symbol is an OR gate with a small circle on the output. The small
circle represents inversion.

EXOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output

if either, but not both, of its two inputs are high. An encircled plus
sign ( ) is used to show the EOR operation.

EXNOR gate
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a
low output if either, but not both, of its two inputs are high. The symbol is an
EXOR gate with a small circle on the output. The small circle represents inversion.

Procedure

Here is a basic procedure for implementing logic gates using Verilog:

1. Define the module: Start by defining a Verilog module for the gate you want
to implement.

2. Write the gate equation: In Verilog, you can write the Boolean equation for
the gate using logic operators such as "&&" for AND and "||" for OR.

3. Simulate the gate: To test the functionality of the gate, you can create a test
bench module that instantiates the gate module and provides inputs.

4. Compile and run the simulation: Once you have written the gate module and
test bench module, you can compile and run the simulation using a Verilog
simulator such as eda playground or VCS. The simulator will generate
waveforms showing the input and output signals, allowing you to verify the
functionality of the gate.

5. Use the gate in a larger design: Once you have verified the functionality of
the gate, you can use it in a larger Verilog design by instantiating the gate
module and connecting its input and output ports to other modules.

Software simulation of gates

Representation of AND gate on Xilinx

Representation of NOT gate on Xilinx

Representation of OR gate on Xilinx

Representation of NAND gate on Xilinx

Representation of NOR gate on Xilinx

Representation of XOR gate on Xilinx

Representation of XNOR gate on Xilinx

Experiment 3

Impliment Half_Adder, Half_subtractor, Full_Adder and Full_Subtractor

using Verilog and prove using truth table.

1.1Objective
To understand how to use different tools involved in Verilog software and how to
implement adder and subtractor digital circuits using Verilog.

1.2Theory

1.2.1Adder
The digital logic circuit in electronics that is extensively used for addition of
numbers is known as adder. Adders are used in processors that calculates addresses
and similar activities.

1.2.1Half Adder
A half adder is a combinational logic circuit. It has two inputs ( one bit each ) termed
as A and B that generates sum ( S ) and carry ( C ) as output. Half adder is designed
using two logic gates that is AND gate and XOR gate. The output of sum is obtained
from XOR gate and the output of carry is obtained from AND gate.

Fig 1:Truth table for Half adder

Expression for Half Adder
The logic expression for half adder is given as

Sum ( S ) = A’B + AB’ = A ⊕ B

Carry ( C ) = A . B

1.2.3Full Adder
A full adder is a combinational logic circuit. It has three inputs ( one bit each ) termed
as A, B and Cin that generates sum ( S ) and carry ( C )as output. Full adder is
designed using two XOR gate, two AND gate, and one OR gate. The output of sum
is obtained from XOR gate and the output of carry is obtained from OR gate. Shown
in circuit below.
 Fig 1:Truth table for Half adder

Expression for Full Adder

The logic expression for full adder is given as

Sum = (A ⊕ B) ⊕ Cin
Carry = AB + BCin + ACin

1.2.4Half subtractor
Half subtractor is a combination circuit with two inputs and two outputs which
is difference and borrow. It produces the difference between the two binary bits at
the input and also produces an output (Borrow) to indicate if a 1 has been borrowed.
In the subtraction (A-B), A is called a Minuend bit and B is called as Subtrahend
bit.

Fig 1:Truth table for Half adder

The SOP form of the Diff and Borrow is as follows:
Diff= A’B+AB’
Borrow = A’B
1.2.5Full subtractor

A full subtractor is a combinational circuit that performs subtraction of two bits,

one is minuend and other is subtrahend, taking into account borrow of the previous
adjacent lower minuend bit. This circuit has three inputs and two outputs. The three
inputs A, B and Bin, denote the minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout represent the difference and output
borrow, respectively.

Fig 1:Truth table for Half adde

Logical expression for difference –

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin
Logical expression for borrow –
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
= A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
= A’Bin + A’B + BBin

1.3 Procedure

 In first step, we have converted the boolean expressions into the Verilog form.
 We have made function for individual circuits which are half adder, full adder,
half subtractor and full subtractor.
 We have made code for test bench in which we have used wire for declaring
output and we have used reg to declare an input variable.
 We have made two functions in test bench code, one for truth table and other
for showing the verification of truth table.
1.4 Output

1.4.1 For Half adder

1.4.2 For Full adder

1.4.3 For Half subtractor

1.4.4 For Full subtractor

Experiment 4

Design the adder and subtractor using same logic using Verilog.

Objective

To understand the concept of parallel use of numbers for addition and subtraction.

Theory

4-bit binary Adder-Subtractor

In Digital Circuits, A Binary Adder-Subtractor is capable of both the addition
and subtraction of binary numbers in one circuit itself. The operation is performed
depending on the binary value the control signal holds. It is one of the components
of the ALU (Arithmetic Logic Unit).
This Circuit Requires prerequisite knowledge of Exor Gate, Binary Addition and
Subtraction, and Full Adder.
Let’s consider two 4-bit binary numbers A and B as inputs to the Digital Circuit
for the operation with digits
A0 A1 A2 A3 for A
B0 B1 B2 B3 for B
The circuit consists of 4 full adders since we are performing operations on 4-bit
numbers. There is a control line K that holds a binary value of either 0 or 1 which
determines that the operation is carried out is addition or subtraction.
As shown in the figure, the first full adder has a control line directly as its
input(input carry Cin), The input A0 (The least significant bit of A) is directly input
in the full adder. The third input is the exor of B0 and K. The two outputs produced
are Sum/Difference (S0) and Carry (C0).

the value of K (Control line) is 1, the output of B0(exor)K=B0′(Complement B0).

Thus the operation would be A+(B0′). Now 2’s complement subtraction for two
numbers A and B is given by A+B’+Cin. This suggests that when K=1, the
operation being performed on the four-bit numbers is subtraction.
Similarly If the Value of K=0, B0 (exor) K=B0. The operation is A+B which is
simple binary addition. This suggests that When K=0, the operation is performed
on the four-bit numbers in addition.
Then C0 is serially passed to the second full adder as one of it’s outputs. The
sum/difference S0 is recorded as the least significant bit of the sum/difference. A1,
A2, A3 are direct inputs to the second, third and fourth full adders. Then the third
input is the B1, B2, B3 EXORed with K to the second, third and fourth full adder
respectively. The carry C1, C2 are serially passed to the successive full adder as
one of the inputs. C3 becomes the total carry to the sum/difference. S1, S2, S3 are
recorded to form the result with S0.
Procedure
A binary parallel adder is a combinational circuit that adds two binary numbers in
parallel. A binary parallel subtractor is a similar circuit that subtracts two binary
numbers in parallel. Here are the steps to implement a binary parallel adder and
subtractor:

Binary Parallel Adder:

Step 1: Determine the number of bits in the two binary numbers to be added. Let's
assume we are adding two 4-bit numbers A and B.

Step 2: Construct a truth table for the binary addition of the two numbers. The truth
table should have 3 input columns (A, B, and Carry-In) and 2 output columns (Sum
and Carry-Out).

Step 3: Implement the truth table using logic gates. The circuit should have 4 full
adders, one for each bit position. Connect the Carry-Out of each adder to the Carry-
In of the next adder.

Step 4: Connect the inputs (A and B) and the outputs (Sum and Carry-Out) to the
appropriate terminals of the circuit.

Step 5: Test the circuit using different combinations of input values and verify that
the outputs are correct.

Binary Parallel Subtractor:

Step 1: Determine the number of bits in the two binary numbers to be subtracted.
Let's assume we are subtracting a 4-bit number B from another 4-bit number A.

Step 2: Take the two's complement of the number to be subtracted (B). This can be
done by inverting all the bits in B and then adding 1.

Step 3: Add the two numbers using the binary parallel adder circuit as described
above. However, use the two's complement of B as the second input to the adder.

Step 4: Ignore the Carry-Out of the last adder and interpret the Sum output as the
result of the subtraction.
Step 5: Test the circuit using different combinations of input values and verify that
the outputs are correct.

Note: In step 2, the two's complement is used to avoid having to build a separate
binary parallel subtractor circuit. The two's complement of a binary number is
equivalent to subtracting that number from 2^n, where n is the number of bits in the
number.

Software simulations
 Experiment 5

Design different combination of multiplexer using Verilog and also write down
its test bench code.

Objective

To implement 4x1 and 8x1 multiplexer using Verilog with testbench.\

Theory
Multiplexing is the generic term used to describe the operation of sending one or
more analogue or digital signals over a common transmission line at different times
or speeds and as such, the device we use to do just that is called the multiplexer.
The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit
designed to switch one of several input lines through to a single common output line
by the application of a control signal. Multiplexers operate like very fast acting
multiple position rotary switches connecting or controlling multiple input lines
called “channels” one at a time to the output.
Multiplexers, or MUX’s, can be either digital circuits made from high speed logic
gates used to switch digital or binary data or they can be analogue types using
transistors, MOSFET’s or relays to switch one of the voltage or current inputs
through to a single output.
The most basic type of multiplexer device is that of a one-way rotary switch as
shown.

Basic Multiplexing Switch

The rotary switch, also called a wafer switch as each layer of the switch is known as
a wafer, is a mechanical device whose input is selected by rotating a shaft. In other
words, the rotary switch is a manual switch that you can use to select individual data
or signal lines simply by turning its inputs “ON” or “OFF”. So how can we select
each data input automatically using a digital device.
In digital electronics, multiplexers are also known as data selectors because they can
“select” each input line, are constructed from individual Analogue Switches encased
in a single IC package as opposed to the “mechanical” type selectors such as normal
conventional switches and relays.
They are used as one method of reducing the number of logic gates required in a
circuit design or when a single data line or data bus is required to carry two or more
different digital signals. For example, a single 8-channel multiplexer.
Generally, the selection of each input line in a multiplexer is controlled by an
additional set of inputs called control lines and according to the binary condition of
these control inputs, either “HIGH” or “LOW” the appropriate data input is
connected directly to the output. Normally, a multiplexer has an even number of
2n data input lines and a number of “control” inputs that correspond with the number
of data inputs.
Note that multiplexers are different in operation to Encoders. Encoders are able to
switch an n-bit input pattern to multiple output lines that represent the binary coded
(BCD) output equivalent of the active input.
We can build a simple 2-line to 1-line (2-to-1) multiplexer from basic logic NAND
gates as shown.
2-input Multiplexer Design

The input A of this simple 2-1 line multiplexer circuit constructed from standard
NAND gates acts to control which input ( I0 or I1 ) gets passed to the output at Q.
From the truth table above, we can see that when the data select input, A is LOW at
logic 0, input I1 passes its data through the NAND gate multiplexer circuit to the
output, while input I0 is blocked. When the data select A is HIGH at logic 1, the
reverse happens and now input I0 passes data to the output Q while input I1 is
blocked.
So by the application of either a logic “0” or a logic “1” at A we can select the
appropriate input, I0 or I1 with the circuit acting a bit like a single pole double throw
(SPDT) switch.
As we only have one control line, (A) then we can only switch 2 1 inputs and in this
simple example, the 2-input multiplexer connects one of two 1-bit sources to a
common output, producing a 2-to-1-line multiplexer. We can confirm this in the
following Boolean expression.
4-to-1 Channel Multiplexer

The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and
data select lines a, b is given as:
Q = abA + abB + abC + abD
In this example at any one instant in time only ONE of the four analogue switches
is closed, connecting only one of the input lines A to D to the single output at Q. As
to which switch is closed depends upon the addressing input code on lines “a” and
“b“.
So for this example to select input B to the output at Q, the binary input address
would need to be “a” = logic “1” and “b” = logic “0”. Thus we can show the selection
of the data through the multiplexer as a function of the data select bits as shown.
Multiplexer Input Line Selection

Adding more control address lines, (n) will allow the multiplexer to control more
inputs as it can switch 2n inputs but each control line configuration will connect only
ONE input to the output.
Then the implementation of the Boolean expression above using individual logic
gates would require the use of seven individual gates consisting
of AND, OR and NOT gates as shown.

4 Channel Multiplexer using Logic Gates

The symbol used in logic diagrams to identify a multiplexer is as follows:

Multiplexer Symbol

Procedure

To implement a multiplexer in Verilog, you can follow these steps:

1. Define the input and output ports of the module:

 data_in: an input bus for the data inputs to be multiplexed.

 sel: an input bus for the select lines that determine which data input to
output.

 out: an output bus for the selected data input.

2. Write the Verilog code for the multiplexer logic using an always block and a
case statement to select the output based on the select lines

3. Define the module using the module keyword and include the input and output
ports:

4. Instantiate the module in your Verilog design hierarchy, connecting the input
and output ports to signals or other modules.

5. Create a test bench to verify the functionality of the multiplexer by generating

input stimuli, applying them to the input ports of the module, and monitoring
the output. Use $display or $monitor statements to print out the values of the
input and output signals.

6. Compile and simulate the design using a Verilog simulator like ModelSim or
VCS.
 7. Debug the simulation by examining the waveforms to ensure the module
behaves as expected.

8. Synthesize the design using a synthesis tool to create a hardware

implementation.

Software Simulation
4x1 Mux
 Lab 6# Barrel Shifter

Objective
The objective of implementing a barrel shifter is to efficiently perform bitwise shift
operations on binary data by shifting the bits by a variable amount specified by a
shift amount input.

Theory

Barrel Shifter

A barrel shifter is a digital circuit that can shift a data word by a specified number
of bits without the use of any sequential logic, only pure combinational logic. Its has
a control input that specifies the number of bit positions that it shifts by. The Barrel
Shifter is similar to the Shift Register (Multi-bit), except that bits shifted of the
register are shifted back into the opposite end of the register. For example, in right
shift operations, the LSBs shifted out of the register are shifted into the MSBs.

Barrel shifters are applicable for digital signal processors and processors.

One way to implement a barrel shifter is as a sequence of multiplexers where the

output of one multiplexer is connected to the input of the next multiplexer in a way
that depends on the shift distance. When implementing a barrel shifter with a
sequence of shift multiplexers, each shifts a word by 2^k bit positions
(1,2,4,8,16,32...) for different values of k. The number of multiplexing stages is
relative to the width of the input vector.

The diagram below shows a right-shifting barrel shifter for 32-bit words.
With more complex multiplexers and some extra circuitry for dealing with end fill
options, a barrel shifter can handle all of the standard bit shift instruction in a
processor's instruction set.

Simple 8-bit right rotator

We start with the simplest and most direct way to program a right-shift barrel shifter
in Verilog HDL, using a case statement with all possible rotation combinations.

We will design a simple 8-bit barrel shifter that rotates and arbitrary number of bits
to the right. The circuit has an 8-bit data input, data, and a 3-bit control signal, amt,
which specifies the amount to be rotated.

The design uses a selected signal assignment statement to exhaustively list all the
combinations of the amt signal and the corresponding rotated results.
SystemVerilog implementation using a case statement

Test bench and simulation

The test bench uses a for loop to iterate through all possibilities of the signal
indicating the amount to rotate.

In the image of the scope you can see how the values are shifted to the right amt bits,
towards the LSB bits and how the MSBs are filled with the overflowing bits, rotating
the information from left to right.

RTL Elaborated Design Schematics

This way of designing the barrel shifter implies the use of a wide 3 to 8 multiplexer

Procedure

To implement a barrel shifter in Verilog, you can follow these steps:

1. Define the input and output ports of the module:

 data_in: an input bus for the data to be shifted.

 shift_amt: an input bus for the shift amount, which determines the
number of bits to shift the data.

 shift_dir: an input bus for the shift direction, which determines whether
to perform a left shift or right shift.

 data_out: an output bus for the shifted data.

 2. Write the Verilog code for the barrel shifter logic using an always block and
a case statement to select the output based on the shift amount and direction:

3. Define the module using the module keyword and include the input and output
ports.

4. Instantiate the module in your Verilog design hierarchy, connecting the input
and output ports to signals or other modules.

5. Create a test bench to verify the functionality of the barrel shifter by

generating input stimuli, applying them to the input ports of the module, and
monitoring the output. Use $display or $monitor statements to print out the
values of the input and output signals.

6. Compile and simulate the design using a Verilog simulator like ModelSim or
VCS.

7. Debug the simulation by examining the waveforms to ensure the module

behaves as expected.

8. Synthesize the design using a synthesis tool to create a hardware

implementation.

Software simulation
 Lab#7 Register File

Objective
The objective of implementing a register file in Verilog is to provide a block of
storage elements that can store and retrieve binary data, typically used in a processor
design for storing CPU register values.

Theory
Register File

Introduction

Register File is a memory space present within the CPU. It is used by

the CPU to fetch and hold the data from the secondary memory devices. It is faster compared to
other memory devices as it is present within the processor. In RISC cores the register file is larger
in size compared to CISC. Register file can be a static random access memory. Within
these SRAM there are bits of memory labeled according to a binary code which will specify
whether it is active or inactive.

A Register File Read operation functions as follows:

 Any value provided on output selection port (4-bit input Sel_o1) is used to select the content
of the corresponding register to provide as output on the 32-bit output port Op1 on the positive
edge of clock when the read enable switch is high.

 Any value provided on output selection port (4-bit input Sel_o2) is used to select the content
of the corresponding register to provide as output on the 32-bit output port Op2 on the positive
edge of clock when the read enable switch is high.
 Figure 1. Block Diagram of Register File Read operation

A Register File Write operation functions as follows:

 Any value provided on the input selection port (4-bit input Sel_i1) is used to select the
corresponding register into which the value from the 32-bit input port 1 is written to on
the positive edge of clock when the write enable switch is high.

Figure 2. Block Diagram of Register File Write operation

Procedure

To implement a register file in Verilog, you can follow these steps:

1. Define the input and output ports of the module:

 clk: the clock input to the register file.

 rst: a synchronous reset input to reset the register file.

 write_en: an enable signal for writing to the register file.

 write_reg: the register number to write to.

 write_data: the data to write to the register.

 read_en: an enable signal for reading from the register file.

 read_reg1: the first register number to read from.

 read_reg2: the second register number to read from.

 read_data1: the data read from the first register.

 read_data2: the data read from the second register.

2. Define the internal storage elements for the register file. This can be done
using a Verilog array, where each element of the array represents a single
register in the file. The number of registers in the file and the width of each
register can be specified using parameters.

3. Write the Verilog code for the register file logic using always blocks and
conditional statements to handle read and write operations.

4. Define the module using the module keyword and include the input and output
ports.

5. Instantiate the module in your Verilog design hierarchy, connecting the input
and output ports to signals or other modules.

6. Create a test bench to verify the functionality of the register file by generating
input stimuli, applying them to the input ports of the module, and monitoring
 the output. Use $display or $monitor statements to print out the values of the
input and output signals.

7. Compile and simulate the design using a Verilog simulator like ModelSim or
VCS.

8. Debug the simulation by examining the waveforms to ensure the module

behaves as expected.

9. Synthesize the design using a synthesis tool to create a hardware

implementation.

Software Simulation
 Lab#8 ALU

Objective
The objective of implementing an Arithmetic Logic Unit (ALU) in Verilog is to
provide a hardware component that can perform arithmetic and logical operations
on binary data.

Theory

In computing, an arithmetic logic unit (ALU) is a combinational digital circuit that

performs arithmetic and bitwise operations on integer binary numbers. This is in
contrast to a floating-point unit (FPU), which operates on floating point numbers. It
is a fundamental building block of many types of computing circuits, including
the central processing unit (CPU) of computers, FPUs, and graphics processing
units (GPUs).

The inputs to an ALU are the data to be operated on, called operands, and a code
indicating the operation to be performed; the ALU's output is the result of the
performed operation. In many designs, the ALU also has status inputs or outputs, or
both, which convey information about a previous operation or the current operation,
respectively, between the ALU and external status registers.

Signals
An ALU has a variety of input and output nets, which are the electrical
conductors used to convey digital signals between the ALU and external circuitry.
When an ALU is operating, external circuits apply signals to the ALU inputs and, in
response, the ALU produces and conveys signals to external circuitry via its outputs.

Data

A basic ALU has three parallel data buses consisting of two

input operands (A and B) and a result output (Y). Each data bus is a group of signals
that conveys one binary integer number. Typically, the A, B and Y bus widths (the
number of signals comprising each bus) are identical and match the native word
size of the external circuitry (e.g., the encapsulating CPU or other processor).

Opcode
The opcode input is a parallel bus that conveys to the ALU an operation selection
code, which is an enumerated value that specifies the desired arithmetic or logic
operation to be performed by the ALU. The opcode size (its bus width) determines
the maximum number of distinct operations the ALU can perform; for example, a
four-bit opcode can specify up to sixteen different ALU operations. Generally, an
ALU opcode is not the same as a machine language opcode, though in some cases it
may be directly encoded as a bit field within a machine language opcode.

Status

Outputs

The status outputs are various individual signals that convey supplemental
information about the result of the current ALU operation. General-purpose ALUs
commonly have status signals such as:

 Carry-out, which conveys the carry resulting from an addition operation, the
borrow resulting from a subtraction operation, or the overflow bit resulting
from a binary shift operation.

 Zero, which indicates all bits of Y are logic zero.

 Negative, which indicates the result of an arithmetic operation is negative.

 Overflow, which indicates the result of an arithmetic operation has exceeded

the numeric range of Y.

 Parity, which indicates whether an even or odd number of bits in Y are logic
one.

Upon completion of each ALU operation, the status output signals are usually stored
in external registers to make them available for future ALU operations (e.g., to
implement multiple-precision arithmetic) or for controlling conditional branching.
The collection of bit registers that store the status outputs are often treated as a single,
multi-bit register, which is referred to as the "status register" or "condition code
register".

Inputs
The status inputs allow additional information to be made available to the ALU when
performing an operation. Typically, this is a single "carry-in" bit that is the stored
carry-out from a previous ALU operation.

Circuit operation

The combinational logic circuitry of the 74181 integrated circuit, an early four-bit
ALU

An ALU is a combinational logic circuit, meaning that its outputs will change
asynchronously in response to input changes. In normal operation, stable signals are
applied to all of the ALU inputs and, when enough time (known as the "propagation
delay") has passed for the signals to propagate through the ALU circuitry, the result
of the ALU operation appears at the ALU outputs. The external circuitry connected
to the ALU is responsible for ensuring the stability of ALU input signals throughout
the operation, and for allowing sufficient time for the signals to propagate through
the ALU before sampling the ALU result.

In general, external circuitry controls an ALU by applying signals to its inputs.

Typically, the external circuitry employs sequential logic to control the ALU
operation, which is paced by a clock signal of a sufficiently low frequency to ensure
enough time for the ALU outputs to settle under worst-case conditions.
For example, a CPU begins an ALU addition operation by routing operands from
their sources (which are usually registers) to the ALU's operand inputs, while
the control unit simultaneously applies a value to the ALU's opcode input,
configuring it to perform addition. At the same time, the CPU also routes the ALU
result output to a destination register that will receive the sum. The ALU's input
signals, which are held stable until the next clock, are allowed to propagate through
the ALU and to the destination register while the CPU waits for the next clock. When
the next clock arrives, the destination register stores the ALU result and, since the
ALU operation has completed, the ALU inputs may be set up for the next ALU
operation.

Procedure

1. Define the input and output ports of the module:

 clk: the clock input to the ALU.

 rst: a synchronous reset input to reset the ALU.

 op: a control input that selects the operation to be performed by the ALU.

 a: the first input to the ALU.

 b: the second input to the ALU.

 result: the output of the ALU.

2. Define the internal signals and variables needed to perform the selected
operation(s). This may include intermediate results, flags, and control signals.

3. Write the Verilog code for the ALU logic using case or if statements to handle
different operations:

 For arithmetic operations (e.g., addition, subtraction, multiplication,

division), use Verilog's arithmetic operators (+, -, *, /) to compute the
result.

 For logical operations (e.g., AND, OR, XOR), use Verilog's bitwise
operators (&, |, ^) to compute the result.
  For shift operations (e.g., left shift, right shift), use Verilog's shift operators
(<<, >>) to compute the result.

 Update any flags or control signals as needed.

4. Define the module using the module keyword and include the input and output
Instantiate the module in your Verilog design hierarchy, connecting the input and
output ports to signals or other modules.

5. Create a test bench to verify the functionality of the ALU by generating input
stimuli, applying them to the input ports of the module, and monitoring the
output. Use $display or $monitor statements to print out the values of the input
and output signals.

6. Compile and simulate the design using a Verilog simulator like ModelSim or
VCS.

7. Debug the simulation by examining the waveforms to ensure the module behaves
as expected.

8. Synthesize the design using a synthesis tool to create a hardware implementation

ports.

Software Simulation