2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

4-Bit Arithmetic Logic Unit That Uses Adjustable

Threshold Pseudo-Dynamic Logic
Aman Agarwal
Department of Electronics and
Communication Engineering
Delhi Technological University
(formerly Delhi College of
Engineering)
Delhi, India
Email: amanagarwal702@gmail.com
Avijeet Kumar Trivedi
Department of Electronics and
Communication Engineering
Delhi Technological University
(formerly Delhi College of
Engineering)
Delhi, India
Email: avijeet.trivedi@gmail.com
Chirag Parashar
Department of Electronics and
Communication Engineering
Delhi Technological University
(formerly Delhi College of
Engineering)
Delhi, India
Email: mechiragp1997@gmail.com

Neeta Pandey
Department of Electronics and
Communication Engineering
Delhi Technological University
(formerly Delhi College of
Engineering)
Delhi, India
Email: neetapandey@dce.ac.in

Abstract— In this paper, in order to improve the
performance and power dissipation of a chip, we present an
Arithmetic and Logic Unit (ALU) using the "Power-
performance tunable Pseudo-Dynamic topology”. To achieve
this, we have designed basic logic gates such as AND, OR and
XOR. The general idea of the logic was inspired from the
pseudoϋdynamic logic [1]. The input and output of this logic
are compatible with static gates and can replace them with
pseudoϋdynamic gates. The pulse generation in the
intermediate nodes decreases the power dissipation. This logic
uses skewing supply voltage to tune the threshold voltage which
provides performance and power dissipation controllability.
Although owing to the larger number of transistors used for the
same functionality, pseudo-dynamic topology acquires a larger
footprint as compared to static CMOS topology, but its delay
and overall power dissipation is certainly better than Static
CMOS logic.
For carrying out our simulations and transient analysis, we
used Cadence® Virtuoso® Schematic Editor and ADEL
Simulator.
Keywords—Pseudo-Dynamic Logic, Pseudo-Static Logic,
Cadence Virtuoso, Tunable threshold, Power-Delay Product.
I. INTRODUCTION
An ALU (Arithmetic and Logical Unit) is a vital part of
almost every computing device be it microprocessors,
computers, embedded designs etc. All these devices have
great application in the field of consumer electronics. An ALU
is a combinational digital circuit used to perform arithmetic
and logic operations on binary numbers. It represents the
fundamental building block of the processing unit. As all the
above-mentioned devices execute various operations, an ALU
becomes a device which is used very frequently in a system
[6], and thus must be made as efficient as possible.
added benefit of taking both delay as well as power into
account, with a lower PDP being a desirable criterion [3].
The majority of the circuits designed today use static
CMOS logic because of its inherent advantages, such as low
static power dissipation, high noise margins, and large fan-
out capability. Though newer technologies are always being
worked upon in hopes of obtaining a better design. General
structure of static CMOS based logic is shown in Fig. 1.
Obtaining energy efficient design while maintaining
computational performance is one of the main pursuits of
contemporary processor design. While scaling of transistor
dimensions has long been a source of performance
improvements in circuits, a corresponding increase in leakage
current for decreasing technology nodes is present. With each
process shrinkage, the leakage power dissipation becomes a
greater component of the total power dissipation. Hence
leakage power should not be neglected, and designs which
lower the static power dissipation while maintaining
functionality and performance should be pursued. Apart from
the circuit topology, another method used to reduce the static
power dissipation is threshold voltage alteration. An increase
in threshold voltage reduces the static power dissipation and
decrease in threshold voltage results in increase in speed. A
popular method used for changing the threshold voltage of a
transistor is to use substrate-bias effect. Due to this effect, any
difference between the substrate and source voltage leads to
a change in the threshold voltage.

The quality of a circuit is judged on the basis of a few

performance metrics such as speed (delay), power and area.
A combined parameter known as power-delay product (PDP)
is also used to gauge the quality of a design. PDP has the
Fig. 1: Static CMOS logic general structure [3]

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

II. RELATED WORK In currently existing literature [1], buffer, AND, OR and
In the majority of designs, there exists a trade-off between XOR gates have been designed using the pseudo-dynamic
power, delay and area. Usually this tradeoff is decided at the logic. These circuits offer the same functionality as pseudo-
time of manufacturing and cannot be altered later. In contrast static circuits while reducing the number of transistors used
to these designs, a logic family known as “pseudo-static for same fan-in and thus having a smaller area. The pseudo-
logic” [2] was introduced. A top level block diagram of dynamic circuits also exhibit a lower power-delay product
pseudo-static logic is shown in Fig. 2. Its path 1 propagates than their pseudo static-counterparts, effectively behaving as
the rising input transition and path 2 propagates the falling a better alternative to them.
input transitions. The weak path (path 3) at the bottom
prevents the gates from becoming meta-stable and holds the
output when the driving path is being reset. It allows the user
to adjust the performance and power dissipation by adjusting
ǻV (skew voltage). For positive ǻV, the overdrive voltage
for the static OPL (Output Prediction Logic) block [5]
decreases, resulting in increase in effective threshold voltage.
This leads to lesser power dissipation and increased delay.
Similarly, for negative ǻV, effective threshold voltage
decreases resulting in increased power dissipation and
smaller delay. This tunability provides a wider range of
power-performance points for a design.

Another logic family, called adjustable threshold pseudo-

dynamic logic family [1] was proposed in 2018. A top level
block diagram of pseudo-dynamic logic is shown in Fig. 3.
This logic structure was inspired by the pseudo-static logic
and uses lesser number of transistors than it. The pseudo-
static logic uses static OPL blocks that includes both pull up
(PU) and pull down (PD) for each stage. The primary idea for
decreasing the area in pseudo-dynamic logic is to replace the
static OPL blocks used in pseudo-static logic with the
dynamic one. In pseudo-dynamic logic the PD and PU of the
CMOS are used in the first and the second stages
respectively. Because of the dynamic OPL block used
pseudo-dynamic logic family also incorporates tunability Fig. 2: Pseudo static logic general structure [2]
property in the same way as it is explained for the pseudo-
static logic. Due to this tunability property, we can obtain a
lower static power dissipation at the expense of reduced
speed by increasing the threshold voltage, while increased
speed can be obtained at the expense of increased static power
dissipation by reducing the threshold voltage.

The pseudo-dynamic logic has pulses propagating in the

internal nodes of the circuit while the external nodes operate
with the same voltage levels as that of static CMOS circuits.
The pulse generation in the intermediate nodes decreases the
power dissipation, and since the external node signals are
same in both static CMOS as well as pseudo-dynamic logic,
they can be interchanged in a design without any
modifications.

There are two different paths responsible for propagating

the rising and falling input transitions. By combining the
outputs of both the paths to a single output, the output node
gets updated by either of the paths whenever an input
transition occurs, while the other path’s node signal remains
unchanged. This leads to pseudo-dynamic circuits having the
same activity factor as their static CMOS counterparts,
consequently resulting in both logics having the same
dynamic power dissipation.

Fig. 3: Pseudo dynamic logic general structure [1]

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

III. PROPOSED WORK

An ALU structure comprising of arithmetic and logic
functions was designed using the pseudo-dynamic logic in an
attempt to reduce the power dissipation, obtain better
performance and also introduce tunability in the design. For
this, initially the logic gates such as AND, OR, XOR were
designed using the pseudo-dynamic logic (Fig. 3). These
logic gates were then used to design the basic sub-blocks of
an ALU such as multiplexers and full adders. The logic gates
and sub-blocks were then connected to form the arithmetic
block and logic block. A concatenation of these blocks’
output through a 2:1 multiplexer formed the desired 4-bit
ALU.

The schematic of designed 4-bit ALU is shown in Fig. 4.

In order to compare the performance of ALU designed using
pseudo-dynamic logic with that of static CMOS logic, the
same ALU was also designed using the static CMOS logic by
using the basic logic gates based on static CMOS logic. The
goal was to obtain a design offering more power efficiency as
well as better performance. To obtain the comparison,
simulations were carried out to verify the functioning and
measure static power dissipation and performance in
Cadence® environment. Fig. 4: ALU schematic

The truth table for ALU is given in table 1. It has four Table 1: ALU FUNCTIONALITY
select lines, namely S3, S2, S1, S0. If S3 is low, arithmetic S3 S2 S1 S0 F FUNCTIONALITY
operations are carried out while if S3 is high, logic operations 0 0 0 0 A+B Add
are carried out. By applying proper values to the select lines, 0 0 0 1 A+B+1 Add with carry
arithmetic operations such as addition, addition with carry,
0 0 1 0 A-B-1 Subtract with borrow
subtraction, subtraction with borrow, increment, decrement,
0 0 1 1 A-B Subtract
transfer and logic operations such as complement, AND,
NAND, OR, NOR, XOR, XNOR can be performed. An 0 1 0 0 A Transfer A
additional operation to reset the output lines of ALU is also 0 1 0 1 A+1 Increment A
provided. 0 1 1 0 A-1 Decrement A
0 1 1 1 A Transfer A
The gates designed using pseudo-dynamic logic are
1 0 0 0 1 All 1
expected to consume lesser power and provide faster
operation as compared to the static CMOS logic, owing to its 1 0 0 1 A' Complement A
internal pulse generation. The width of evaluation transistors 1 0 1 0 A ‫؞‬B AND
is kept high to provide faster operation while the width of 1 0 1 1 (A ‫؞‬B)’ NAND
other transistors is kept small in order to reduce the static 1 1 0 0 A ‫؞‬B OR
power dissipation. 1 1 0 1 (A ‫؞‬B)’ NOR
1 1 1 0 AْB XOR
A skew voltage, ǻV was also applied in the supply rails of
the dynamic-OPL blocks of the logic gates designed using 1 1 1 1 (A ْ B)’ XNOR
pseudo-dynamic logic (Fig. 3). It is expected that for more
positive skew voltage applied in VDD and VSS, static power
dissipation would reduce and propagation delay would IV. RESULTS
increase due to a higher effective threshold voltage of the Simulations were carried out using 180nm technology in
evaluation transistors. Similarly, for smaller skew voltages, Cadence® Virtuoso® for static CMOS and pseudo-dynamic
static power dissipation would increase and propagation logic. Results obtained are given in table 2-5. Table 2 shows
delay would reduce due to a reduction in the effective the delay, power, and PDP for the basic logic gates designed
threshold voltage of the evaluation transistors. using both static CMOS logic as well as pseudo-dynamic
logic with zero skew (ǻV = 0). The results obtained verifies
By using the logic gates designed with pseudo-dynamic that the logic gates designed using pseudo-dynamic logic
logic to build the ALU, we expect to obtain power and delay consumes lesser power and provides faster operation as
tunability by controlling the skew voltage in larger designs of compared to those designed using the static CMOS logic.
pseudo-dynamic topology as well. Multiplying both propagation delay and power dissipation,
we get power-delay product (PDP). PDP in pseudo-dynamic

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

logic gates come out to be substantially lesser than that of

static CMOS logic gates. Table 3: COMPARISION OF STATIC CMOS AND PSEUDO-DYNAMIC ALU

The simulation results obtained for logic gates when skew Unit Topology Average Average PDP
Delay Power (fJ)
is introduced are given in table 4. The skew voltages (ǻV) at (ns) (ȝW )
which the outputs were taken are -0.1, 0, 0.1, 0.2 and 0.3. A Arithmetic Static
graphical representation for the same is provided in Fig. 5. Functions CMOS 1.1753 8.6390 10.1532
From the graphs obtained for OR gate, it can be observed that Pseudo-
introduction of skew further reduces the static power Dynamic 0.8262 8.9820 7.4209
dissipation by up to 30 percent, delay by up to 10 percent and Logic Static
PDP by up to 15 percent. Similar trends are also observed for Functions CMOS 0.8390 3.3380 2.8006
AND and XOR gates. Pseudo-
Dynamic 0.3924 3.5118 1.3779
Since, the arithmetic and logic unit is an interconnection
of these basic logic gates, the PDP of the ALU designed using Table 4: POWER AND SPEED FOR DIFFERENT SKEW OF LOGIC GATES
pseudo-dynamic logic is expected to be lower than that
Average Delay Average PDP
designed using the static CMOS logic. This is verified by the Gate Skew (ns) Power (ȝW) (fJ)
simulation results given in table 3. The results for pseudo- 0.905 0.0733
OR -0.1 0.081
dynamic logic in table 3 are taken at zero skew voltage (ǻV).
0.0 0.090 0.267 0.0240
The simulation results of the pseudo-dynamic ALU with
skew are given in table 5. The same skew voltages are applied 0.1 0.098 0.230 0.0225
for the ALU as well. Since in the ALU, the number of 0.2 0.104 0.203 0.0211
possible input combination is equal to 2n, the delay and power 0.3 0.110 0.187 0.0205
will be different for different set of inputs. In our analysis, we AND -0.1 0.062 0.198 0.0122
have carried out simulations for the worst case. Worst case 0.0 0.079 0.173 0.0115
for delay means that we have taken inputs such that the carry 0.1 0.083 0.161 0.0134
is propagated to the most significant bit of the design. In case 0.2 0.094 0.151 0.0142
of power calculation, we have maximised the number of bits 0.141 0.0140
0.3 0.099
being toggled for the worst case value. The reported readings
XOR -0.1 0.111 1.386 0.1544
are the average of the delay and power dissipation for all the
arithmetic and logic operations respectively. A graphical 0.0 0.115 1.287 0.1484
representation for the same is provided in Fig. 6. The same 0.1 0.161 1.197 0.1931
trend is observed for the ALU that was there in basic logic 0.2 0.169 1.078 0.1818
gates. 0.3 0.176 0.936 0.1650

The metric in which pseudo-dynamic loses out to static Table 5: POWER AND SPEED FOR DIFFERENT SKEW OF ALU
CMOS is that of area. The pseudo-dynamic logic uses larger Average Average PDP
number of transistors for achieving the same functionality for Unit Skew Delay (ns) Power (ȝW) (fJ)
same number of fan-in, which leads to this logic having a Arithmetic
larger area as compared to static CMOS logic. The pseudo- Functions -0.1 0.757 9.786 7.4034
dynamic logic has a greater transistor count for achieving the 0 0.826 8.982 7.4209
same functionality and fan-in than that of static CMOS. 0.1 0.900 7.477 6.7319
Transistor count for different logic gates are given in table 6.
0.2 0.977 7.076 6.9129
Fan-in for all the gates in table 6 is 2. It is clear from the table
that the better PDP and tunabilty feature comes at the cost of 0.3 1.058 6.945 7.3506
more area on-chip per logic. Logic
Functions -0.1 0.618 7.632 4.7202
Table 2: POWER, DELAY AND PDP OF STATIC CMOS AND PSEUDO- 0 0.673 2.978 2.0048
DYNAMIC LOGIC GATES 0.1 0.730 2.644 1.9301
Cell Topology Delay Power PDP (fJ) 0.2 0.783 2.383 1.8659
(ns) (ȝW ) 0.3 0.828 2.297 1.9008
OR Static
0.109 0.286 0.0312
CMOS
Pseudo- 0.090 0.267 0.0240 Table 6: NO. OF TRANSISTORS USED IN EACH TOPOLOGY
Dynamic
AND Static No. of
0.067 0.234 0.0156 Cell Topology
CMOS Transistors
Pseudo- 0.079 0.173 0.0115 OR Static CMOS 6
Dynamic Pseudo-dynamic 18
XOR Static AND Static CMOS 6
0.131 1.233 0.1610
CMOS Pseudo-dynamic 18
Pseudo- 0.115 1.287 0.1484 XOR Static CMOS 8
Dynamic Pseudo-dynamic 30

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)
V. CONCLUSION
The propagation delay obtained in all the circuits designed
using pseudo-dynamic logic is smaller in comparison to static
CMOS logic for the worst case analysis. The domain in which
pseudo dynamic logic shines is the propagation delay metric,
due to which the power-delay product of pseudo-dynamic
logic is consistently lower than both static CMOS and
pseudo-static logic. Also, the tunabilty offered by this
topology can be exploited in mobile phones and laptops.
(a) Propagation delay of Logic gates wrt skew voltage
(b) Static power dissipation of Logic gates wrt skew voltage
Fig. 5: Variation of propagation delay and static power dissipation for
different skew voltages in pseudo-dynamic based logic gates
(a) Propagation delay of ALU wrt skew voltage
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(b) Static power dissipation of ALU wrt skew voltage
Fig. 6: Variation of propagation delay and static power dissipation for
different skew voltages in the ALU
For applications which demand real time processing, the CPU
can be tuned for high performance whereas applications that
do not require fast processing, circuits can be tuned for power
efficiency.
Although owing to the larger number of transistors used for
the same logic functionality, pseudo-dynamic topology
acquires a larger footprint as compared to static CMOS
topology, but still lesser when compared to pseudo-static
logic. All the resulting data points to the pseudo-dynamic
logic being objectively better than static CMOS topology
when area is not of concern.
As seen from the graphs, by varying the applied skew
voltage, we can operate our circuits at a range of operating
points by either finding an optimal balance between power
dissipation and delay or by operating at points that favour
either power dissipation or delay depending on the workload.
With every subsequent decrease in technology node size,
the amount of total power made up by static power keeps on
increasing. Due to which adopting this logic to design circuits
with ever shrinking node sizes can be beneficial, allowing the
user to have the advantages of both low power dissipation as
well as faster processing.
VI. REFERENCES
[1] Gha arishad H, Mohammadzadeh N, Ghaznavi Ghoushchi M B. A
power performance tunable logic with adjustable threshold pseudo
dynamic building blocks and CMOS compatibility. Int J Circ Theor
Appl. 2018.
[2] Nezamfar B, Alon E, Horowitz M. Energy performance tunable logic.
IEEE Journal of, Solid State Circuits. 2009;44(9):2554 2567.
[3] Rabaey JM, Chandrakasan AP, Nikolic B. Digital Integrated Circuits.
2 Englewood Cli s: Prentice Hall; 2002.
[4] Kang S M, Leblebici Y. CMOS Digital Integrated Circuits. New
York: Tata McGraw Hill Education; 2003.
[5] L. McMurchie, et al., “Output Prediction Logic: A High-Performance
CMOS Design Technique,” Proc. ICCD, pp. 247-254, Sept., 2000.
[6] Mano, Morris M. Computer System Architecture, 3e: Pearson
Education Inc; 2007.