2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)

Bangalore, India. Oct 7-9, 2022

An Energy-Efficient Conditional-Boosting Flip-Flop

with Conditional Pulse for Low Power Application
Dipali Patidar, Alok Kumar Mishra, Dhandapani Vaithiyanathan and Baljit kaur
Department of Electronics and Communication Engineering
National Institute of Technology Delhi, Delhi. India
dipalipatidar1@gmail.com, alokmishra014@gmail.com, dvaithiyanathan@nitdelhi.ac.in, baljitkaur@nitdelhi.ac.in

Abstract—Along with size and performance considerations,
power consumption is regarded as a significant challenge in
current VLSI design. In digital systems, the flip flop is an
extremely significant clocked timing element. An energy-
efficient conditional-boosting flip-flop with a conditional pulse
is proposed for low power applications. The proposed flip-flop
2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT) | 978-1-6654-6855-8/22/$31.00 ©2022 IEEE | DOI: 10.1109/GCAT55367.2022.9972127
threshold can be unacceptable. Parameters like delay, hold
time and setup time can be reduced and cause more variation
if components like flip-flop and latches [3]– [7] that are basic
components in synchronous systems operating on higher
speed use the voltage near the threshold voltage, causes the
unacceptable effect on the performance of the whole system.

allows voltage - boosting to achieve low delay. It allows

conditional capture to reduce switching power consumption by
removing unwanted boosting operations. It also allows
conditional pulse generation to eliminate unwanted pulses
resulting in less switching power consumption. Simulation
results in a 90-nm CMOS technology represented that the
proposed flip-flop delivered up to 34% lower delay and 53%
better energy-delay product at 25% data switching activity
compared with the conventional conditional-boosting flip-flop.
Capacitive boosting [8]– [11] may be a viable option for
dealing with the issues produced by aggressive voltage
scaling. It enables some MOS transistors to have their gate-
source voltage raised above or below the supply voltage. The
improved transistor driving capabilities acquired thus can
reduce delay and its sensitivity to process fluctuations.
A. Basic Capacitive Boosting Technique

Keywords—Bootstrapping, flip-flops, conditional pulse, low

This approach is used in the boosted CMOS driver
power. introduced in [8] for driving the large capacitive outputs
providing much-decreased delay. The basic bootstrapping
mechanism utilized in a CMOS driver circuit which drives
I. INTRODUCTION large load is represented in Figure 1 [8]. The bootstrap circuit
Nowadays, Portable electronic devices are extremely is divided into two sections for pull-down and pull-up
used in our daily life. It requires energy-efficient operations, as indicated in the diagram. The boosted pull-up
computation to get a long operation time with a less power operation is performed with capacitor Cbp and NMOS
budget. In high-performance digital systems such as devices N1b/N2b, whereas the boosted pull-down operation
microprocessors, digital signal processors (DSPs), and other is performed with capacitor Cbn and PMOS devices
applications, the necessity for low-power design is becoming P1b/P2b. Because it's a static driver, though, every input
a critical challenge. However, an increase in chip density and transition triggers the boosting process. As a result, if some
speed of operation results in a very complex chip design with transitions are unwanted, there could be a significant amount
a higher clock frequency. And if the clock frequency of unwanted power usage.
increases then power dissipation and temperature of the chip
also increase linearly. In a digital VLSI system, flip-flops are
important building components. Registers, pipelines, and
state machines for data sequencing are some of the
application areas where flip flops are commonly used. The
power consumption and speed of a VLSI system are directly
affected by flip-flops. Because of the redundant transitions
and clocking system contained in flip flops and latches, they
utilize more power. As a result, our goal is to design flip-
flops that are both high-performing and energy-efficient [18-
20].

II. LITERATURE SURVEY

One of the most successful methods for reducing the
power consumption of CMOS digital circuits is voltage
scaling[1]. But, extensive scaling in voltage, used for
computation at the sub-threshold level, results in significant
speed loss. Near-threshold computing appears to be a
potential method for minimizing energy while considering
delay[2]. However, high speed and low power is required in
Fig. 1. Basic Capacitive Boosting Technique used for CMOS driver [8].
most of the application and more delay and variation in
performance of circuits which operates on voltage around

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B. Conditional-Boosted Latched CMOS Driver
To decrease unnecessary power usage, the conditional-
boosting latching CMOS driver [9] presents the conditional
boosting concept. The basic form of the proposed drivers, the
conditional-boosting latched CMOS driver, is shown in Fig.
2. (CBLD). UP and DN are the two inputs. The first is an
active-high input that indicates output pull-up, while the
second is an active-low input that indicates output pull-down.
These inputs are triggered one at a time, and they cannot be
active at the same time. Because it's act as latched driver, it
can only boost when the given input and previously stored
output logic values are not the same, which indicates no
boosting, and ultimately energy is saved for low switching
activity.
Fig. 2. Conditional-boosted latched CMOS driver [9].
C. Boosted Dynamic Logic Circuit
Figure 3 depicts a Boosted Dynamic Logic Circuit
introduced in the paper [10]. Because of lower internal
parasitic capacitances, the speed performance of CMOS
dynamic logic circuits is superior to that of CMOS static
logic circuits at low supply voltage. However, because the
serial fan-in is huge, the propagation delay connected with it
may dramatically increase, which is especially problematic at
low supply voltage. It's crucial to figure out how to improve
the speed of CMOS dynamic logic circuits. This research,
provided a CMOS booster circuit that can be utilized to
improve the driving capabilities of the following stage in a
CMOS dynamic logic circuit, hence improving its switching
time.
Fig. 3. Boosted CMOS Dynamic Logic Circuit [10].
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D. Conditional-Boosted Flip-Flop (CBFF)
In digital systems, the flip flop is extremely significant.
The conditional boosting flip-flop (CBFF) [11], which
employs conditional capacitive boosting, has a low EDP and
lower DQ latency. Its operation requires an explicit brief
pulse generator, which results in redundant pulse creation at
reduced data switching activity and increases switching
power consumption. The pulse generator required for this
flip-flop and its timing diagram is shown in figure 4 and 5
respectively.
Fig. 4. Pulse generator used in CBFF [11].
Fig.5. Timing waveform of CBFF [11].
III. PROPOSED CONDITIONAL-BOOSTING FLIP-FLOP WITH
CONDITIONAL PULSE
A. Working Principle
The proposed flip-flop CBFF-CP uses the concept of
conditional boosting same as CBFF [11], in addition, it
allows conditional pulse generation to remove unwanted
pulse generation when data activity is low which results in
less energy consumption for lower data switching activity as
compared to CBFF. Four possible possibilities for input data
capture should be addressed when introducing a precharged
differential flip-flop with conditional boosting, which are
dictated by logic values of the input and output. The
following are the scenarios:
1) for quick capture of incoming data, a high value of
input data should activate boosting for a low value of output
data;
2) low input data should not trigger boosting for low
output data because the input does not need to be captured.;
3) for quick capture of incoming data, low value of input
data should activate boosting for high value of output data.;
4) high input data should not trigger any boosting for
high output data.
 Using only one boosting capacitor and two working
principles, these possibilities can be represented in a circuit
design. One is that the data saved at the output must be used
to determine the presetting of voltage for the capacitor's
boosting terminals (called output-based presetting). The
second principle, depending on the input data applied to flip-
flop, boosting operation should be performed ( called input-
based boosting). Figure 6 depicts the conceptual schematic
diagrams that support these principles. As illustrated in Fig.
6, the pre-set voltages of capacitor terminals P and PB are
decided by the Q and QB outputs to facilitate output-based
presetting (a). P and PB are set to low and high, respectively,
if Q and QB are low and high [in Fig. 6(a) left diagram],
while P and PB are set to high and low, respectively, if Q and
QB are high and low [ in Fig. 6(a) right diagram]. To
perform the input-based boosting, As indicated in Fig. 6, the
D input (non-inverting) is connected to PB via NMOS
transistor, and DB input (the inverting) is connected to P via
other NMOS transistor to achieve input based boosting (b).
A high input permits PB to be dragged below ground and
causes the voltage at P to go -VDD because of capacitive
coupling [in Fig. 6(b) upper left diagram]. This is one
instance when low data value is saved in flip-flop,
performing presetting in capacitor seen in Fig. 6(a)[in the
left diagram]. Meantime, P is connected to the ground
because of low input, but because the node P is previously
set to VSS, voltage change does not occur at PB, thus
boosting is not done [in Fig. 6(b) bottom left diagram]. A
low input causes P to be dragged below ground, and causes
the voltage at PB to go -VDD because of capacitive coupling
[in Fig. 6(b) lower right diagram], as in the other situation
when high value data is saved in flip-flop, pre-setting at
capacitor terminals is achieved shown in Fig. 6(a) [in the
right diagram].
(a)
(b)
Fig. 6. [11] Conceptual schematic diagrams; fig (a) output data-based
presetting, fig (b) input data-based boosting.
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TABLE I. DATA-BASED BOOSTING AND PRESETTING
Meantime, because of a high value input, PB should be
connected to the ground but because node is previously set to
VSS, the voltage at P remains the same, thus no boosting
occurs [in Fig. 6(b) upper right schematic]. For ease of
comprehension, Table I outlines these operations. Any
unwanted boosting can be removed using these processes,
resulting in a less power dissipation, mainly for low data
switching activity.
B. Circuit Implementation
Figure 7 depicts the schematic of the suggested
conditional-boosting flip-flop with a conditional pulse
(CBFF-CP) based upon the preceding section's assumptions.
It includes a differential stage with conditional
bootstrapping, asymmetric latch, and a conditional pulse
generator. P5/P6/P7 and N8/N9 are utilized to perform
output-based presetting in conditional-bootstrapping
differential stage represented in Fig. 7(a), while N5/N6/N7
with boosting capacitor Cb is used to do input-based
boosting. The symmetric latch is made up of P8–P13 and
N10–N15, as seen in Fig. 7. (b). A short-pulsed signal CPS
is created through a unique conditional short pulse generator
depicted in Fig. 7(c) that is used to operate some transistors
in fig 7 (a) differential stage. The proposed pulse generator
uses a conditional pulse generation technique, it consists of
two blocks one is a clock selection circuit and the other is a
pulse generator circuit. The clock selection block is used to
generate conditional pulse, it is done based on applied data
input (D), the need for pulse generation is only when D
changes as shown in the timing diagram. At lower switching
activity of input D, some pulse operations are redundant,
contributing to switching power consumption. This block
consists of a AND logic gate (G1) where clock (CLK) and
enable (EN) are applied as an input to G1. When EN is low,
the output (GCLK) of G1 is low and the output (CPS) is
also low, resulting in no pulse generation as long as the
input (EN) is low. For the duration when EN is high, the
entire clock signal appears across the output of G1 and it is
an input for the pulse generator circuit. PMOS Keeper is not
used in this pulse generator circuit to sustain a high value
for PSB which is achieved by P1 connected in parallel to
N1, also helps in achieving a quick pull-down of PSB. PSB
is quickly discharged by N1, P1, and I0 at the rising edge of
GCLK, allowing CPS to be high. PSB is charged by P2 after
the latency of I1 and I2, and CPS goes to low, producing
short positive pulse at CPS with a width dictated by the
delay of I1 and I2. P1 keeps PSB high when GCLK is low,
even while P2 is turned off.
 Fig. 8. Timing waveform of the proposed CBFF-CP.

(a) Fig. 8 represents the timing waveform of the proposed

CBFF-CP flip-flop. Let's pretend that Q output is low while
the clock (CLK) is low, to explain the operation. RBN is then
set to high due to the activation of P5 and P7, whereas LBN
is set to low because of the activation of N8 (output-based
presetting). Depending on the input data D, LBN (RBN) will
make the connection to either node SB (RB) or VSS when
CPS rises following the rising edge of CLK. Because D is
high (not the same as Q), RBN is dragged below VSS by N6
and N7, while LBN, which is coupled to SB by N1 and N3,
is pulled below VSS through Cb by capacitive coupling, as
seen in the first cycle in Fig. 8. (Input-based boosting). The
driving strength of N1 and N3 is increased, and SB is pulled
down quickly as a result of this action. Due to small forward
body bias generated by the negative voltage at LBN, VTH is
reduced, which also helps to increase the driving capacity.
Furthermore, the negative enhanced voltage supplied to SB
increases the driving capability of the PMOS transistors in I1
and also in P8 in the symmetric latch, causing a quick Q pull-
up. Because QB is now low, LBN is preset high through P5
and P6 on the following falling CLK edge, allowing preset
low at RBN by N9 (output-based presetting). P3 also pre-
(b) charges SB to a high level. Let us understand the behavior in
Fig. 8 (in second cycle), in which D is sustained to be a logic
high value (same as Q). CPS remains low after rising Clock
edge because EN is low which blocks the CLK to appear as
an input to the pulse generator and hence no unwanted pulse
generation. However, because LBN and RBN are previously
at high and low logic values, input-based boosting is skipped,
and output remains the same. P1 and P2 maintain high levels
of SB and RB, to avoid leakage. A negative boosting occurs
at RBN in Fig. 8 (for the third cycle), when D is low and Q is
high, resulting in a quick pull-down of Q. and also pulse
generation is done for its operation while enabling the clock
to appear across pulse generator. Meanwhile, because D and
Q both are low, neither pulse production nor boosting is done
for the fourth cycle.
(c)
Voltage boosting, which enhances the driving capacity of
Fig. 7. Proposed CBFF-CP. (a) Conditional-bootstrapping differential transistors, reduces the delay of the proposed flip-flop
stage.[11] (b) Symmetric latch.[11] (c) Proposed conditional pulse significantly, as implied by the procedure described above.
generator.
This functionality is aided by increased transistor gate-source
voltage. A forward source to body voltage created in some of
transistors by pushing voltages at the source below ground
reduces threshold voltages, increasing driving strength even

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more. Furthermore, using output-based presetting and other
input-based boosting, only when stored and input data
differs, boosting is done. In addition to it, pulse generation is
also achieved only when the input and stored data are
different. As a result, high-power consuming unwanted
boosting operations and pulse production can be removed,
giving significantly increased energy efficiency, particularly
at low data activity.
IV. SIMULATION AND COMPARISON
The Proposed flip-flop CBFF-CP and other circuits like
CBFF [11], boosted CMOS driver [8], conditional boosted
latched CMOS driver [9] and boosted dynamic logic circuit
[10] are designed and simulated in 90nm technology. To
reduce EDP, in each circuit, the size of each device is
individually optimized.
A. Fundamental Capacitive Boosting Technique
Simulation waveforms for the pull-up and pull-down
operation of the CMOS driver (shown in fig. 1) are
represented in Fig.9 and Fig. 10 respectively. That represents
it performs the capacitive boosting for both pull-up and pull-
down operations. It allows the node voltage Vp1 (= -0.2V,
after boosting) to go below VSS for pull-up operation which
increases the driving capability of the P1 transistor. And the
node voltage Vn1 (= 1.75V, after boosting) goes beyond
VDD (= 1.5V) for pull-down operation which increases the
driving capability of the N1 transistor. Hence results in faster
charging and discharging of load capacitance CL.
Fig. 9. Simulation waveform for pull-up operation of boosted CMOS driver
Fig. 10. Simulation waveform for pull-down operation of boosted CMOS
driver.
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B. Conditional-Boosting Latched CMOS Driver
Simulation waveforms for the pull-up and pull-down
operation of the CMOS driver (shown in fig. 2) are
represented in fig.11 and fig. 12 respectively. That represents
it performs the capacitive boosting for both pull-up and pull-
down networks. It allows the node voltage NBP (= -0.35,
after boosting) to go below VSS for pull-up operation which
increases the driving capability of the P1 transistor. And the
node voltage NBN (=1.89, after boosting) goes beyond VDD
(=1.5V) for pull-down operation which increases the driving
capability of the N1 transistor. Hence results in faster
charging and discharging of load capacitance CL. Since it
performs conditional boosting that removes the unwanted
boosting operation resulting in the reduction of energy
consumption.
Fig. 11. Simulation waveform for pull-up operation of conditional boosted
latched CMOS driver.
Fig. 12. Simulation waveform for pull-down operation of conditional
boosted latched CMOS driver.
C. Boosted Dynamic Logic Circuit
The simulation waveform of the boosted dynamic logic
circuit (shown in fig. 3) is represented in fig.13. Capacitor
Cb0 is charged to VDD (=1.5V) during the precharge period
(when CLK is low). If both inputs (VINa and VINb) are high
during the logic evaluation phase (when CLK is high), the
internal node Vb0 (=2.2V, after boosting) is boosted to
above supply voltage VDD, increasing the output driving
capability of the circuit and as a result, the switching speed
of the following stage in the circuit gets enhanced.
 Fig. 15. Schematic diagram of Conditional-Boosting Flip-Flop with
Fig. 13. Simulation waveform of Boosted Dynamic Logic circuit. Conditional Pulse (CBFF-CP).

D. Conditional-Boosted Flip-Flop (CBFF)

The simulation waveform of CBFF [11] is represented in
fig. 14. The boosted voltage of -0.26V is achieved at SB and
RB resulting in the increased driving capability of transistors
P8 and P9, increasing the switching speed of output. Since it
performs the pulse generation at each rising edge of CLK
which is not required results in more energy consumption,
especially at lower data activity.

Fig. 16. Simulation waveform of Conditional-Boosting Flip-Flop with

Conditional Pulse (CBFF-CP).

TABLE II. PERFORMANCE COMPARISON OF FLIP-FLOP AT 1 V

Fig. 14. Simulation waveform of Conditional-Boosted Flip-Flop (CBFF).

E. Proposed Conditional-Boosting Flip-Flop with

Conditional Pulse (CBFF-CP)
The schematic diagram and simulation waveform of the
proposed CBFF-CP are represented in fig. 15 and 16
respectively. The boosted voltage of -0.27V is achieved at
SB and RB resulting in the increased driving capability of
transistors P8 and P9, increasing the switching speed of
output. Since it uses conditional pulse generation to remove
unwanted pulse generation, energy consumption is reduced
at low data activity. Table II represents the performance
comparison of CBFF and CBFF-CP. Figure 17 represents the
comparison of CBFF and CBFF-CP for simulated energy at
1 V for various data activities. Simulation results show that
the CBFF-CP provides 53% and 34% improvement in EDP
and DQ latency respectively at 25% data activity.

Fig. 17. Simulated energy at 1 V for various data activities.

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 V. CONCLUSION
A new CBFF-CP has been presented for application that
requires low power without serious performance
deterioration. The proposed CBFF-CP uses an energy-
efficient circuit for pulse generation, with the help of this, the
pulse can be generated only when it is required which means
at the lower data activity unwanted pulse generation can be
eliminated and results in less energy consumption. The
proposed flip-flop delivered up to 34% lower delay and 53%
better energy delay product at 25% data switching activity,
according to the analysis in a 90-nm CMOS process.
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