Proceedings of 2015 Global Conference on Communication Technologies(GCCT 2015)

A new Design Technique for Low Power Dynamic

Feedthrough Logic with Delay Element

 Arjun Dev  R. K. Sharma  Mayur Varshney

School of VLSI and Embedded system School of VLSI and Embedded system School of VLSI and Embedded system
Design Design Design
National Institute of Technology National Institute of Technology National Institute of Technology
Kurukshetra Kurukshetra Kurukshetra
Kurukshetra, India Kurukshetra, India Kurukshetra, India
arjunmadhavan.nair@outlook.com rksharma@nitkkr.ac.in er.mayurvarshney@gmail.com

Abstract—This paper presents a new approach for high
performance and low power circuit using a new CMOS logic
known as feedthrough logic (FTL). Feedthrough logic can
improve the performance by partial evaluation in its
computational block before getting a valid input. The FTL
is more suited for those circuits which consist of a critical
path of large cascaded inverting gates. FTL based circuit can
perform better in both high fan out and high frequency
operations due to both lesser delay and dynamic power
consumption at the cost of area. A 2 bit conventional
multiplier circuit with proposed model is simulated. The
proposed circuit achieves a reduction in the average power
and delay. The comparison analysis has been simulated by
180 nm CMOS technology. The proposed modified FTL
reduces total power delay product up to 22.85% in NAND
gates and 11.63% in NOR gates. The results of 2 bit
multiplier simulation also confirms that the proposed model
can perform with better as compared with existing models
of FTL with less transistor count.
Keywords—Feedthrough logic (FTL); dynamic CMOS logic
;low power; high performance
I. INTRODUCTION
Dynamic circuits have high performance and low power
consumption than static CMOS[1,2] which are being
increasingly used due to their compactness and introduction of
pre charge and evaluation phase using clock. However excessive
power dissipation due to switching and clock activities, less
noise margin due to charge leakage and charge sharing and
requirement of additional inverter for cascading are the major
drawbacks of this logic circuit. In order to reduce excessive
power dissipation in dynamic gate various power gating
techniques such as dual supply voltage and dual threshold
voltage [3, 4] are prosed in the literature.
A new logic family is introduced known as feedthrough logic
[5] which improves the performance of logic circuits basically
for having long logic depth with reduced power dissipation [6].
This logic works properly with domino concept for cascaded
logic, differential style and multiple output with iterative
networks has shown high design flexibility with the feature of
partial evaluation of output before getting a valid input. This
feature results in very fast evaluation of output in computational
block.
Major advantage of feedthrough logic [5] is which does not
require any additional circuits like keeper circuits for the
reduction of leakage power and FTL can be cascaded without
the use of inverters.
In this paper a modified FTL based dynamic circuit is
proposed for improved power reduction and better performance.
The power dissipation in CMOS logic is given by
P total = P static + P dynamic + P short circuit
Total power is the sum of static, dynamic and short circuit
power. Static power means the power dissipated when the power
supply is on. It is equivalent to the product of supply voltage and
leakage current. Dynamic power is the power dissipated due
switching activity. Dynamic power of a logic circuit is
proportional to capacitance of the node, total swing of voltage
and switching activity. Short circuit power is the power
dissipated due to short circuit current from supply voltage to
ground. It is equal to the product of supply voltage and total short
circuit current in that network.
II. PRINCIPLE OF OPERATION
The FTL in [5] consists of a pull up PMOS transistor (T P)
and NMOS reset transistor (T N) and a NMOS block. Both T N
and T P are clocked. The principle of FTL is as follows. As
shown in the fig 1(a) the output node is pulled to ground in the
high phase of clock (reset phase). When the clock become low
(evaluation phase) the output node conditionally evaluate either
logic high (V OH = V DD) or low (V OL). If all inputs are at logic
high then the output voltage will be remain in V OL otherwise
output is

978-1-4799-8553-1/15/$31.00 © 2015 IEEE 

Proceedings of 2015 Global Conference on Communication Technologies(GCCT 2015)

Fig 1. (a)basic structure of FTL, (b) transistor level circuit diagram for cascaded inverter using FTL (6 stages), (c) output voltage
from first stage (N1) to last stage (N6)

pulled up towards V DD. The FTL logic is much faster than other propagation delay is less as compared to FTL [5]. The main
logics because of following reasons: drawback of this model is the reset network needs a separate
design because the structure of reset network depends on the
1. This logic consists of a gradually reduced load due to input logic even though this circuit [6] can reduce the power
requirement of NMOS logic expression. consumption effectively. In the case of a cascaded NAND gate,
2. The output can be partially evaluated before getting a circuit cannot reset output in the reset phase. Output will be in
valid input. logic high and sometime it will be more than V DD. The
modified FTL [6] is failed to avoid the direct path problem when
3. The logic consists of a constant critical path (PMOS all inputs are at logic high. This problem directly affect the total
transistor) regardless the logic expression. power dissipation in the case of NOR gates.
A cascaded chain of inverter designed by using FTL is
shown in the fig 1(b). Output nodes are at logic 0 in the reset
phase (when clock=1). All the output nodes (N1, N2,
N3,…………., N6) rise to threshold voltage of gate V TH, when
clock goes from 1 to 0 as shown in the fig. 1(c). At this point a
small variation in the input can cause a fast variation in the
output node voltage. A partial transition at output node from V
TH to V OL or V OH takes place only after getting a valid inputs
at the gate terminal. Propagation delay of FTL is comparatively
less as compared to domino logic due to partial transition of
output node after the valid input where as in domino logic output
node makes the transition from either V OH to V OL or V OL to
V OH and domino logic use one extra inverter circuit for getting
the output. So total propagation delay is sum of input network
and the inverter circuit.
Despite the performance advantage of FTL it suffers a non-
zero short circuit current caused by the contention between
PMOS (T P1) and NMOS (T N1) during the switching of clock
and a direct path will exist when all inputs are at logic high. So
it create a chance for unlimited current flow from V DD to ground
other than short circuit current due to switching. This make more Fig 2 modified FTL with reset block.
dynamic power consumption by the circuit
The modified FTL [6] is shown in the fig 2. It consists an
additional PMOS transistor (T P2) in series with T P1 and reset
network in series with NMOS (T N1). This model can reduce the
contention problem as discussed above up to a limit and

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Proceedings of 2015 Global Conference on Communication Technologies(GCCT 2015)

III. PROPOSED MODIFIED FTL STRUCTURE FOR WIDE FAN IN

GATE

Proposed modified circuit is shown in fig 3. It consists of an

additional PMOS transistor (T P2) and NMOS transistor (T N2)
in series with T P1 and T N1 respectively. A delayed clock is
given to both T P2 and T N2 for reducing contention problem
during clock transition.
During switching of the clock from logic 1 to 0 and logic 0
to 1, both T N1 and T P1 will change first. Both transistors T P2
and T N2 change after a delay at which both T N1 and T P1 will
be in a steady state. So there will no short circuit current flow at
a point in which both T N1 and T P1 are in saturation due to
additional transistors (T P2 and T N2) with delayed clock.
Fig 4 delay element using fast inverters and transistors with
In this network no extra designs are needed as compared to high V TH
modified FTL [6]. The additional PMOS and NMOS transistors
and delayed network can be used with all other gates of this
particular logic. So amount of transistors needed for a cascaded
logic are tremendously reduced.
IV. DESIGN AND PERFORMANCE ANALYSISIS OF PROPOSED
STRUCTURES IN WIDE FAN IN GATES

A NAND gates and NOR gates designed by the

modified structure are shown in fig 3 and fig 4 are compared
with other proposed FTL models in [5] and [6]. The output will
be evaluated when clock input is at logic zero. NAND gate
structure is simulated by using 180 nm UMC CMOS process
technology at room temperature conditions. The power supply
(V DD) of all circuits for simulations is 1.8 V with 200 MHz
clock frequency.

I. 2 input NAND gate

Logic family Pavg T p (ps) Area of the
(μW) circuit (no of
transistors)
FTL in [5] 10.572 55 4
Modified FTL in [6] 6.42 60 7
Proposed modified 5.50 54* 6**
FTL
Fig 3 modified proposed FTL with delay element.
II. 2 input NOR gate
Logic family Pavg T p (ps) Area of the
Design of delay network (μW) circuit (no of
transistors)
Power loss due to short circuit is the major problem which is FTL in [5] 35.028 55 4
facing in modern CMOS technology. The delay network yields
to avoid short circuit current flow through PMOS and NMOS Modified FTL in [6] 19.96 59 7
during switching. The minimum delay for avoiding contention
problem is the time of short-circuit current. So we can design Proposed modified 18.7 56* 6**
delay element with transistors with high V TH [9] or fast FTL
inverters.

978-1-4799-8553-1/15/$31.00 © 2015 IEEE 

Proceedings of 2015 Global Conference on Communication Technologies(GCCT 2015)

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Fig. 5 Power delay product analysis of NAND abd NOR gates

Table 3 Simulation result of 2 bit multiplier

*/**-- exclude the delay and transistors of delay element
(common for all proposed model)
Logic family Pavg T p Area of the
(μW) (ps) circuit (no of
transistors)
Design of 2 bit multiplier
FTL in [5] 210 345 60
Two bit multiplier is an ordinary binary multiplier using
conventional technique. The basic cells of multiplier circuit are Modified FTL in [6] 128.56 380 96
designed by the proposed model to make a comparison with the
existing models. Proposed modified 111.25 350 84
FTL
Two bit multiplier designed by the proposed model is simulated
by UMC 180 nm CMOS technology with power supply 1.8 V.

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Fig 6 Two bit conventional multiplier circuit Fig 7 Power delay product comparison of 2 bit multiplier

978-1-4799-8553-1/15/$31.00 © 2015 IEEE 

Proceedings of 2015 Global Conference on Communication Technologies(GCCT 2015)
V. CONCLUSION
This paper consists of a low power dynamic circuit with
improved performance. The proposed technique reduces short
circuit current of dynamic circuit up to a large extend with the
help of delay elements. This technique will be more effective in
the case of NAND gates. The simulation of NAND gate result
confirms that the total power delay product is reduced by
22.85% with respect to modified FTL [6] and 48.88% with
respect to FTL [5]. The simulation of NOR gate shows that this
modified circuit can reduce total power delay product by 46.08%
with respect to FTL [5] and 11.63% with respect to modified
FTL [6].
The results of 2 bit multiplier simulation also confirms that
the proposed model can perform with better as compared with
existing models of FTL with less transistor count.
978-1-4799-8553-1/15/$31.00 © 2015 IEEE
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[1] J.M. Rabaey, A. Chandrakasan, B. Nikolic, ‘Digital Integrated Circuits:
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[2] S. M. Kang, Y. Leblebici, ‘CMOS Digital Integrated Circuits: Analysis &
Design’, TATA McGraw- Hill Publication, 3e, 2003.
[3] N. Weste, K. Eshraghian, ‘Principles of CMOS VLSI Design, A systems
perspective’, Addision Wesley MA,1988.
[4] A novel variation-aware low-power keeper architecture for wide fan-in
dynamic gates. Dadgour, H.F. ; Joshi, R.V. ; Banerjee, K.Design
Automation Conference, 2006 43rd ACM/IEEE, 2006.
[5] V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi, " Analysis
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Trans. Cir. & syst. II, vol. 54, no. 6, Jun. 2007, pp. 489-493.
[6] Performance analysis of modified feedthrough logic for low power and
high speed Sahoo, S.R.; Mahapatra, K.K. Advances in Engineering,
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Publication Year: 2012R.