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A Low-Density Power and Delay Testing of PTL and Gate Using 0.09µm
Technology

Conference Paper · April 2018

DOI: 10.1109/ICICS.2018.00026

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 A Low-Density Power and Delay Testing of PTL AND Gate using 0.09µm
Technology
1
Remalli Dinesh,2Sandeep Bansal, 3Cherry Bhargava*, 4Navjot Rathour, 5Raghav Gupta
1
PG Scholar, School of Electronics & Electrical Engineering, Lovely Professional University
2,3,4,5
Assistant Professor, School of Electronics & Electrical Engineering, Lovely Professional University
1
r.dinesh.in@ieee.org, 2sandeep.15732@lpu.co.in, 3cherry.bharagava@lpu.co.in, 4navjot.16885@lpu.co.in,
5
raghav.22026@lpu.co.in

Abstract— To augment the performance of the PTL AND gate
compared with that of basic AND gate cell with the need of low
power and delay which cause the advancement of
uncompromising designing approaches to bring down the power
consumption significantly. To endure the rising demand, we put
forward a low power PTL AND gate cell via forfeit the MOS
transistor reckon that shrink the severe threshold loss drawback,
considerably improve the speed and drop off the power while
relate with the static energy recovery of AND gate when used in
adder circuit. The present work links 1.8V, 1.7V, 1.6V, 1.5V,
1.4V, 1.3V, 1.2V, 1.1V, 1.0V MOS transistor PTL AND gate cells
in assessment of basic AND gate described in the research
literature. We have been worked out for power, delay and power
delay product values of all the cells using 0.09µm technology.
Keywords-PTL; MOS transistor; low power; delay; power delay
product; high speed; adder; AND gate.
I. INTRODUCTION
As we realize that, AND gate operation being applied in
every VLSI systems. Also, it is core of many other bit wise
arithmetic operation such as division, multiplication, address
calculation. In majority of these systems, it is component of
critical path that influence the global performance of the
system and in complex arithmetic circuit like full adder it is
one of central element. Optimized design for AND gates are
needed to raise the performance of complex circuits they are
being part of. So PTL AND gates were proposed for this
purpose and to avoid any deprivation on the output voltage,
devour a lesser amount of power, having less delay, and lower
power-delay product even with little voltage as in extreme
submicron or nanotechnology.
0.3µm [2]. It was basically an imperfect switch of single
PMOS or NMOS and in designing a logic circuit; it reduces
the number of surplus amount of transistor. PMOS or NMOS
transistor work as a switch such that it can adopt to pass logic
levels connecting nodes of a circuit, in its place of as switches
connected without delay to supply voltages [4]. However,
PTL’s benefit was not clearly understood by researchers in
deep submicron CMOS technology yet. This paper presents
results in 0.09µm CMOS process which confirmed that PTL’s
circuits offer up to 75% power and delay benefits in contrast to
conventional PTL.
This paper briefs on the properties of Pass-transistor in
Section 2 and Section 3 talks about the performance and
gives us an idea about how minor design changes influences
the final structure while Section 4 and 5 discuses about the
comparative analysis so obtained and conclude it
respectively.
II. THEORETICAL ANALYSIS
A. Pass-transistor Properties
The average power which was consumed by CMOS
switch is given by [2]
Pav = (Vdd)2. f.CL.Ai (1)
Parameters are summarized as:
Vdd : supply voltage;

f:operating frequency;
Since high speed, low power and less area are the most
significant design trade-offs requires in VLSI industry until CL: Load Capacitance experienced by the gate
speed has been compared with the performance factor [1]. The
need of low power circuits emerges from the revolutioned field Ai : Switching activity of gate
of portable gadgets in the present consumer market. With
power becoming a restrictive factor for the performance of a
Reduction in CL cause a definite impact on power
system, so call for low power circuits without forfeit circuit
consumption. Since the input capacitance of PTL gate was
performance is apparent [2]. Traditional static CMOS logic
minute as compared to that of static CMOS gate, so
gates used widely in today’s ASIC design due to its easy well-
interchanging CMOS gate with that of PTL gate should
organized synthesis and testing environment. The major
consequence in a diminution in the power use up [2].
attention achieved in the field of logic design was Pass
Transistor Logic (PTL), projected in [3]. The delay estimation of PTL was carried out by [5]:
td = τn.N2 (2)
PTL was well thought-out an alternative circuit design
technique for low power in CMOS technology of 0.5µm and Parameters of delay are described as:
τn : Time constant

N2 : Number of transistors arranged in series

III. DESIGN TESTING OF PTL AND GATES

A. Design Methodology
In this section PTL AND gates are designed with 2 NMOS
and 2 PMOS as shown in figure 1.

Figure 3. Output of PTL AND gate with power

Net3 and net4 are the pins A and B from where the input
voltage has been given to gate.

Figure 1. PTL AND gate Schematic designed in Cadence

As compared with PTL AND gate we can saw that in
traditional AND gate utilize more number of transistors as 3
PMOS and 3 NMOS was shown in figure 2.

Figure 4. Output of traditional AND gate with power

And the delay for PTL AND gate for figure1 was 20.08E-9
seconds and for traditional AND gate as shown in figure 2 was
evaluated to be 20.07E-9 seconds.

IV. COMPARATIVE ANALYSIS

Figure 2. Traditional AND gate Schematic designed in Cadence
B. Graph Based Simulation
The output voltage swing for PTL AND gate was 1.7V for
input voltage level of 1.8V and power consumption was
890.1E-9 watts as shown in figure 3. And the output voltage
swing for traditional AND gate was 1.8V for the input voltage
level of 1.8V and the power consumption was 894.0E-9 watts
as shown in figure 4.
A large numerical testing is performed to modify the gate
performance and a comparative analysis is presented for
power, delay and power-delay product between PTL AND gate
and Traditional AND gate. The obtained results are organized
in TABLE 1 and TABLE 2. It shows the vital performance of
the PTL AND gate in 0.09µm CMOS technology. Below Table
1 shows the comparison between two types of AND gates for
power trade-off factor.
 specific application where power and delay is the main factor
TABLE I . POWER CONSUMPTION ANALYSIS to consider while designing an application in VLSI circuits.
The design and development of low power circuits to reduce
Power of PTL AND Power of power consumption and delay which answer various technical
gate(watts) traditional challenges in application growth. It is necessary in terms of
Voltage(V)
AND commercializing VLSI circuits of low power.
gate(watts) ACKNOWLEDGMENT
1.8 890.1E-9 894.0E-9 The authors are genuinely acknowledging the research
1.7 693.7E-9 711.2E-9 scholars and associated members for assistance in VLSI
Design.
1.6 537.0E-9 562.1E-9
1.5 420.2E-9 441.9E-9 REFERENCES
1.4 313.6E-9 344.6E-9
[1] P.Divakara Verma, R.Ramana Reddy. A Novel 1-Bit Full Adder Design
1.3 235.5E-9 266.7E-9 Using DCVSL XOR/XNOR Gate and Pass Transistor
Multiplexers.International Journal of Innovative Technology and Exploring
1.2 174.5E-9 204.6E-9 Engineering (IJITEE);Vol. 2, No. 4, March 2013.
[2] Geun Rae Cho, Tom Chen. On Mixed PTL/Static Logic for Low-Power
1.1 127.0E-9 155.8E-9
and High-Speed Circuits. VLSI Design; Vol. 12, No.3, pp:399-406, 2001.
1.0 90.98E-9 117.2E-9 [3] D. Radhakrishnan, S.R Whitaker. Formal Design Procedures for Pass
transistor Switching circuits. IEEE journal of Solid-State Circuits; SC-20,
pp:531-536, April 1985.
[4] Rajkumar Sharma, Veerati Raju. Design and Performance analysis of
Now Table II shows the delay trade-off factor for the AND hybrid adders for high speed arithmetic circuit. International journal of
gates. VLSI Design and CommunicationSystems (VLSICS); Vol. 3, No. 3, June
2012.
[5] Weste, N. H. E. Principles of CMOS VLSI Design; A system perspective,
TABLE II. DELAY ANALYSIS Addison Wesley, 2nd Edition, 1993.
Voltage(V) Delay of PTL AND Delayof
gate(secs) traditional
AND gate(secs)
1.8 -20.08E-9 -20.07E-9
1.7 -10.07E-9 -10.06E-9
1.6 -10.11E-9 -10.06E-9
1.5 -10.11E-9 -10.05E-9
1.4 -10.04E-9 -10.05E-9
1.3 -10.03E-9 -10.04E-9
1.2 -10.01E-9 -10.03E-9
1.1 -10.01E-9 -10.02E-9
1.0 -10.1E-9 -10.0E-9

Negative sign indicates that PTL AND gates consume less

time and in contrast speed and performance is far better than
traditional AND gate. Also, if we calculate the power-delay
product and we find that it was also better for PTL AND gates.
V. CONCLUSION
A novel PTL AND gate analysis has been proposed for
power and delay which shows a wide range of values of power
and delay for discrete value of supply voltage. Also provide
optimum results for various voltage levels. The consequences
for different values of voltage shows that we can optimize

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