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Design of modified low power CMOS differential ring oscillator using sleepy
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Article  in  Analog Integrated Circuits and Signal Processing · May 2018

DOI: 10.1007/s10470-018-1205-6

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104
https://doi.org/10.1007/s10470-018-1205-6(0123456789().,-volV)(0123456789().,-volV)

Design of modified low power CMOS differential ring oscillator using

sleepy transistor concept
Prachi Gupta1 • Manoj Kumar1

Received: 12 May 2017 / Revised: 18 February 2018 / Accepted: 4 May 2018 / Published online: 10 May 2018
Ó Springer Science+Business Media, LLC, part of Springer Nature 2018

Abstract
As the technology feature size shrinks, leakage power is dominating in the total chip power consumption of VLSI circuits.
In this work to reduce the leakage power, sleepy transistor technique is used for differential ring oscillator (RO). First
design is proposed using CMOS inverter stage in a differential manner to form ring oscillator with sleepy NMOS and
sleepy PMOS transistors. Second design of differential ring oscillator is proposed with CMOS cross-coupled cell with
sleepy NMOS and PMOS transistors. Further, substrate-biasing concept has been applied to proposed design for
improvement in the power consumption. The power consumption for sleepy NMOS inverter stage differential ring
oscillator (RO) is 0.696–0.953 mW and the frequency of operation is 3.09–4.56 GHz. Sleepy NMOS cross-coupled based
ring oscillator design shows the power consumption of 0.78–1.21 mW at an operating frequency of 2.23–4.25 GHz. The
power consumption for sleepy PMOS inverter stage differential RO design is 1.95–2.04 mW and the frequency of
operation is 4.41–4.63 GHz. Further, sleepy PMOS cross-coupled RO design shows power consumption of 0.97–1.06 mW
at an operating frequency of 2.26–2.41 GHz. The substrate biasing of sleepy NMOS inverter stage ring oscillator design
gives power consumption of 0.862–0.924 mW and the frequency of operation is 4.16–4.45 GHz. Substrate biasing of
sleepy NMOS cross-coupled ring oscillator design shows power consumption of 1.06–1.16 mW and output frequency
varies from 1.86–2.05 GHz. The simulations have been performed using SPICE in 0.18 lm CMOS technology. Results of
power consumption, tuning range, phase noise, FoM and output frequency have been compared with earlier circuits and
proposed circuits show improvement in results.

Keywords CMOS  Differential delay cell  FoM  Leakage power  Phase noise  Ring oscillator  Sleepy transistor 
VCO

1 Introduction scaling of transistor has provided an increase in speed and

Voltage controlled ring oscillator (RO) is used in PLL for
frequency synthesis and clock and data recovery. Delay
cells are fundamental building blocks of VCOs. Ring
oscillators may be made of single-ended or differential
delay cells. Figure 1 shows a VCO architecture using
three-stage differential delay cell. Differential delay cells
can be implemented with inverter stages or cross-coupled
cells. In VLSI circuit design, some of the key parameters
are power, delay and area for CMOS technology [1]. The
& Prachi Gupta
prachigupta257@gmail.com
1
University School of Information, Communication and
Technology, GGSIPU, Delhi, India
frequency of operation giving higher performance but at
the same time power dissipation also increases [2, 3].
Power consumption, output frequency and phase noise
performance are the major design parameter for a VCO
circuit. LC oscillator shows better noise performance but
consumes the large layout area on the chip. CMOS based
oscillators are the prominent candidate for VLSI based
designs. Leakage current is a major contributor to the total
power consumption at lower technology feature sizes.
During switching of transistor in the circuit, dynamic
power is consumed. It was previously largest concern for
low-power chip designing. However, as the technology
feature size shrinks, the static power dissipation due to
leakage current becomes prominent which is also known as
stand-by power consumption. It becomes 30–40% of total

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88 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

power consumption at 180, 130, 90 nm technology

Vbias
whereas it may even exceed dynamic power dissipation at Vcontrol
65-nm feature size [4]. Threshold voltage, sub-threshold
leakage and gate-oxide leakage are the dominant sources of
leakage. As the technology feature size reduces, supply
voltage and threshold voltage also scale down [2] and the
sub-threshold leakage power increases exponentially.
Hence, supply voltage and threshold voltage need to be
optimized for low power and high performance [5]. In Fig. 2 Transistor biasing
the literature different type of VCO circuits have been
reported using variety of delay stages including single
ended and differertial stages [6–12]. Power consumption,
output frequency range and phase noise performance are VDD
the major design considerations in VCO circuits [13–22].
Total static power consumption in a CMOS circuit is HVT
Sleep
given by Eq. (1).
PTOTAL ¼ ISUB VDD þ IGATELEAKAGE VDD ð1Þ Virtual VDD
Pull-up
where ISUB is the sub-threshold leakage current, Network
IGATELEAKAGE is the gate-oxide leakage current and VDD is LVT
the power supply voltage.
The different techniques can be used to reduce power Output
dissipation in the stand-by mode of CMOS circuits such as Input
substrate biasing; source biasing; voltage scaling; sleep Pull-down
transistor; transistor stacking and sleepy stack transistor Network
[2, 3]. When a separate voltage source is used to bias the LVT
body or bulk terminal of a MOS transistor, it is called body
or substrate biasing as shown in Fig. 2. Substrate biasing Virtual GND
technique uses body terminal as a control mechanism to
Sleep
tune the threshold voltage. Substrate biasing in PMOS HVT
biases the body of the transistor to a voltage higher than
VDD and in NMOS, to a voltage lower than Vss [3]. For Fig. 3 Sleep transistor circuit
non-zero substrate bias, threshold voltage of a MOS tran-
sistor is given by the following Eq. (2):
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi
VT ¼ VTO þ c j2uF þ VSB j  j2uF j ð2Þ Concept of substrate biasing is shown in Fig. 2 as applied
to the proposed circuits in this works.
The threshold voltage of a transistor can be calculated In multi-threshold CMOS (MTCMOS), a high threshold
from Eq. (2), where VTO is the threshold voltage when voltage (HVT) device, called sleep transistor as shown in
VSB ¼ 0, uF is the Fermi potential and c is the body-effect Fig. 3, is inserted in series to the low threshold voltage
coefficient. Substrate biasing increases the threshold volt- (LVT) circuit. During active mode, HVT device remains
age of the device, hence reduces the power consumption. turned on and can be modeled as a resistor. It acts as a

Fig. 1 3-stage differential ring

oscillator

+ - + - + -

- + - + - +

D1 D2 D3

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 89

current gate to the circuit and hence the technique is known
as power gating. During the stand-by mode, the HVT
device are turned off creating a virtual power and virtual
ground connection providing good leakage control [2].
Sleep transistor sizing is critical to leakage power and
delay performance and dual threshold voltage may cause
delay overhead in switching. With the addition of sleep
transistor in a CMOS based delay stage the overall delay of
stage increases and subsequently the output frequency of
ring oscillator decreases. Delay of a CMOS circuit is
dependent on the width to length (W/L) ratio and is
inversely proportional. Since the CMOS gate with small
channel width limits the leakage current and affects the
overall power consumption. In the super cutoff CMOS
(SCCMOS), sleep transistor has the same threshold voltage
as the designed circuit. This avoids the additional delay due
to HVT [4].
Power gating is implemented by inserting a header
(PMOS) or footer (NMOS) device between the active
circuit and power supply and ground rails, where the
header and footer are controlled by a sleep signal. How-
ever, this technique leaves output floating after the stand-by
mode, so results in destruction of a state. The rest of the
paper is organized as follows: Sect. 2 presents the con-
ventional and proposed circuits with sleepy transistor
CMOS technique. Section 3 shows the results for proposed
circuits. Section 4 summarizes this work.
2 System description
2.1 Conventional CMOS inverter stage
differential RO
The conventional design of CMOS inverter based differ-
ential delay cell [6] is shown in Fig. 4(a), which is used as
the starting point of modified ring oscillator design. It
comprises of two PMOS transistors P1, P2 and two NMOS

VDD

P1 P2

+Vout-
Vin Vin-

N1 N2

(a)

VDD VDD VDD

P1 P2 P3 P4 P5 P6

N1 N2 N3 N4 N5 N6

(b)
Fig. 4 Conventional inverter stage differential a delay cell, b ring oscillator

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90 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

VDD

P1 P2 P3 P4

Vin+ Vin -
N1 N2
Vout

(a)

VDD VDD VDD

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12

N1 N2
N3 N4 N5 N6

(b)
Fig. 5 Conventional cross coupled differential a delay cell, b ring oscillator

transistors N1, N2, where P1, N1 form first inverter and P2,
N2 form second inverter. The two inverters are connected
in a way to form a differential delay cell. The conventional
differential delay cell has been used to form a three-stage
differential ring oscillator as shown in Fig. 4(b). The power
supply voltage is 1.8 V, NMOS N1 and N2 consist the
differential pair, PMOS P1 and P2 are used as active loads.
The gate of P1 and P2 are connected to the gate of N1 and
N2, so that the output signal can be pulled to maximum
voltage VDD.
The conventional design CMOS cross-coupled differ-
ential delay cell [7] is shown in Fig. 5(a). It is a modifi-
cation of conventional design-1 where two additional
PMOS transistors P2, P3 have been connected to supply
voltage directly. The cross-coupled differential delay cell is
used to form a three-stage cross-coupled differential ring
oscillator shown in Fig. 5(b). Each delay cell has dual input
and dual output. The active loads are P1–P4, where P2 and
P3 are used additionally, to maximize the output voltage
swing. Transistors P1, P4 are connected directly to a supply

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 91

VDD

P7

P1 P2

Vin+ +Vout- Vin-

N1 N2

N7

Vcontrol

(a)

VDD VDD VDD

P7 P8 P9

P1 P2 P3 P4 P5 P6

N1 N2 N3 N4 N5 N6

N7 N8 N9

Vcontrol Vcontrol Vcontrol

(b)
Fig. 6 Sleepy NMOS differential a delay cell, b ring oscillator

voltage as the current-source load to maximize tuning
range. The channel length of 0.18 lm and width of PMOS
transistor is taken as Wp = 2.5 lm whereas for NMOS
width of Wn = 1 lm is used.
2.2 Sleepy CMOS inverter stage differential RO
design
The proposed sleepy CMOS inverter stage differential
delay cell is shown in Fig. 6(a). This is the modified ver-

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92 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

VDD

Vcontrol P7

P1 P2

Vin+ +Vout- Vin-

N1 N2

(a)

VDD VDD VDD

Vcontrol P7 Vcontrol P8 Vcontrol P9

P1 P2 P3 P4 P5 P6

N1 N2 N3 N4 N5 N6

(b)
Fig. 7 Sleepy PMOS differential a delay cell, b ring oscillator

sion of conventional inverter design as shown in Fig. 4(a).
In the Fig. 6(a) N1 and N2 are acting as differential pair
and P1–P2 are acting as an active load. The sleep transis-
tors, transistor N7 is connected between the sources of N1
and N2 and ground as shown in Fig. 6(a). In Fig. 6(a),
transistor N7 is used as tail-current source is called gated-
GND. In Fig. 7(a), transistors N1 and N2 form the differ-
ential pair and transistors P1–P2is acting as active loads.
Sleep transistor P7 is used for frequency tuning is called
gated-VDD as shown in Fig. 7(a). Width (Wp) for transis-
tors P1–P9 is taken as 2.5 lm and for transistors N1–N9
width (Wn) of 1 lm is used. As the sleep transistor is added
to the circuit, the current drawn by sleep transistor is
increased in active mode, resulting in increasing output
frequency. Power consumption is reduced in the sleep
mode, when the sleep transistors cut-off the pull down
network from ground in NMOS and cuts off pull-up net-
work from VDD in PMOS network. Hence, leakage power
is saved with reduction in power consumption.
The control voltage Vcontrol is applied at the gate of N7
and P7 sleep transistors, which is used to tune the fre-
quency of the oscillator by regulating the value of tail-
current source. A 3-stage sleepy NMOS differential ring
oscillator is shown in Fig. 6(b). The PMOS sleep differ-
ential delay cell forms a three-stage sleepy PMOS differ-
ential ring oscillator as shown in Fig. 7(b). The circuit
operates at 1.8 V. Sleepy transistor technique is state-de-
structive and cuts off pull-up network from supply voltage

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 93

VDD

P1 P2 P3 P4

Input Output

N1 +Vout- N2

N7
Vcontrol

(a)

VDD VDD VDD

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12

N1 N2
N3 N4 N5 N6

N7 N8 N9
Vcontrol Vcontrol Vcontrol

(b)
Fig. 8 Sleepy NMOS cross coupled differential a delay cell, b ring oscillator

and pull-down network from ground, by isolating the logic
networks during sleep mode, thereby reducing dynamic
and leakage power.
2.3 Sleepy CMOS cross coupled differential RO
design
Figure 8(a) shows the proposed sleepy NMOS cross-cou-
pled delay cell, which is a modified version of conventional
cross-coupled design as shown in Fig. 5(a). The transistor
N7 is a sleep transistor that has a control voltage Vcontrol at
its gate, which is used to tune the output frequency. In sleep
mode, N7 cuts off ground to the pull-down network.
Figure 8(b) shows a three-stage sleepy NMOS cross-cou-
pled differential ring oscillator.
Figure 9(a) represents proposed sleepy PMOS cross-
coupled differential delay cell with sleep transistor P13.
Transistor P13 cuts off supply voltage to the pull-up net-
work in sleep mode, hence, reduces the leakage power
consumption. Transistor P13 is connected to the control
voltage Vcontrol at its gate terminal, which controls the
output frequency. Vcontrol takes negative values, less than
0 V. Figure 9(b) shows a three-stage sleepy PMOS cross-
coupled differential ring oscillator. Transistors P2 and P3
act as positive feedback pair, whereas NI and N2 form a
differential pair. Transistors P1 and P4 are the active loads

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94 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

VDD
P13
Vcontrol

P1 P2 P3 P4

Vin Vin -
N1 N2
Vou

(a)

VDD VDD VDD

Vcontrol Vcontrol Vcontrol

P13 P14 P15

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12

N1 N2
N3 N4 N5 N6

(b)
Fig. 9 Sleepy PMOS cross coupled differential a delay cell, b ring oscillator

Table 1 Result of 3-stage sleepy NMOS differential RO 3 Results and discussion

VCONTROL (V) Frequency (GHz) Power (lW)
3.1 Sleep CMOS inverter differential RO design
1.0 3.09 696.63
1.2 3.82 817.75 The results of proposed differential ring oscillator have
1.4 4.17 875.80 been obtained through the simulation with SPICE in
1.6 4.35 908.68 CMOS 180 nm technology. The conventional design of
1.8 4.45 928.64 CMOS inverter based differential delay cell has output
2.0 4.48 941.08 frequency range from 2.09 to 6.96 GHz and power con-
2.2 4.54 948.74 sumption range from 8.92 lW to 3.83 Mw where VDD
2.4 4.56 953.20 varies from 1.0 to 2.4 V. For the sleepy NMOS ring
oscillator of Fig. 6(b) and sleepy PMOS ring oscillator of
Fig. 7(b) Vcontrol has been varied to obtain the different
output frequency range having the VDD is fixed at 1.8 V.
in Figs. 8 and 9. For transistors P1–P15 width Wp- Further, result of sleepy NMOS differential ring oscillator
= 2.5 lm and for transistors N1–N9 width Wn = 1 lm as is obtained by varying VBIAS at the body terminal of
taken for the circuit shown in Figs. 8(b) and 9(b). transistor N7 sleep transistor. Here, VDD and Vcontrol is
fixed at 1.8 V.

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 95

Fig. 10 Waveformof 3-stage sleepy NMOS differential RO

Table 2 Result of 3-stage sleepy PMOS differential RO

VCONTROL (V) Frequency (GHz) Power (mW)

- 0.1 4.41 1.95

- 0.2 4.45 1.97
- 0.4 4.51 1.99
- 0.6 4.54 2.00
- 0.8 4.57 2.01
- 1.0 4.59 2.02
- 1.2 4.60 2.03
- 1.4 4.61 2.035
- 1.6 4.63 2.04

Table 1 shows the result of proposed three-stage sleepy

Fig. 11 3-stage sleepy NMOS differential RO a output frequency,
b power consumption variation with control voltage
NMOS inverter stage differential ring oscillator. In the
Fig. 6(b), the control voltage Vcontrol is varied form 1.0 to
2.4 V keeping supply voltage VDD fixed at 1.8 V. As the
control voltage is increased, the current drawn by sleep
transistor is increased, resulting in increasing output fre-
quency and power consumption. Comparing Figs. 4(b) and
6(b), the delay of the circuit is increased, but, power con-
sumption is reduced in the sleep mode, when the sleep
transistors N7, N8 and N9 cut-off the pull down network
from ground., leakage power is saved. Figure 10 shows the
waveform of three-stage sleepy NMOS differential ring
oscillator at Vcontrol = 1.8 V. Figure 11(a), (b) represent
the graph of the output frequency (GHz) and power con-
sumption (lW) plotted against control voltage respectively.
With increase in Vcontrol, the output frequency and power
consumption increases. The output frequency varies from

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96 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

Fig. 12 Waveform of 3-stage sleepy PMOS differential RO

3.09 to 4.56 GHz and power consumption varies from

0.696 to 0.953 mW.
Table 2 represents the result of three-stage sleepy
PMOS inverter stage differential ring oscillator as shown in
Fig. 7(b). The value of control voltage Vcontrol is taken
below 0 V (from - 0.1 to - 1.6 V) to conduct. The
waveform of three-stage sleepy PMOS differential ring
oscillator at Vcontrol = - 0.8 V is shown in Fig. 12. The
output frequency (GHz) and power consumption (lW) are
plotted against the control voltage as shown in Fig. 13(a),
(b) respectively. As the control voltage is reduced, the
current through the PMOS sleep transistors, P7, P8 and P9
is increased, resulting in higher output frequencies and
higher power consumption. The output frequency varies
from 4.41 to 4.61 GHz and power consumption varies from
1.95 to 2.04 mW (Figs. 12, 13).
Table 3 shows the results of sleepy NMOS inverter
stage differential ring oscillator as shown in Fig. 6(b). In
this circuit design the body terminal of sleep transistor, N7,
N8 and N9 is connected with a bias voltage VBIAS keeping
the Vcontrol and VDD fixed at 1.8 V. The Table 3 shows as
the bias voltage is decreased below 0 V, the power con-
sumption along with output frequency is further reduced as
compared to circuits of Figs. 4(b) and 6(b). This substrate
biasing method is useful for low power applications [3].
The corresponding waveform with substrate biasing in
three-stage sleepy NMOS differential ring oscillator is
shown in Fig. 14. The graph of output frequency (GHz) vs
bias voltage is shown in Fig. 15(a) and graph of power
consumption (mW) versus bias voltage is shown in
Fig. 15(b). The output frequency varies from 4.16 to
Fig. 13 3-stage sleepy PMOS differential RO a output frequency,
b power consumption variation with control voltage

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 97

Table 3 Result of bias voltage of 3-stage sleepy NMOS RO

VBIAS (V) Frequency (GHz) Power (lW)

- 0.1 4.45 924.78

- 0.2 4.43 920.89
- 0.4 4.39 913.05
- 0.6 4.35 905.07
- 0.8 4.32 896.92
- 1.0 4.29 888.57
- 1.2 4.24 879.99
- 1.4 4.20 871.14
- 1.6 4.16 862.02

4.45 GHz and power consumption varies from 0.924 to

0.862 mW.

3.2 Sleep CMOS cross coupled differential RO

design

The results of proposed sleepy CMOS cross-coupled dif-

ferential ring oscillator are provided in this section. The
conventional cross-coupled ring oscillator shows the output
frequency from 1.16 to 3.26 GHz and the power con-
sumption from 12.68 lW to 5.10 mW with varying VDD is
from 1.0 to 2.4 V. Results of sleepy NMOS cross-coupled
ring oscillator of Fig. 8(b) and sleepy PMOS cross-coupled
ring oscillator of Fig. 9(b) have obtained by varying
Vcontrol to obtain variable output frequency. In third case,
results of sleepy NMOS cross coupled differential ring Fig. 15 3-stage sleepy NMOS differential RO a output frequency,
b power consumption variation with bias voltage

Fig. 14 Waveform of bias voltage for 3-stage sleepy NMOS differential RO

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98 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

oscillator is obtained by varying VBIAS at the body terminal increased, but, power consumption is reduced in the sleep
of transistor N7 sleep transistor. Here, VDD and Vcontrol is mode, when the sleep transistors N7, N8 and N9 cut-off the
fixed at 1.8 V. pull down network from ground, leakage power is saved.
Cross-coupled transistors have been used to maximize Figure 16 shows the waveform of three-stage sleepy
the output voltage swing and lower the noise power. NMOS differential ring oscillator at Vcontrol = 1.8 V. Fig-
Table 4 shows the result of proposed three-stage sleepy ure 17(a), (b) represent the graph of the output frequency
NMOS cross-coupled differential ring oscillator. In the (GHz) and power consumption (mW) plotted against con-
Fig. 8(b), the control voltage Vcontrol is varied from 1.0 to trol voltage respectively. With increase in Vcontrol, the
2.4 V keeping supply voltage VDD fixed at 1.8 V. As the output frequency and power consumption increases. The
control voltage is increased, the current drawn by sleep output frequency varies from 2.23 to 4.25 GHz and power
transistor is increases resulting in increase in the output consumption varies from 0.780 to 1.21 mW.
frequency. Comparing Figs. 5(b) and 8(b), the delay is Table 5 represents the result of three-stage sleepy
PMOS cross coupled differential ring oscillator as shown in
Fig. 9(b). The control voltage Vcontrol needs values below
Table 4 Result of 3-stage sleepy NMOS cross coupled RO
0 V for PMOS to conduct from - 0.1 V to - 0.9 V. The
VCONTROL (V) Frequency (GHz) Power (mW) waveform of three-stage sleepy PMOS cross coupled dif-
1.0 2.23 0.780 ferential ring oscillator at Vcontrol = - 0.4 V is shown in
1.2 2.73 0.984 Fig. 18. The output frequency (GHz) and power con-
1.4 3.40 1.08 sumption (mW) are plotted against the control voltage as
1.6 3.95 1.14
shown in Fig. 19(a), (b) respectively. As the control volt-
1.8 4.13 1.17
age is reduced below 0 V, the current through the PMOS
sleep transistors, P13, P14 and P15 is increased, resulting
2.0 4.19 1.19
in higher output frequencies and igher power consumption.
2.2 4.23 1.21
The output frequency varies from 2.26 to 2.41 GHz and
2.4 4.25 1.21
power consumption varies from 0.97 to 1.06 mW
(Figs. 18, 19).

Fig. 16 Waveform of 3-stage sleepy NMOS cross coupled RO

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 99

Table 5 Result of 3-stage sleepy PMOS cross coupled RO

VCONTROL (V) Frequency (GHz) Power (mW)

- 0.1 2.26 0.97

- 0.2 2.28 0.99
- 0.3 2.30 1.00
- 0.4 2.31 1.01
- 0.5 2.35 1.02
- 0.6 2.38 1.03
- 0.7 2.39 1.04
- 0.8 2.40 1.05
- 0.9 2.41 1.06

to circuits of Figs. 5(b) and 8(b). The corresponding

Fig. 17 3-stage sleepy NMOS cross coupled RO a output frequency,
b power consumption variation with control voltage
Table 6 shows the results of sleepy NMOS cross-cou-
pled differential ring oscillator as shown in Fig. 8(b) when
the body terminal of sleep transistor, N7, N8 and N9 is
connected with a bias voltage VBIAS, keeping the Vcontrol
and VDD fixed at 1.8 V. The Table 6 shows as the bias
voltage is decreased below 0 V, the power consumption
along with output frequency is further reduced as compared
waveform with substrate biasing in three-stage sleepy
NMOS differential ring oscillator is shown in Fig. 20. The
graph of output frequency (GHz) vs bias voltage (V) is
shown in Fig. 21(a). Graph showing the variation of power
consumption (lW) with bias voltage (V) is shown in
Fig. 21(b).
Effect of load capacitance on output frequency has been
studied for the proposed circuit by including the different
two different capacitance values at the output node with
VDD = 1.8 V. Results are shown in the Table 7 and it has
been observed that the output frequency decreases with
addition of capacitance at output node. With increases in
the output node capacitance, overall delay of the individual
inverter delay stage increases and results in the reduction of
output frequency of ring oscillator.
Table 8 compares the results of two different designs of
differential RO with conventional designs in terms of
output frequency and power consumption. Phase noise can
be considered as undesirable fluctuation due to device
noise. Phase noise and figure of merit (FoM) results have
also been obtained for the proposed VCO with different
value of control voltage (V). Mathematical relation of
figure of merit (FoM) [23] as shown in Eq. (3) has been
used for calculations.
fo P
FoM ¼ 20 log  10 log  PN ð3Þ
Df 1mW
where PN is the measured phase noise at the offset fre-
quency from the central frequency fo , P is the DC power

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100 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

Fig. 18 Waveform of 3-stage sleepy PMOS cross coupled RO

Table 6 Result of bias voltage of 3-stage sleepy NMOS cross coupled

RO
VBIAS (V) Frequency (GHz) Power (mW)

- 0.1 2.05 1.16

- 0.2 2.04 1.16
- 0.4 2.01 1.15
- 0.6 1.99 1.13
- 0.8 1.96 1.12
- 1.0 1.94 1.11
- 1.2 1.91 1.09
- 1.4 1.88 1.08
- 1.6 1.86 1.06

consumption in mW. Table 9 compares the phase noise for

proposed designs at different control voltages. For NMOS
inverter stage design, as supply voltage is increased, phase
noise reduces. For PMOS cross-coupled design, as control
voltage is made more negative, phase noise reduces. Fig-
ure 22 presents the phase noise of NMOS inverter stage
differential RO at VDD = 1.8 V and Vcontrol = 1.8 V
@1 MHz. The phase noise is - 93.62(dBc/Hz). For
Table 10 compares the results obtained in this paper with
earlier work.

Fig. 19 3-stage sleepy PMOS cross coupled RO a output frequency,

b power consumption variation with control voltage

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 101

Fig. 20 Waveform of 3-stage sleepy PMOS cross-coupled RO

4 Conclusion

Two differential ring oscillator designs in 180 nm CMOS

technology have been proposed in this paper. The concept
of sleepy transistor has been applied to reduce the leakage
power consumption. As the technology feature size shrinks,
leakage power consumption may dominate total chip
power consumption. The simulations have been performed
using SPICE in 0.18 lm CMOS technology. First design is
obtained from conventional CMOS inverter based differ-
ential ring oscillator (RO) by adding sleepy NMOS and
sleepy PMOS transistors separately. The power consump-
tion for sleepy NMOS differential RO design is 0.696 to
0.953 mW and the frequency of operation is
3.09–4.56 GHz. The power consumption for sleepy PMOS
differential RO design is 1.95–2.04 mW and the frequency
of operation is 4.41–4.63 GHz. The substrate biasing of
sleepy NMOS RO design gives power consumption of
0.862–0.924 mW and the frequency of operation is
4.16–4.45 GHz. Second design is obtained by modifying
conventional CMOS cross-coupled differential ring oscil-
lator by adding sleepy NMOS and sleepy PMOS transis-
tors. The power consumption for sleepy NMOS cross-
coupled differential RO design is 0.78–1.21 mW and the
frequency of operation is 2.23–4.25 GHz. The power
consumption for sleepy PMOS cross-coupled differential
RO design is 0.97–1.06 mW and the frequency of operation
is 2.26–2.41 GHz. The substrate biasing of sleepy NMOS
cross-coupled RO design gives power consumption of
1.06–1.16 mW and the frequency of operation is
1.86–2.05 GHz. Output frequency and power consumption
results have been compared with earlier reported circuits Fig. 21 3-stage sleepy NMOS cross coupled RO a output frequency,
b power consumption variation with bias voltage

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102 Analog Integrated Circuits and Signal Processing (2018) 96:87–104

Table 7 Effect of load

C = 1 fF C = 10 pF
capacitance on the outpur
Freq (GHz) Freq (GHz)
frequency of VCO
Proposed sleepy NMOS inverter stage RO 3.54 1.73
Proposed sleepy PMOS inverter stage RO 3.43 2.48
Proposed sleepy NMOS cross coupled RO 2.03 1.49
Proposed sleepy PMOS cross coupled RO 1.94 1.42

Table 8 Comparison of proposed VCO

Inverter stage RO Cross coupled RO
Conventional Sleepy Sleepy PMOS Substrate bias Conventional Sleepy Sleepy PMOS Substrate bias
NMOS sleepy NMOS NMOS sleepy NMOS

Control – 1.0 to 2.4 - 0.1 to - 1.6 - 0.1 to - 1.6 – 1.0 to 2.4 - 0.1to - 0.9 - 0.1 to - 1.6
Voltage (V)
Output 2.09–6.96 3.09–4.56 4.41–4.63 4.16–4.45 1.16–3.26 2.23–4.25 2.26–2.41 1.86–2.05
frequency
(GHz)
Power 0.008–3.83 0.696–0.953 1.95–2.04 0.862–0.924 0.012–5.10 0.78–1.21 0.97–1.06 1.06–1.16
consumption
(mW)

Table 9 Comparison of proposed VCO for phase noise

Proposed design Supply voltage (VDD) Control voltage (Vcontrol) Phase noise (dBc/Hz) @1 MHz FoM (dBc/Hz)

NMOS inverter stage 1.8 1.0 - 93.62 166.26

NMOS inverter stage 1.8 1.8 - 92.89 165.53
NMOS inverter stage 1.8 2.0 - 92.82 165.46
PMOS cross coupled cell 1.8 - 0.2 - 97.33 163.48
PMOS cross coupled cell 1.8 - 0.8 - 97.09 163.24

Fig. 22 Phase noise for NMOS inverter stage @1 MHz

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Analog Integrated Circuits and Signal Processing (2018) 96:87–104 103

Table 10 Comparison of VCO performances

RO designs Technology Supply Control voltage Output Power Tuning
(nm) voltage (VDD) (Vcontrol) frequency consumption range (%)
(GHz) (mW)

[7] 350 3.3 0.0 to 2.5 1.43–1.55 79.0 8.05

[8] 180 0.8 0.0 to 2.0 5.07–6.20 2.81 20.3
[10] 130 1.5 – 7.30–7.86 60.0 7.38
[13] 500 2.5 – 0.66–1.20 15.5 58.0
[14] 180 3.5 0.5 to 2.5 5.29–6.56 6.80 21.4
[15] 90 1.0 – 3.60–7.50 1.70 70.2
[17] 180 1.8 – 1.62–3.22 1.00 66.1
[18] 180 1.8 1.1 to 3.0 7.42–8.52 8.28 13.8
[19] 90 1.0 0.1 to 0.8 1.70–9.30 18.0 70.0
[20] 180 1.8 0.4 to 1.6 1.77–1.92 13.0 8.13
[21] 180 1.6 – 9.40–10.1 11.5 6.10
[22] 180 1.5 0.0 to 1.5 4.46–5.36 8.70 18.3
Proposed sleepy NMOS inverter stage 180 1.8 1.0 to 2.4 3.09–4.56 0.69–0.95 38.4
Proposed sleepy PMOS inverter stage 180 1.8 - 0.1 to - 1.6 4.41–4.63 1.95–2.04 4.86
Proposed substrate biased sleepy 180 1.8 - 0.1 to - 1.6 4.16–4.45 0.86–0.92 6.73
NMOS inverter stage
Proposed Sleepy NMOS cross coupled 180 1.8 1.0 to 2.4 2.23–4.25 0.78–1.21 63.4
cell
Proposed sleepy PMOS cross coupled 180 1.8 - 0.1 to - 0.9 2.26–2.41 0.97–1.06 2.72
cell
Proposed substrate biased sleepy 180 1.8 - 0.1 to - 1.6 1.86–2.05 1.06–1.16 9.71
NMOS cross coupled cell

and proposed circuits show significant improvement over
previous circuits.
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17. Liu, H., Zhang, X., Dai, Y., Lu, Y., & Wei, B. (2009). A wide Manoj Kumar is working as an
range low power CMOS radio frequency ring oscillator. In Associate Professor in USICT
ICIEA, pp. 1340–1344. (ECE), GGSIPU, Dwarka, New
18. Hsu, M. T., Li, W. J., & Hsu, Y. T. (2014). Design of self-bias tail Delhi. He has more than
transistor technique for low phase noise CMOS VCO with har- 14 years of experience in
monic suppression using capacitance ground. Microelectronics teaching and research. He has
Journal, 45(1), 35–42. (ISSN 0026-2692). published 30 research papers in
19. Maaita, T. A. A., Tahboub, A. H., & Gharbeh, K. A. (2013). A International/National journals.
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20. Chen, Z. Z., & Lee, T. C. (2011). The design and analysis of dual- tional/National conference. His
delay-path ring oscillators. IEEE Transactions on Circuits and research interests include inte-
Systems, 58(3), 470–478. grated circuit design, low power
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noise and low power modified current-reused VCOs for 10 GHz tronics for communication sys-
applications. Microelectronics Journal, 44(2), 145–151. (ISSN tems. He is a Life Member of IETE (India), ISTE (India), CSI (India)
0026-2692). and Semiconductor Society of India.
22. Xie, J., Vamshi, M. K., Do, M. A., Boon, C. C., & Yeo, K. S.
(2012). A low power low phase noise dual-band multiphase
VCO. Microelectronics Journal, 43(12), 1016–1022. (ISSN
0026-2692).
23. Andreani, P., Bonfanti, A., Romano, L., & Samori, C. (2002).
Analysis and design of a 1.8-GHz CMOS LC quadrature VCO.
IEEE Journal of Solid-State Circuits, 37(12), 1737–1747.

Prachi Gupta is a student of

M.Tech. (Electronics and com-
munication Engineering) in
USICT, GGSIP University,
New Delhi, India. She is doing
her research work in the field of
low power CMOS circuit
design. She has published one
paper in IEEE ICCCA 2017 in
Noida, U.P, India.

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