A Novel High Performance Low Power CMOS NOR
Gate Using Voltage Scaling and MTCMOS Technique
Ankish Handa, Jitesh Chawla
Maharaja Surajmal Institute of Technology
New Delhi, India
Abstract—CMOS logic is extensively used in VLSI circuits but
due to scaling of technology, the threshold voltage of the transistors
used in CMOS circuits decrease which cause an increase in leakage
power. Dynamic power consumption, which is proportional to
square of supply voltage VDD further adds to the overall power
dissipation. This results in low battery life of mobile devices. In this
brief, a novel method to curtail both dynamic power dissipation
and leakage power is proposed. The proposed method combines
Voltage Scaling and Multi-Threshold CMOS (MTCMOS)
technique which helps in reducing dynamic and static power
dissipation respectively without degrading the circuit’s
performance. The proposed technique saves power dissipation by
30% to 90% as compared to conventional CMOS and other
existing techniques. A 2-input NOR gate is implemented using the
proposed VS-MTCMOS technique in sub-threshold region over
different temperatures. Tanner EDA Tool is used to simulate the
designed circuit.
Keywords- CMOS; Sub-threshold; Voltage Scaling; MTCMOS;
Power Consumption; Power Delay Product.
I. INTRODUCTION
In the past, area, cost, reliability and performance were
regarded as the primary concerns for VLSI designers while
power consumption was treated as a secondary concern. But,
with the introduction and ever increasing demand of mobile
electronic devices and other wireless communication systems
such as PDAs and personal communicators, power consumption
is now given equal importance in comparison to area and
performance [1]. This requires power efficient VLSI circuits.
Sub-threshold logic circuits have been introduced recently for
applications that require ultra-low power consumption [2] [3].
These circuits require that the operating voltage VDD should be
less than the threshold voltages of the transistors that are present
in the VLSI circuit. The overall power consumption is reduced in
such circuits.
There are two primary sources of power dissipation in any
CMOS circuit. The first source is the dynamic power dissipation
which is due to switching activity of the circuit. In this, the
parasitic capacitances are charged and discharged as the nodes of
978-1-4799-3080-7/14/$31.00 2014
c IEEE
Geetanjali Sharma
Maharaja Surajmal Institute of Technology
New Delhi, India
the circuit transits between the two logic levels. As the current
flows through the transistors, some resistance is offered by their
channel and hence electrical energy is converted into heat and
dissipates away [4]. This dynamic power dissipation is
proportional to the square of the supply voltage VDD, load
capacitance and frequency and is given by PDYN=CV2DDf.
The second source of power dissipation takes place when
input(s) applied to a logic gate and the output of that logic gate is
not changing. This is termed as static power dissipation and is
due to junction leakage, sub-threshold leakage and gate oxide
leakage. The sub-threshold leakage refers to the leakage current
which flows from drain to source when the transistor is in OFF
state. This leakage increases exponentially as we scale down the
threshold voltage and device geometry. The sub-threshold
leakage depends on the parameters given in [5].
In present work, a novel technique is proposed that reduces
both dynamic power dissipation and leakage power by
incorporating Voltage Scaling and MTCMOS technique. The
Voltage Scaling and Charge Sharing technique curtails dynamic
power dissipation by degrading the supply voltage level and
static power is suppressed greatly by MTCMOS technique which
comprises of high VT sleep transistors between PUN and power
supply and/or between PDN and ground. The proposed
methodology aims at gaining an edge over other existing
techniques. The rest of the paper is organized as follows: Section
II presents a review of the existing techniques for low power
design. Section III and IV explains Voltage Scaling technique
and MTCMOS technique. In Section V, the proposed technique
(VS-MTCMOS) is presented in detail for low power CMOS
circuit design. Section VI presents the simulation result. This is
followed by conclusions in Section VII.
II. EXISTING METHODS FOR POWER REDUCTON
Dynamic power consumption absorbs most of the power in a
VLSI circuit. Hence dynamic power dissipation must be
suppressed to reduce the overall power consumption. A Low
Power VDD management technique is proposed in [6] to reduce
power consumption for domino circuits. It exploits a rising and
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charge sharing voltage which allows circuits to consume less
power and have high performance. In [7] a hybrid approach is
described. The proposed technique merges Voltage Scaling
technique and Dual Threshold Voltage (DTV) technique. Voltage
Scaling reduces dynamic power dissipation and DTV curtails
leakage power. Local Voltage Dithering approach when
combined with sub-threshold operation permits ultra-dynamic
voltage scaling [8]. This technique reduces power consumption
by 9 times than ideal shutdown.
Current trends show that leakage power reduction has become
significant than dynamic power dissipation. The reason behind
this is the exponential increase in leakage power due to scaling of
power supply and device geometry. Several methods have been
proposed to control leakage power. Power Gating [9] technique
reduces leakage power by cutting off the power supply to the
circuit during standby mode. This is accomplished by introducing
sleep transistors in between pull-up network and power supply
and/or pull-down network and ground. These transistors are
turned on when the circuit is in active state and are switched off
throughout standby mode. A variation to Power Gating technique
is Multi-Threshold CMOS (MTCMOS) technique [10] which
employs high VT sleep transistors because of the fact that leakage
power varies exponentially with threshold voltage. While low VT
transistors are used for logic gates present in the circuit to
maintain circuit performance. In [11] Forced Stacking technique
is proposed where an existing transistor is partitioned into two
transistors whose size is half to that of actual transistor. This
forms a stack of transistors. When these transistors will be in cut-
off state, a reverse bias is induced between them which abate the
leakage power.
III. VOLTAGE SCALING TECHNIQUE
In this section, Voltage Scaling and Charge Sharing technique
[12] to curb dynamic power dissipation is explained. This
section describes the Voltage Scaling circuit and its operation.
Fig. 1 shows the circuit for Voltage Scaling technique.
Fig. 1 Voltage Scaling and Charge Sharing Circuit
2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)
The above circuit is helpful in abating dynamic power
dissipation through scaling of voltage supply VDD. The required
power supply to the circuit is imparted through node a, instead
of providing power supply directly through VDD. Signal S
controls the supply of VDD to the circuit through node a. In
above technique, transistors M1 and M2 are connected to signal
S. When S goes high, transistor M1 becomes OFF and M2 turns
ON. This causes M3 to turn ON and allows full supply of VDD to
the circuit. Supply voltage is fully provided till the signal S is
high. As soon as the signal S goes low, transistors M2 and M3
are turned OFF while transistor M1 turns ON. The circuit now is
charged and discharged alternatively. The value of VS drops
below supply voltage VDD and in this way Voltage Scaling
technique reduces power dissipation. Capacitors Ca and Cb share
charge through Self-Stabilization (SS) path which further helps
in maintaining a low level of variation in VS.
IV. MTCMOS TECHNIQUE
Sub-threshold leakage increases exponentially as the device
geometry scales down. Scaling of power supply and threshold
voltage of transistors further increases the leakage current.
Hence, the standby leakage power will become equal to dynamic
power dissipation under such circumstances.
The standby period of battery operated devices like cell
phones and PDAs is high which requires standby leakage current
to be reduced in order to increase battery life. Thus reduction in
leakage power becomes a primary concern for VLSI designers.
Fig. 2 MTCMOS Technique
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 The MTCMOS technique is one of the powerful techniques to During standby mode, where input(s) applied to a logic gate
curtail leakage power. The MTCMOS technique has two modes and its corresponding output does not change, the high VT sleep
of operation, active mode and standby mode. In general, a transistor H1 and H2 present in the circuit are switched off by
standard CMOS circuit incorporates only single threshold (VT) setting T=’1’ and TBAR=’0’. This sets a high resistance path
transistors whereas MTCMOS technique consists of two between the two networks. Thus, there is a reduction in leakage
threshold voltage transistors. The high VT transistors are called power during the standby mode which is setup by introduction
sleep transistors which helps in preventing leakage power of MTCMOS technique that incorporates high VT sleep
dissipation and low VT transistors are used in the logical circuit to transistors H1 and H2. Voltage Scaling circuit, on the other side
boost up circuit’s performance. prevents dynamic power dissipation during active mode and
standby mode. Thus, overall power is reduced by combining
The MTCMOS technique is shown in Fig. 2. It consists of these two techniques.
two high VT sleep transistors. One sleep transistor is placed
between power supply and Pull-Up Network while other is
placed between ground and Pull-Down Network. These
transistors are driven by complementary signals T and TBAR.
The Pull-Up and Pull-Down Network which is also regarded as
the logical circuit, consists of low VT transistors.
The given circuit operates in active and standby mode. In
active mode both sleep transistors are turned on by making T=0
and TBAR=1. The circuit works as a normal CMOS circuit but at
a higher speed because of presence of low VT transistors in
logical circuit. During standby mode of operation, T=1 and
TBAR=0 which turns off the sleep transistors. This provides a
higher resistance path from VDD to Gnd which reduces leakage
power.

V. PROPOSED VOLTAGE SCALING AND MTCMOS

TECHNIQUE
In section III and IV, Voltage Scaling and MTCMOS
technique are discussed. In this section, we propose a new power
reduction technique which combines Voltage Scaling and
MTCMOS technique (VS-MTCMOS). This hybrid technique
ensures reduction in both dynamic and static power dissipation.
The structure of proposed method is experimented on a 2 input
NOR gate shown in Fig. 3.
The given circuit works in two modes of operation which are
active mode and idle mode. During active mode of operation,
the power supply voltage is scaled down through Voltage
Scaling and Charge Sharing technique to combat dynamic power
dissipation. The high VT sleep transistors H1 and H2 are turned
on by applying logic 0 to T and logic 1 to TBAR which allow
them to behave as normal transistors. The circuit has become a Fig. 3 Proposed VS-MTCMOS Technique
standard CMOS circuit. When S is high, transistor M2 turns on
and voltage level of VP gets low. This turns on the transistor M3
and full power supply is fed to the circuit. The correct output is VI. SIMULATION RESULTS
collected. When S gets low, transistor M1 and M3 are turned off The proposed technique is implemented on a 2 input NOR
which drops the voltage level of VS. At the same time capacitor gate using Tanner EDA tool at 45nm process technology.
Cb and Ca shares charge through self stabilization path which Simulation results of the proposed methodology are compared
further decreases the voltage level of VP. In such situation with the conventional CMOS and other existing techniques. All
transistor M3 will turn on, raising the voltage level of VS and circuits are tested at 10°C, 30°C and 50°C and supply voltage
will also help to reduce large variations in VS. Thus, dynamic
VDD varies from 0.3v to 0.6v. The threshold voltage of
power dissipation is reduced through Voltage Scaling technique.
transistors used in logic circuit is higher than supply voltage VDD
which provides ultra-low power consumption over the entire

626 2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)

VDD range. Power Consumption at different temperatures is 30°C. Same results are obtained at 50°C. Hence, proposed
shown in Table I, II and III. design is superior to conventional CMOS circuit. Similar results
are obtained when only MTCMOS technique is incorporated in
The power consumption value of various techniques at 10°C CMOS circuit.
is given in Table I. The proposed technique has outshined the TABLE II
conventional CMOS technique. The power consumption is
POWER CONSUMPTION OF 2-INPUT NOR GATE AT 30°C
reduced by 68.45% at 0.6v while more than 90% power is saved
at 0.5v, 0.4v and 0.3v. Similar results are obtained when only
MTCMOS technique is applied to CMOS circuit. Power is Power Consumption(W)
reduced by 62.18% at 0.6v. At other operating voltages, power
is curtailed by more than 90%.
VDD Standard Voltage MTCMOS VS-
VS-MTCMOS technique has also outshined Voltage Scaling (V) CMOS Scaling MTCMOS
technique. The proposed technique uses 63.71% and 67.69%
less power at 0.6v and 0.5v. When experimented at 0.4v and
0.3v, VS-MTCMOS technique consumes 59.70% and 31.24%
less power than Voltage Scaling technique. Fig. 4 shows the
0.6 7.731E-8 6.934E-8 6.351E-8 2.414E-8
comparison among different techniques.

TABLE I
0.5 4.712E-8 7.996E-9 3.953E-8 4.011E-9
POWER CONSUMPTION OF 2-INPUT NOR GATE AT 10°C

0.4 2.824E-8 6.693E-9 2.329E-8 2.308E-9

Power Consumption(W)

0.3 1.463E-8 4.022E-9 1.181E-8 7.359E-10

VDD Standard Voltage MTCMOS VS-
(V) CMOS Scaling MTCMOS

TABLE III

0.6 7.067E-8 6.460E-8 5.895E-8 2.229E-8 POWER CONSUMPTION OF 2-INPUT NOR GATE AT 50°C

Power Consumption(W)
0.5 4.588E-8 3.281E-9 3.812E-8 1.060E-9

0.4 2.734E-8 1.997E-9 2.247E-8 8.047E-10 VDD Standard Voltage MTCMOS VS-
(V) CMOS Scaling MTCMOS

0.3 1.405E-8 9.382E-10 1.126E-8 6.451E-10

0.6 8.288E-8 7.992E-8 6.883E-8 3.615E-8

The power consumption value for various techniques at 30°C
and 50°C is shown in Table II and III. Even at higher
temperature, the proposed VS-MTCMOS technique outshines 0.5 5.064E-8 6.081E-9 4.227E-8 3.677E-9
the existing techniques. The power consumed is 68.77% and
56.38% less than conventional CMOS at 30°C and 50°C when
operated on 0.6v. The VS-MTCMOS technique saves 61.99% 0.4 3.010E-8 5.584E-9 2.493E-8 2.847E-9
power as compared to MTCMOS technique at 0.6v and at 30°C
while at 50°C, proposed method consumes 47.47% less power.
0.3 1.567E-8 2.858E-9 1.283E-8 1.066E-9
When operated on 0.5v, 0.4v and 0.3v, the proposed design
saves more than 90% power as compared to basic CMOS at

2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI) 627

When compared with Voltage Scaling technique, the proposed From Fig. 7, it can be seen that the PDP values of proposed
VS-MTCMOS technique saves 65.18% and 54.76% power at technique is least.
30°C and 50°C when operated on 0.6v.
More power is saved at 0.4v and 0.3v. When operated at 50°C,
power consumption is reduced by 49.01% and 30.59% while at
30°C, 65.51% and 81.70% less power is required by proposed
circuit. Fig. 5 and Fig. 6 compare the proposed technique with
other techniques.

Fig. 6 Power Consumption Vs VDD at 50°C

TABLE IV
POWER DELAY PRODUCT OF 2-INPUT NOR GATE AT 30°C

Power Delay Product(fWsec)

Fig. 4 Power Consumption Vs VDD at 10°C

VDD Standard Voltage MTCMOS VS-

(V) CMOS Scaling MTCMOS

0.6 0.240 0.226 0.195 0.109

0.5 0.998 0.553 0.391 0.305

0.4 1.628 0.777 0.923 0.502

0.3 2.118 0.914 2.077 0.676

Fig. 5 Power Consumption Vs VDD at 30°C
Table IV shows the Power Delay Product (PDP) at 30°C. The
PDP value of proposed technique is less than other techniques.
Thus, VS-MTCMOS technique does not degrade the
performance of the circuit. Fig. 7 shows the PDP values at 30°C.
The proposed technique also ensures that the circuit is less
sensitive to temperature variations. Fig. 8 gives the power
consumption of various techniques at different temperatures.
The results are taken at 0.6v. The variation in power
consumption is least for the proposed VS-MTCMOS technique.

628 2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)

Hence, VS-MTCMOS technique abates overall power
consumption without degrading the performance of the circuit.
Fig. 7 Power Delay Product Vs VDD at 30°C
Fig. 8 Power Consumption Vs Temperature at 0.6v
VII. CONCLUSION
In this paper, a novel methodology using Voltage Scaling and
MTCMOS technique has been described. The proposed
technique is able to curtail both dynamic power dissipation and
2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)
leakage power and has maintained the speed of the circuit. The
total power dissipation has been reduced by 40 to 90%. The
output logic is also preserved when circuit go into active state
from idle state and vice-versa. Moreover, the proposed
technique is less sensitive to temperature variations.
In future, the sleep transistors used in proposed method will
be optimized and the effect of process and temperature
variations on performance and power consumption of CMOS
circuits will be studied.
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