An Energy-Efficient Subthreshold Level Shifter with

A Wide Input Voltage Range

Yuan Cao1,2 , Wenbin Ye2 , Xiaojin Zhao2,∗ and Peigang Deng3

1
College of Internet of Things Engineering, Hohai University, Changzhou, P. R. China
2
College of Electronic Science and Technology, Shenzhen University, Shenzhen, P. R. China
3
School of Science, Wuhan Institute of Technology, Wuhan, P. R. China
∗
Email: eexjzhao@szu.edu.cn
VDDH VDDH
Abstract—The level shifters are crucial primitives in the multi-
Large standby
supply voltage circuits and systems. In this paper, an energy- current
MP1 MP2
efficient level shifter is proposed to achieve the conversion from MP1 MP2
VDDH VDDH
the subthreshold voltage to the above threshold voltage. It is a VDDH
hybrid structure consisting of the Wilson current mirror and the OUT
OUT
cross-coupled level shifter. By addressing the voltage drop issue of IN
IN MN1 MN2
the level shifter based on the Wilson current mirror, the leakage MN1 MN2

power is significantly reduced, with the advantage of wide input

voltage range for the Wilson current mirror level shifter well- VDDL
VDDL

preserved. In addition, the multi-threshold CMOS (MTCMOS) Too weak to pull down when IN
is lower than the threshold
technology is employed to provide more flexibility for our ultra- (a) (b)
low power design. The reported simulation results using 65 nm
CMOS process validate our proposed implementation and an
Fig. 1. The schematics of the two convectional level shifters: (a) the cross-
ultra-low power consumption of 19.44 fJ per conversion from coupled structure; (b) the current mirror structure.
0.2 V to 1.2 V at 1 MHz is achieved without the need of any
intermediate power supply.
VDDH
I. I NTRODUCTION
The design concern on maximizing the performance while MP1 MP2
minimizing the power consumption has become more and VDDH VDDH
more critical not only in the mobile consumer electronics but OUT
MP3
also in the wired embedded systems and high-end computing
platforms [1], [2]. In [1], multi-supply-voltage implementation IN
MN1 MN2
has been proven an effective solution to lower the power con-
sumption, and the implementation capable of near-threshold
and subthreshold operations have been proposed to provide VDDL
optimal energy consumption [2]. However, sufficient driving
strength for large capacitance of the interfaces or IO pads
requires normal supply voltage for the related transistors (e.g.
1.8 V). Therefore, the level shifters are always inevitable for Fig. 2. The transistor implementation of the Wilson current mirror based
the conversion between different voltages. level shifter.

In the past few years, a number of level shifter implemen-
tations have been proposed [3]–[7]. Most of them are based
on two conventional designs: the cross-coupled structure and
the current mirror structure [8]. Fig. 1 shows the schematics
of the two designs. It is disclosed that both of them employ
a differential input generated by an inverter stage. The cross-
coupled level shifter in Fig. 1 (a) takes significant advantage
of the full output swing generated by a positive feedback.
The major limiting issue for this design is that the driving
strength for the NMOS pair (MN1 and MN2) is much weaker
than that of the PMOS pair, when the input is below the
threshold voltage of the NMOS pair. This results in the failure
of the output’s toggling. Although the driving strength can be
improved by greatly upsizing the NMOS pair, it is at the cost
of large area and load capacitance. Fig. 1 (b) shows a topology
that uses a current mirror to level shift before the output buffer.
However, the static current flowing through MP1 and MN1
consumes large static power when the input is high. To reduce
this static current, the Wilson current mirror based level shifter
was proposed in [3] (Fig. 2), which adds a feedback PMOS
(MP3) to reduce the static current. However, before the output
buffer, the feedback by MP3 introduces a voltage drop (i.e. Vgs
of MP3) below VDDH, which can cause large static current in
the buffer. The voltage drop can be reduced by upsizing MP3,
nevertheless, it can result in increment of both the delay and
power consumption for the high-to-low transition.
In this paper, we present an energy-efficient level shifter
with a wide input voltage range. It is a hybrid structure of the
Wilson current mirror based level shifter and the conventional
cross-coupled level shifter. By addressing the voltage drop
issue of the level shifter based on the Wilson current mirror,
the leakage power is significantly reduced, while the advantage
of wide input voltage range for the Wilson current mirror

978-1-4799-5341-7/16/$31.00 ©2016 IEEE 726

 VDDH VDDH VDDH

I1
MP4 MP5 MP7 MP8

MP1 MP2 VDDH

OUT
MP6

MP3
IN_NOT IN A B
MN3 MN4 MN5 MN6
IN IN_NOT
MN1 MN2

VDDL
IN IN_NOT High Low Normal
Vth Vth Vth

Fig. 3. The proposed hybrid level shifter with MTCMOS implementation.

Fig. 4. The transient simulation waveforms of the proposed level shifter.

level shifter is well-preserved. Specifically, the voltage drop
of the Wilson current mirror based level shifter before the TABLE I. T RANSISTOR TYPES AND SIZES FOR THE PROPOSED LEVEL
SHIFTER .
output buffer is compensated by the cross-coupled level shifter,
while the input for the cross-coupled level shifter is raised up Transistor Type W/L (nm) Transistor Type W/L (nm)
near or above threshold to reduce the power dissipation and MP1 nvt 120/650 MP2 nvt 120/550
delay. Additionally, the multi-threshold CMOS (MTCMOS) MN1 lvt 120/60 MN2 lvt 350/60
devices are adopted to further reduce the power consumption. MP3 nvt 120/60 MP6 nvt 120/60
MP4 nvt 120/650 MP5 nvt 120/550
The simulation using 65 nm CMOS process indicates that it MN3 lvt 120/60 MN4 lvt 350/60
only consumes 19.44 fJ per conversion from 0.2 V to 1.2 V MP7 hvt 120/1500 MP8 hvt 120/1500
at 1 MHz without requiring any intermediate power supply. MN5 lvt 120/60 MN6 lvt 120/60
MP11* lvt 1200/60 MN11* lvt 1200/60
The rest of the paper is organized as follows. In Section II, MP12* nvt 120/600 MN12* nvt 120/600
the implementation of the proposed level shifter is elaborated. * MP11 and MN11 are for the input buffer. MP12 and MN12 are for the output buffer.
The simulation results are presented and discussed in Section
III. Finally, the conclusion is drawn in Section IV.
current flow through MP1, MP3 and MN1, the node A will be
II. P ROPOSED L EVEL S HIFTER I MPLEMENTATION discharged and the other Wilson current mirror will generate
a complementary waveform of node A at node B as shown
Fig. 3 shows the VLSI implementation of the proposed in Fig. 4. As a result, IN and IN NOT are levelled-up at
level shifter. The MTCMOS technique is employed in the A and B by the Wilson current mirror stages, with the high
design to optimize the delay and the power consumption. voltage level at A or B having a voltage drop due to the
The proposed level shifter mainly consists of two Wilson off-biased PMOS transistors. In addition, the cross-coupled
current mirrors as its initial level-up stage, and a cross- structure further raises the high level voltage to VDDH (i.e.
coupled structure as its output stage. The differential inputs 1.2 V), as shown in Fig. 4. A and B can easily exceed the
are generated by an inverter with low threshold voltage Vth , drive strength of the corresponding PMOS transistors MP7
featuring a shorter delay. Moreover, the Wilson current mirrors and MP8 for successful toggling, resulting from that A or B
raise the input voltage to a voltage near or above the threshold has a high level voltage of above or near threshold of the
of the NMOS. In order to reduce the power consumption, the NMOS MN5 and MN6. It is noted that the high level voltage
lengths of PMOS transistors in the current mirror are larger at node A and B should be well-determined. If it is too high,
than the process feature size. The W/L ratios of the output the power consumption for the whole level shifter will be large.
transistors MP2, MN2, MP5 and MN4 for the current mirror On the other hand, if it is too low, MP7 and MP8 should be
can be increased, in order to achieve a higher speed. The exponentially upsized to enable the successful transition [3].
full swing of the output is maintained by the following cross-
coupled structure, and the pull-down strength is improved by
III. S IMULATION R ESULTS
using low Vth NMOS for MN5 and MN6, while the active
current is limited by using high Vth PMOS for MP7 and MP8. The proposed level shifter, with the transistor sizes listed in
Table I, was simulated using 65 nm 1.2 V CMOS technology
at 27 ◦ C. The performance in terms of the minimum convert-
The operation of the proposed design is described with the
ible VDDL, the power, the speed and the energy consumed
transient simulation waveforms at each node of the design,
per transition are verified through the simulation using the
as shown in Fig. 4. The low supply voltage and the high
provided process design kit (PDK). The simulation results of
supply voltage are set to be 0.2 V and 1.2 V, respectively.
the proposed level shifter show that the minimum convertible
The differential inputs IN and IN NOT generated from the
VDDL are 85 mV and 400 mV for operating frequencies of
inverter stage are at the frequency of 1 MHz. If IN is high and
1 MHz and 100 MHz, respectively. The reported power and
IN NOT is low, MN1 is turned-on. The current I1 can flow
delay include the contribution of the output buffer, which is
through MP1, MP3 and MN1. This current is then mirrored
applied as a load to the proposed design.
and flows through MP2. As MN2 is off, the node A will be
charged until MP3 is turned-off. If IN is low and IN NOT Fig. 5 shows the power consumption dedicated to the Wil-
is high, the MN1 is off and MN2 is on. Since there is no son current mirror stage, the power consumption dedicated to

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Fig. 5. The simulation results of the power consumption by the Wilson Fig. 6. The simulation results of the leakage power for the proposed design,
current mirror stage, the power consumption by the cross-coupled structure the input inverter buffer and the remaining circuitry versus VDDL.
and the overall power consumption in VDDL domain.

the cross-coupled structure and the overall power consumption

as a function of VDDL, which is input at a frequency of 1
MHz, and of which the high voltage level ranges from 90 mV
to 1 V. It is indicated that the total power dissipation for this
proposed design decreases as VDDL reduces. This is primarily
attributed to the driving strengths of MN2 and MN4, which
are limited by VDDL. Moreover, the node A and the node B
cannot be completely discharged to the ground when a small
VDDL is applied. The large low voltage level of A or B causes
a high power consumption for the low Vth transistors MN5
and MN6, which is confirmed by the high power consumption
for the cross-coupled structure when VDDL is low (Fig. 5).
Furthermore, the total power consumption drops dramatically
until VDDL reaches ∼200 mV, and it is 38.87 nW for the Fig. 7. The propagation delay versus VDDL.
voltage conversion from 200 mV to 1.2 V. As there are two
types of conversion in each clock cycle (i.e. low to high and
high to low), the energy per conversion is calculated to be is revealed by the simulation results that the delay is 15.22 ns
19.44 fJ (38.87 nW ÷ 1 MHz ÷ 2). for the Wilson current mirror stage while 6.35 ns for the cross-
coupled structure stage. Although the delay can be further
The leakage power for the proposed design, the input reduced by upsizing the output transistors MP2, MN2, MP5
inverter buffer and the remaining circuitries in VDDL domain and MN4, it is at the expense of higher power consumption
are presented in Fig. 6. Regarding the total leakage power and larger silicon area. In addition, the propagation delay is
consumption, the optimal input VDDL ranges from 160 mV reversely proportional to VDDL. This verifies the proposed
to 380 mV. For example, the leakage power consumption at level shifter is capable of operating at a higher frequency
VDDL of 200 mV is 1.69 nW. The reason why the leakage with VDDL increased. The overall power consumption in the
power consumption in the low VDDL domain is high is that operating frequency domain is shown in Fig. 8, which is
the low VDDL cannot completely discharge A or B to the linearly proportional to the input frequency.
power ground. More leakage power is needed for the higher
low level input of low Vth transistors MN5 and MN6 (Fig. Furthermore, the concern of process variation has become
6). When VDDL deviates 400 mV, the total leakage power more and more significant for the subthreshold analog circuit
increases since the leakage power for the input inverter buffer design [6]. The robustness of the proposed level shifter against
implemented with low Vth transistor increases as indicated by the process variations has been verified with extensive Monte
Fig. 6. Figure 7 shows the relationship between the propagation Carlo simulations, where 100 runs of transistor-level Monte
delay and the VDDL. It is indicated that the propagation delay Carlo simulation have been performed for the voltage conver-
is 21.65 ns at the VDDL of 200 mV. This delay is mainly sion from 0.2 V to 1.2 V. Both switches of the inter-die and
contributed by the Wilson current mirror stage. Concretely, it intra-die process variations are turned-on in the simulation.

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 TABLE II. P ERFORMANCE COMPARISON WITH THE PREVIOUS SUBTHRESHOLD TO ABOVE THRESHOLD LEVEL SHIFTERS .

Process (nm) VDDH (V) Min VDDL (V) Delay (ns) Energy per transition (fJ) Leakage power (pW)
TCAS-II’10 [3]* 90 1 0.1 7@0.3 → 1 22@0.3 → 1 7,000 @0.3 → 1.8
JSSC’12 [4] 350 3 0.23 10,000 @0.4 → 3 5,800@0.4 → 3 230 @0.4 → 3
TCAS-I’14 [5] 65 1.2 0.2 300@0.2 → 1.2 136@0.3 → 2.5 NA
ISCAS’15A [6]* 180 1.8 0.19 21.6@0.4 → 1.8 390@0.4 → 1.8 160 @0.4 → 1.8
ISCAS’15B [7]* 180 1.8 0.32 31@0.4 → 1.8 680@0.4 → 1.8 1160 @0.4 → 1.8
This work* 65 1.2 0.085 21.65@0.2 → 1.2 19.44@0.2 → 1.2 1690@0.2 → 1.2
* Simulation results.
IV. C ONCLUSION
This paper presents a novel energy-efficient subthreshold
level shifter design. The proposed hybrid structure combining
the Wilson current mirror and cross-coupled level shifter
takes the advantages while overcomes the drawbacks of the
two structures. In addition, MTCMOS devices are applied
to achieve a low power/energy consumption. The simulation
results using 65 nm CMOS technology show it only consumes
19.44 fJ per conversion for 0.2 V to 1.2 V conversion at an
operating frequency of 1 MHz, with the input high voltage
level as low as 85 mV. Moreover, the proposed implementa-
tion’s reliability against the process variations is verified by the
extensive Monte Carlo simulation with 100% pass rate. As a
result, this energy-efficient level shifter with a wide input range
Fig. 8. The total power consumption in the operating frequency range. can find applications in the interfaces between subthreshold
and above threshold voltage modules.
ACKNOWLEDGEMENT
This work was supported by the CRSRI Open Research
Program (Grant No. CKWV2014225/KY), Wuhan Science and
Technology Bureau Grant (Grant No. 2015010101010002),
the National Natural Science Foundation of China (Grant
No. 61504087), the Kongque Technology Innovation Foun-
dation of Shenzhen (Grant No. KQCX20120807153227588),
the Fundamental Research Foundation of Shenzhen (Grant No.
JCYJ20140418095735624 and JCYJ20150324141711677).
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