This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2933288, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
A Hybrid Modular DC/DC Converter for HVDC
Applications
Binbin Li, Member, IEEE, Xiaodong Zhao, Student Member, IEEE, Shuxin Zhang, Qintian Fu,
Shengbo Wang, and Dianguo Xu, Fellow, IEEE
Abstract—Recently, remarkable progress has been made in the
voltage source converter (VSC) based high voltage direct current
(HVDC) transmissions. For the upcoming need to interconnect
multiple DC transmission lines with different voltage levels, high
voltage and large power DC/DC converters are necessary. This
paper investigates a non-isolated bidirectional DC/DC converter
which is composed by cascaded half-bridge SMs, series connected
diodes, and mechanical disconnectors. This hybrid topology
presents very attractive features such as low cost, high efficiency,
and light weight. Operation principle, parameter design, and
dedicated control strategies are developed. Simulation of a
150MW, 200kV/300kV DC/DC converter has been performed to
verify its performance and evaluate the efficiency. Moreover, a
downscaled three-phase prototype rated at 500V/300V 4.5kW has
been built and tested. The experimental results further confirm the
effectiveness of the proposed DC/DC converter.
Index Terms—Bidirectional DC/DC converter, mechanical
disconnectors, hybrid topology, energy buffering string, HVDC,
diodes, high robustness.
I. INTRODUCTION
ITH the continuous progress in the field of voltage-
W source-converter (VSC) technology, particularly the
development of modular multilevel converter (MMC) [1], [2],
the VSC-HVDC has been increasingly used for offshore wind
power transmission and asynchronous grids interconnection [3].
Recently, VSC-HVDCs in multi-terminal and even the HVDC
grids are highly expected in both academia and industry for
better integration of large-scale renewable energy sources and
strengthening the network stability and reliability [4]. Several
multi-terminal HVDCs have already been in operation while
one piolet project of a ±500kV/9000MW HVDC grid is
currently under construction [5], [6].
However, compared to the mature AC grids, two major
technical challenges have to be addressed in future HVDC grids:
1) DC circuit breaker (CB) and 2) DC transformer. Because of
the absence of natural current zero in HVDC grids, a DC CB
must be able to create an artificial current zero while absorbing
the fault energy from DC transmission line plus any added DC
inductance. Recent advances of hybrid DC CBs, consisting of
mechanical ultrafast disconnector (UFD) and IGBT–based
main breaker as well as a load commutation switch, can satisfy
the requirements and achieve very short interruption time (2-3
ms) [7], [8]. Many hybrid DC CB topologies have recently been
proposed and industrial prototypes have also been developed
[9]–[11]. On the other hand, DC transformer is required to
match the HVDC lines with different voltage levels [12]. As
This work was supported by National Key Research and Development
Program of China under Grant 2018YFB0904600 and by National Natural
Science Foundation of China (51807033).
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1
magnetic transformer is not possible for DC voltage conversion,
power electronics technology must be used. There are plenty of
DC/DC converter topologies in low power applications, but
most of these topologies cannot be readily scaled up to
hundreds of kilovolts and megawatt power ranges, due to the
limitations of losses, cost, dv/dt, filter size, and voltage rating
of the semiconductors. To overcome these limitations, several
novel HV DC/DC converter topologies based on modular
structure have been proposed during the last few years, which
utilize series connection of submodules (SMs) in place of series
connection of semiconductors so as to effectively share the
voltage stress and improve efficiency [13]. These novel DC/DC
topologies can be classified into two categories, according to
whether there is galvanic isolation, i.e., isolated types [14]–[18]
and non-isolated types [19]–[28]. The common feature of the
isolated DC/DC converter topologies is that they are based on a
front-to-front (FTF) configuration, which utilizes two full-
power DC/AC conversion stages (usually MMC) and an AC
transformer. This is a relatively costly solution as each stage
must process the full power, resulting in very high components
count and high power losses. As a consequence, the isolated
topologies are more promising for applications with a large DC
voltage ratio (e.g., interconnection of HVDC and MVDC
systems [18]) or very strict galvanic isolation requirement.
The non-isolated DC/DC converter topologies, on the other
hand, are more suitable for interconnecting HVDC lines with a
small voltage ratio. In [19]–[22], the single-stage MMC DC/DC
topology is introduced, in which part of the SMs are utilized on
both the high-voltage and low-voltage sides, hence it is more
efficient than the FTF topologies. However, high magnitude
AC voltages and circulating currents need to be injected in the
MMC to exchange power between the upper and lower arms,
such that the power balance of each SM capacitor can be
maintained. Bulky HV filters are therefore required to isolate
the injected AC voltages from appearing at the DC terminals.
In [23], an additional SM branch was added at the low-voltage
DC terminal which actively attenuates the injected AC voltage,
but this is at the expense of much higher component count and
losses. Besides, the DC/DC auto transformer concept was
proposed in [24], in which two MMCs are series connected at
the DC terminals whereas parallel connected at the AC
terminals through a partial-power AC transformer. In this
topology, only part of the total power was transmitted through
the AC transformer while the remaining part is transferred
directly through the DC path. Thus, capacity of the AC
The authors are with the School of Electrical Engineering and Automation,
Harbin Institute of Technology, Harbin 150001, China (e-mail:
libinbin@hit.edu.cn; xudiang@hit.edu.cn).
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transformer and the converter loss can be reduced. Based on this iLc iHc
FD1c
concept, a multiport DC auto transformer topology has also D2c
D1c
been reported [25]. In [26], to avoid the use of the bulky AC FD1b
iLb iHb
transformer (which suffers high DC offset voltage stress) in the
D1b D2b
DC auto transformer, the AC transformer was replaced by a FD1a
IL iLa iHa IH
cross-connected SM branch between the upper and lower arms.
D1a D2a
Meanwhile, in [27] and [28], a novel hybrid cascaded DC/DC iPa iPb iPc
converter (HCDC) was proposed, with each phase constructed L L L
by two branches of series-connected IGBTs and one branch of
cascaded SMs. The cascaded SMs operate as an energy storage SM1 SM1 SM1
element, which connects with one DC side to store a certain
amount of energy and then switches to the other side to release SM2 SM2 SM2

the absorbed energy. The poly-phase structure is employed uPa

which avoids the DC power flow being interrupted by single-
UL UH
phase switching action. This topology requires few additional SMN SMN SMN

components beside several small inductors, hence it shows very D3a

small footprint. However, the disadvantage of this topology is
that it needs direct series connection of a large number of
IGBTs. In brief summary, the existing DC/DC topologies are
either technically complex or expensive, which hinders their
application and results in the development of HV DC/DC
converter falling far behind the DC CBs.
This paper presents a new hybrid modular DC/DC converter
(HMDC) topology for HVDC applications. By incorporating
several mechanical disconnectors, the topology can achieve
efficient bidirectional DC/DC conversion with only limited
number of cascaded half-bridge SMs and series connected
diodes, showing very attractive features of low cost, high
efficiency, and simplicity. The circuit configuration as well as
its operation principle, parameter design, modulation and
control schemes, are presented and verified by simulation
results. Moreover, a downscaled prototype has been built and
tested to further confirm effectiveness of the proposed topology.
II. PRINCIPLE OF OPERATION
A. Circuit Configuration
Circuit configuration of the proposed hybrid modular
DC/DC converter (HMDC) is shown in Fig. 1. It contains three
interleaved phases (j=a, b, c); each phase is formed by four
branches of series connected diodes (D1j, D2j, D3j, and D4j) and
one energy buffering string formed by series connected SMs
and an inductor L. There are a total of N SMs in each string and
each SM is a half-bridge circuit. Particularly, mechanical
disconnectors FD1j and FD2j are paralleled with D2j and D4j,
respectively. FD1j and FD2j are used to achieve bidirectional
power transfer capability and they are in complementary
operation: FD2j is kept on while FD1j is off when power is
transmitted from the low-voltage (LV) side to the high-voltage
(HV) side; whereas FD2j is off while FD1j is on when power is
transmitted in the opposite direction. The terms UL and IL are
the voltage and current of the LV DC side, and UH and IH are
the voltage and current of the HV DC side, respectively. iLj and
iHj represent the currents of each phase at the LV and HV sides,
respectively. UC is the SM capacitor voltage, thus the SM
terminal voltage is UC when S1 is on and S2 is off, whereas the
SM terminal voltage is 0 when S1 is off and S2 is on. uPj is the
sting voltage which is summation of the N SM terminal voltages,
and iPj is the string current.
Sub-module
D3b
S1
D3c
CSM UC
FD2a FD2b FD2c
S2
D4a D4b D4c
Fig. 1. Configuration of the proposed hybrid modular DC/DC converter
(HMDC) topology.
B. Operation Principle of the HMDC Topology
Fig. 2 shows the operation waveforms of the HMDC
topology when DC power is transferred from the LV side to the
HV side. The energy buffering string alternatively connects
with the two DC terminals, to store a certain amount of energy
from LV DC side during [0, 0.5Th] and then release the energy
to the HV DC side during [0.5Th, Th], where the string current
iPj is controlled as trapezoid waveforms with positive and
negative amplitudes of IL and IH, respectively. Hence, the string
current would flow through D1j when iPj>0 and D2j when iPj<0,
respectively. Meanwhile, the diodes D3j are kept reversely
blocked while D4j are bypassed as the disconnectors FD2j are
closed. The three-phase waveforms of HMDC are interleaved
with 120°electrical angle. Despite the iHj and iLj in one phase
of HMDC are discontinuous, the total DC currents iH and iL,
given by summation of the three-phase iHj and iLj currents, are
ensured to be continuous DC, as a result of the ripple
cancellation effect of interleaved waveforms.
The string voltage uPj not only needs to alternatively match
the LV and HV DC voltages, but also includes an extra U0
component which is imposed across the inductor to regulate the
iPj waveform during the current rising or falling process Tcp.
Besides, to avoid generating excessive dv/dt, a staircase shaped
waveform is utilized during the rising and falling transitions of
uPj, which limits the voltage slew rate by sequentially switching
the SMs at an interval of a few microseconds [16].
On the other hand, Fig. 3 presents the waveforms of HMDC
when power is transferred from the HV side to the LV side. In
this mode, the diodes D1j are reversely blocked while the D2j are
bypassed as the disconnectors FD1j are closed. The energy
buffering string is firstly inserted between the HV and LV DC
sides to absorb a certain amount of energy during [0, 0.5Th], and
then parallels with the HV side during [0.5Th, Th] to release the

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2933288, IEEE
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Therefore, without considering SM redundancy, the required

iLa iLb iLc
IL number of SMs in energy buffering string can be calculated as
U H +U 0
t N= (1)
o (1 −  2)U C
iHc iHa iHb where UC is the nominal voltage of SMs, and ε is the peak-to-
IH
t
peak capacitor voltage ripple.
o On the other hand, the maximum current transition driving
iPa iPb iPc voltage U0 can be obtained as
IL
max ( I H ,I L -I H )
U0 = L (2)
t Tcp
o
where max(IH, IL-IH) denotes the maximum value of iPj when
-IH
the energy buffering string parallels with the HV DC side,
uPa under both the conditions of Fig. 2 and Fig. 3.
U0
UH The total number of IGBTs in each energy buffering string is
UL therefore 2N. From Figs. 2 and 3, it is shown that the current
Tcp stress of the IGBTs is determined by the maximum value of the
t
o
string current iPj, which is IL.
0 0.5Th Th
Fig. 2. Sketched key waveforms of the HMDC when power is transferred
B. SM Capacitance
from the LV side to the HV side. Role of the SM capacitors is to tolerate the energy
fluctuations of each buffering string. Under steady states, in
o each cycle Th, the absorbed energy should be equal to the
t
released energy. Hence, when power is transferred from LV to
iLa iLb iLc HV sides, energy variation of the string can be calculated by
-IL
integrating the power during half cycle [0, 0.5Th], as in Fig. 2,
iHa iHb iHc
IL-IH t which is
o U I T 1 P
ΔE1j = 
0.5Th
uPjiPjdt = L L h = 3 (3)
0 3 fh
-IL
where P=ULIL=UHIH is the rated DC power and fh is the
IL
iPa iPb iPc operation frequency.
This energy variation has to be buffered by the N SM
t capacitors in each string, that is
o

( )
1 P 1
IH-IL 3
= NC U C,2 max − U C,2 min = NCU C2 (4)
fh 2
uPa
UH which further gives
Tcp 1 P
3
C= (5)
UH-UL
t NU C2 f h 
o
0 0.5Th Th On the other hand, when power is transferred from HV to LV
Fig. 3. Sketched key waveforms of the HMDC when power is transferred sides, the energy variation can be obtained as
from the HV side to the LV side. 0.5Th (U − U L ) I LTh 13 P (k − 1)
energy and maintain the power balance, where the string current ΔE2j =  uPjiPj dt = H = (6)
0 3 fh
iPj is controlled as trapezoid waveforms and its positive and
where k stands for the voltage ratio (k=UH/UL).
negative amplitudes are IL and IL-IH, respectively. Hence, the
Similarly, the required SM capacitance can be derived as
string current would flow through D3j when iPj>0 and D4j when
iPj<0, respectively. The string voltage uPj alternatively matches 3 ( )
1 P k −1
C= (7)
UH-UL and UH, meanwhile an extra voltage component is NU C2 f h 
needed to drive the rising and falling processes of iPj waveform. Accordingly, it is found the SM capacitance depends on the
DC power direction. Hence, the required SM capacitance for
III. COMPONENT REQUIREMENTS AND CIRCUIT ANALYSIS the bidirectional HMDC can be determined by selecting the
maximum value between (5) and (7):
A. Sub-Modules
 13 P
As stated in the operation principle, the energy buffering  NU 2 f  , k  2
string in the proposed HMDC either connects with the DC  C h
C=  (8)
 3 ( )
1 P k −1
terminals or is inserted between the HV and LV sides. Thus, the
, k  2
string voltage uPj should always be able to match the voltage of  NU C2 f h 
HV side plus an extra current transition driving voltage U0.

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C. Series-Connected Diodes Compared with the IGBTs employed in [27], diodes exhibit
To withstand hundreds of kilovolt, the diodes in the HMDC many salient features. For comparison, two commercial devices
must be used in series. With respect to the diode branches D1j of similar current rating (5SNA3000K452300 IGBT [29] and
and D2j, when power is transferred from the LV to HV sides, 5SDD50N6000 Diode [30]) are compared, as listed in Table I.
they are alternately conducted. Consequently, the maximum Diodes have higher voltage ratings, hence the number for series
voltage stress they need to withstand is the voltage difference connection as well as the associated cost and complexity, can
between the HV and LV sides. On the other hand, when power be reduced. Furthermore, in terms of series connection of
is reversed, D2j are bypassed by disconnectors FD1j while D1j IGBTs, both active gate clamping control and passive snubbers
are reversely blocked which still withstand the voltage are required to achieve static and dynamic voltage sharing. On
difference between the HV and LV sides. Therefore, the the contrary, only passive snubbers are necessary with respect
required number of series-connected diodes in D1j and D2j is to the series connection of diodes. Moreover, diodes present
U −UL lower on-state voltage drop which means lower power losses.
ND1 j, D2 j = H (9) For instance, the 5SNA3000K452300 IGBT conducting a
dU B current of 3000A is expected to have a forward voltage drop of
where UB is the rated blocking voltage of each diode and λd is 3.65V, whereas the 5SDD50N6000 conducting the same
the voltage derating factor in terms of series connection. amount of current only gives an 1.2V voltage drop. Besides,
Analogously, the diodes D3j and D4j have to withstand the diode has much higher surge current robustness than IGBT.
voltage of LV DC side, which yields Therefore, by fully developing the current controllability of the
U energy buffering strings in the proposed HMDC topology,
N D3 j, D4 j = L (10)
dU B diodes can be adopted, which reduces the capital cost, losses,
and the difficulty in series connection.
On the other hand, with respect to the current rating, diode
D1j only conduct the DC current IL during one third of the D. Fast Mechanical Disconnectors
operation cycle, because of the 120° waveform interleave In the proposed HMDC, mechanical disconnectors are used
among the three phases. Hence, the average current of the diode to achieve bidirectional power transfer capability. The
branch D1j can be expressed as mechanical disconnectors FD1j and FD2j are paralleled with D2j
1 2π / 3 I

and D4j, respectively. Thus, the FD1j should have the ability to
I F(AV)-D1j = I L d = L (11)
2π 0 3 withstand the voltage difference between the HV and LV sides,
In a similar way, average currents of the diode branches D2j, i.e., UH-UL. Similarly, the FD2j should withstand the voltage of
D3j and D4j can be expressed as (12), (13), and (14), respectively LV side, i.e., UL. The current stress of FD1j and FD2j is
1 2π / 3 I determined by the maximum value of the string current iPj,
I F(AV)-D2 j =
2π 0
I H d = H
3
(12) which is IL.
Since mechanical actions are usually slow, it is necessary to
1 2π / 3 I

I F(AV)-D3 j = I L d = L (13) examine whether the FD1j and FD2j can satisfy the power
2π 0 3 reversal speed. In HVDCs, the power regulation speed is
1 2π / 3 (I − I ) usually not rapid, up to 100MW per minute [31]. Thus, it
I F(AV)-D4 j =  ( I L − I H )d = L H (14) provides the opportunity to use relatively slow mechanical
2π 0 3 switches. However, in some emergency cases if very fast
and these values should not exceed the maximum forward processing of power reversal is intended (typically up to
current value (IFAVM) of the selected diodes. 200MW per second [31]), fast mechanical switches must be

TABLE I
CHARACTERISTICS COMPARISON BETWEEN THE IGBT AND DIODE

IGBT Diode

Product type 5SNA 3000K452300 5SDD 50N6000

Maximum blocking voltage 4.5kV 6kV
Rated on-state current 3000A 4210A
Voltage balancing in terms of Active di/dt and dv/dt gate
series connection control and passive snubber Passive snubber only

3.65V 1.2V
On-state voltage
@Ic=3000A, TVj=125℃ @IFM=3000A TVj=125℃

Surge current capability 21000A+ 71200A++

+
Determined by the desaturation current and I2t, Tvj=125°C, tp=10ms, half-sinewave.
++
Determined by I2t, Tvj=150°C, tp=10ms, half-sinewave.

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DC power control
wave generator 1 FD 1a switch logic
SFD1a
1
Mechanical Disconnectors FD 2a switch logic
SFD2a
Control Logics
insert Ns SMs for ZVZCS
|Pref| iPa_ref_P SM Gating
PI Signals
=0
P String current control if Pref
iPa_ref uPa_ref !=0
PI
Energy storage regulator iPa PSC-
UC_ref iPa_ref_N PWM
PI
UC_avg SM cap. voltage balancing control
UC_avg Δu(k)
P
-1 UC(k)
wave generator 2 iPa sign(x)

Fig. 4. Control block diagrams for the proposed HMDC converter.

employed. Borrowing from the hybrid HVDC circuit breakers, signals is adopted, where UC(k) is the k-th SM capacitor voltage
ultrafast disconnectors (UFD) are available which are capable (k=1, 2, …, N). The polarity of Δu(k) is changed according to
of opening within several milliseconds (2~3ms) at the nearly the signum of string current, which ensures a correct logic to
zero current condition [7]. In the proposed HMDC topology, charge or discharge the capacitors. Finally, the obtained
thanks to the current controllability of the energy buffering reference voltages are sent to the PSC-PWM generator which
string, FD1j and FD2j can also achieve zero-voltage and zero- synthesizes the gating signals for the SM IGBTs.
current (ZVZC) opening and closing. As a result, there is no
B. Mechanical Disconnectors Control Logics
technology barrier to employ UFDs in the HMDC and satisfy
both normal and emergency power reversal conditions. As described earlier, the mechanical disconnectors can
achieve ZVZC opening and closing owing to the highly
IV. CONTROL SCHEMES controllable energy buffering string. In steady-state operation,
when power is transmitted from LV side to the HV side (Pref>0),
A. General Control FD2a is kept on (SFD2a=1) while FD1a is off (SFD1a=0); whereas
Suitable control schemes are necessary to ensure proper FD2a is off (SFD2a=0) while FD1a is on (SFD1a=1) when power is
operation of the proposed DC/DC converter. The general
Power Insert Ns SMs
architecture of the controller is presented in Fig. 4, in which reversal for ZVZC
Pref activation
phase a is taken as an example. The control system can be condition
Open Close
divided into six main parts: DC power control, energy storage FD 2a FD 1a
regulator, string current control, SM capacitor voltage t
0
balancing, phase shifted carrier pulse-width modulation (PSC-
Tdelay1 Tdelay2
PWM), and control logics of the disconnectors.
The DC power control manages the transferred power 1 SFD1a

between LV and HV sides. This control block generates the t

0
positive amplitude of the string current reference, iPa_ref_P. Then SFD2a
1
the energy storage regulator compares the average SM t
capacitor voltage UC_avg (which represents the total stored 0
energy in the string) against the nominal value UC_ref and
determines the negative amplitude of string current reference, FD1a FD1a
iPa_ref_N, to ensure power balance of the string. Subsequently, the D1a D1a
D2a D2a
string current reference iPa_ref can be obtained by summing
iPa_ref_P and iPa_ref_N. The string current control further produces L L

the string voltage reference uPa_ref for shaping the desired UL UH UL UH

current waveform. Besides, by limiting the slew rate of the UH UH
D3a D3a
proportional-integral (PI) controller, the rising and falling
transitions of the final string voltage waveform uPa can be FD2a FD2a
automatically staircase shaped (i.e., switching the SMs D4a D4a
sequentially to avoid generating excessive dv/dt).
In addition, to balance the SM capacitor voltages, voltage
Fig. 5. Timing diagram of the disconnector control logics during power
balancing control based on adjustment of the voltage reference reversal of the HMDC.

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transmitted in the opposite direction (Pref<0). diagram of the switching sequences. Once detecting the power
During power reversal condition, Fig. 5 shows the timing command reaching zero, gating signals of the SMs will be

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Fig. 6. Simulation results of the proposed DC/DC converter. (a) transmitted DC power; (b) control logics of mechanical disconnectors; (c) voltage of two DC
sides; (d) currents of two DC sides; (e) currents of energy buffering string; (f) voltages of energy buffering string; (g) SM capacitor voltages; (h) currents of FD1a
and FD2a; (i) voltages of FD1a and FD2a.

generated by disconnector control logics instead of the PSC- TABLE II

PWM generator. At this instance, the string voltage reference SIMULATION PARAMETERS
uPa_ref is set as UH and then divided by the value of the capacitor Converter Parameters Value
voltage to round down to the closest voltage level, Ns. After Rated DC power P=150MW
knowing Ns, the controller inserts Ns SMs to counteract the HV
HV DC voltage UH=300kV
DC side voltage UH. The final voltage of energy buffering string
may be slightly smaller than UH, but the difference can be LV DC voltage UL=200kV
limited less than one capacitor voltage UC (corresponding to the No. of SMs in each string N=180
rounding error). As a result, voltage stresses of the Average SM capacitor voltage UC=2kV
disconnectors during both opening and closing are quite low, SM capacitance C=2mF
and in the meantime, currents of the disconnectors are zero
SM capacitor voltage ripple ε=20%
since the power is null. This means a ZVZC switching
condition has been created by the energy buffering string. The PSC carrier frequency fc=580Hz
control signals of disconnectors (SFD1a and SFD2a) are then Operation alternating frequency fh=250Hz
inversed after certain time delays, Tdelay1 and Tdelay2. These delay Arm inductance L=10mH
times are determined by the opening and closing speed of the
Control Parameters Value
selected disconnectors. After that, controllers of the PSC-PWM
generator and capacitor voltage balancing control are enabled Proportional gain of energy regulator 0.01A/V
again and the power begins transferring in the opposite Integral gain of energy regulator 1A/Vs
direction. Proportional gain of current control 720V/A
In summary, using mechanical disconnectors, the proposed Integral gain of current control 72kV/As
HMDC topology achieves bidirectional DC/DC power transfer
capability. The mechanical disconnectors are basically opened
and closed at ZVZC condition, thus they can be made in strings operate with 120° electrical angle apart, which can be
lightweight [7]. observed in the zoomed regions of the waveforms. As a result,
the identical but interleaved string currents guarantee a
V. SIMULATION STUDY continuous and smooth DC current waveform. Besides, the 180
In order to access validity of the proposed topology and SM capacitor voltages in phase a are shown in Fig. 6(g) which
control strategies, simulation of an 150MW HMDC which were kept well balanced around the rated voltage of 2kV. Figs.
connects two HVDC systems with voltages of 300kV and 6(h) and (i) further present the currents (iFD1a, iFD2a) and voltages
200kV, is performed in MATLAB/Simulink software. In each (uFD1a, uFD2a) of the mechanical disconnectors FD1a and FD2a.
energy buffering string, there are a total of 180 SMs and each These results confirm the effectiveness of the proposed DC/DC
rated SM voltage is 2kV. Detailed parameters of the simulated converter and the control strategies.
circuit and operating conditions are listed in Table II. Moreover, Fig. 7 demonstrates the detailed steady-state
Fig. 6 displays the key simulation results of the proposed waveforms of phase a when the power is transferred from the
DC/DC converter. As shown in Fig. 6(a), initially, the rated DC HV side to the LV side. The energy buffering string either
power was transferred from the HV side to the LV side. The inserts between the HV and LV DC sides (uPa around 100kV)
disconnectors FD1j were kept closed while the disconnectors or parallels with the HV side (uPa around 300kV). And the
FD2j were opened, as shown in Fig. 6(b). Then, between 0.3s diodes D3a and D4a alternatively conducted the string current, as
and 0.5s, the power was ramped from –150MW to 0. After shown in Fig. 7(b), thus the diode voltages uD3a and uD4a would
power reached zero, the control logics of FD1j and FD2j were alternatively withstand the LV side voltage UL, as displayed in
inversed, which reconfigured the HMDC topology to transfer Fig. 7(c). Observing the voltage of energy buffering string in
power from the LV side to the HV side; afterwards, the power Fig. 7(d), the zoomed-in view presents a staircase shaped
was gradually increased from 0 to 150MW and maintained waveform during the falling transition (rising transition is
150MW after 0.8s, meaning the power flow was completely identical), so that the dv/dt stress can be well limited. In Fig.
reversed. Figs. 6(c) and (d) show the voltages (UH and UL) and 7(e), the SM capacitor voltages are depicted, which are well
currents (iH and iL) of the two DC terminals, respectively. Figs. balanced.
6(e) and (f) show the voltages and currents of the three-phase
energy buffering strings. It is shown that the energy buffering

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2933288, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
Fig. 7. Detailed waveforms of the proposed DC/DC converter when rated DC
power is transmitted from the HV side to the LV side: (a) current of FD1a; (b)
currents of D3a and D4a; (c) voltages of D3a and D4a; (d) voltage of energy
buffering string; (e) SM capacitor voltages.
Similarly, if the DC power is delivered from the LV side to
the HV side, detailed waveforms in phase a under this case are
summarized in Fig. 8. Fig. 8(b) and (c) show the current and
voltages of D1a and D2a. It is shown the string current iPa was
alternatively conducted through these diodes. Notice that, the
capacitor voltage fluctuation in Fig. 8(e) is approximately
doubled comparing to Fig. 7(e), which can be explained by Eq.
(2) and (5), and the voltage ratio k equals 1.5.
To verify the opening and closing performances of the
mechanical disconnectors, waveforms during the power
reversal transients are further zoomed in and displayed in Fig.
9. At 0.5s, the DC power flow was ramped up to zero; and the
currents of mechanical disconnectors (iFD1a and iFD2a) both
stayed at ZC status, as shown in Fig. 9(c). On the other hand,
the energy buffering string inserts appropriate number of SMs
to counteract with UH, resulting in almost ZV status for the
mechanical disconnectors, as described in Fig. 9(d) and (e). The
further zoomed-in view of disconnector voltages uFD1a and uFD2a
are displayed in the dotted box in Fig. 9(e). It can be observed
there was only a small voltage across FD1a and FD2a. Afterward,
the controller inversed the control logics (SFD1j and SFD2j)
sequentially at ZVZC conditions, as in Fig. 9(b). In brief
summary, thanks to the high controllability of the energy
buffering string, ZVZC closing and opening of the mechanical
disconnectors can be realized.
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8
Fig. 8. Detailed waveforms of the proposed DC/DC converter when rated DC
power is transmitted from the LV side to the HV side: (a) current of FD 2a; (b)
currents of D1a and D2a; (c) voltages of D1a and D2a; (d) voltage of energy
buffering string; (e) SM capacitor voltages.
VI. EXPERIMENTAL VERIFICATION
A. Experimental Prototype Setup
In order to further verify the validation of the proposed
DC/DC converter, a downscaled three-phase prototype rated at
500V/300V, 4.5kW has been built in the authors’ laboratory, as
shown in Fig. 10. Each energy buffering string contains seven
SMs, and each SM is comprised of two IGBTs (Infineon
IKW30N60T) and an 1mF capacitor. Two DC voltage sources
are connected to the proposed HMDC to emulate two HVDC
systems. The diode branches adopt the DD100N16S (Infineon),
and the mechanical disconnectors adopt the LC1D09BDC
(Schneider Electric). The main circuit parameters are collected
in Table III. A digital signal processor TMS320F28335 DSP
plus an EP3C25Q240C8 FPGA are employed to realize the
control algorithms. Moreover, each SM is controlled by an
independent EPM570T100 CPLD.
B. Experimental Results
Fig. 11 presents the experimental results for verifying the
bidirectional power transfer capability. In this experiment, the
proposed HMDC initially transmitted 4.5kW power flow from
the HV side to LV side, and then turned into power reversal
process. Eventually, the power flow was transmitted from the
LV side to HV side. In this entire process, the DC currents (iH
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TABLE III
EXPERIMENTAL PARAMETERS
Converter Parameters Value
Rated DC power Pmax=4.5kW
HV DC voltage UH=500V
LV DC voltage UL=300V
No. of SMs in each string N=7
Average SM capacitor voltage UC=85V
SM capacitance C=1mF
PSC carrier frequency fc=6kHz
Operation alternating frequency fh=250Hz
Arm inductance L=1mH
Capacitor bleeding resistor Rb=12kΩ
Control Parameters Value
Proportional gain of energy control 0.05A/V
Integral gain of energy control 0.5A/Vs
Proportional gain of current control 5.95V/A
Integral gain of current control 279.60V/As

Fig. 9. Zoomed waveforms of the closing and opening processes of FD1a and
FD2a: (a) DC power; (b) disconnector control logics; (c) currents of FD1a and
FD2a; (d) voltage of energy buffering string; (e) voltages of FD1a and FD2a.

Fig. 11. Experimental results of the proposed DC/DC converter under power
reversal: (a) voltages and currents of the two DC sides; (b) capacitor voltages
of the SMs uCa1~uCa6; voltages and currents of energy buffering string.

confirmed the effectiveness of the DC/DC topology as well as

the proposed control strategies.
Fig. 10. Photograph of the laboratory prototype. The detailed steady-state waveforms of the DC/DC converter,
when power was transferred from the HV to the LV side, were
given in Fig. 12. In this case, the FD1j was closed to provide
and iL) satisfactorily followed their reference and maintained
bidirectional current path as shown in Fig. 12(c), while the FD2j
continuous and smooth, as described in Fig. 11(a). However,
was opened. It can be observed from Fig. 12(b), the three-phase
some visible harmonics existed and this is due to the limited
string current waveforms were almost identical but interleaved
number of SMs in each string in the experiment, as a result,
with 120°electrical angle, resulting in continuous HV and LV
switching of one SM would cause non-negligible harmonics
DC currents iH and iL. On the other hand, Fig. 13 shows the
and influence the current waveform quality. Besides, the SM
steady-state operation waveforms of the proposed DC/DC
capacitor voltages remained stable and well balanced during the
converter, when power was transmitted from the LV to the HV
whole process, as described in Fig. 11(b). These results again

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Transactions on Power Electronics
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iH , iL (5A/div)
iH , iL (5A/div)

uH , uL (250V/div)
uH , uL (250V/div)

[2ms/div] [2ms/div]

(a) (a)

(b) (b)
1 1
0 SFD1a 0 SFD1a
1 1 SFD2a
0 SFD2a 0
iFD1a,iFD2a (5A/div) iFD1a,iFD2a (5A/div)

[2ms/div]
(c)
Fig. 12. Experimental results of the proposed DC/DC converter when power is
transmitted from the HV side to the LV side: (a) currents and voltages of the
two DC sides; (b) capacitor voltages of the SMs uCa1~uCa6; voltages and currents
of the energy buffering string; (c) control logics and currents of FD1a and FD2a.
[2ms/div]
(c)
Fig. 13. Experimental results of the proposed DC/DC converter when power is
transmitted from the LV side to the HV side: (a) currents and voltages of the
two DC sides; (b) capacitor voltages of the SMs uCa1~uCa6; voltage and current
of the energy buffering string; (c) control logics and currents of FD1a and FD2a.

side. Control logics of the mechanical disconnectors are
inversed compared to Fig. 12, and the DC currents are reversed.
Finally, Fig. 14 shows the transient performances under
power reversal, where the voltages and currents across the
mechanical disconnectors (FD1a and FD2a) as well as the
corresponding control signals (SFD1a and SFD2a) are displayed. It
can be observed in the zoomed region that the disconnector
currents iFD1a and iFD2a were controlled to zero as the power
ramped down to null. And then, the energy buffering string was
forced to withstand the HV side voltage, so as to create almost
ZV condition for the disconnectors, as shown in the uFD1a and
uFD2a waveforms. These results coincide with the timing
diagram as described in Fig. 5. It again confirmed the feasibility
of employing mechanical disconnectors to fulfill bidirectional
DC power transfer.
VII. LOSS EVALUATION AND DISCUSSIONS
In attempt to evaluate the losses of the proposed DC/DC
converter, a simulation model rated at 300kV/200kV, 150MW
is further performed by co-simulation between
MATLAB/Simulink and PLECS software. Considering the
series connected diodes (D1j, D2j, D3j, and D4j) operate in ZCS
manner and the operation frequency is relatively low (250Hz in
this simulation), the grid-commutated rectifier diode
6.8kV/1.59kA D1481N (Infineon, Press-pack, VT0=0.75V) are
adopted. And the voltage derating factor λd is set as 0.7.
According to (9) and (10), 21 diodes are required in D1j and D2j,
and 42 diodes are required in D3j and D4j. The ABB
3.3kV/1.2kA IGBT module 5SNA1200G330100 is employed
in the SMs. Other parameters are exactly same as Table II, and
the junction temperature of 85℃ are assumed for all the
semiconductors in this simulation.
Fig. 15 presents the power loss of each diode in the series
branch. Since the diodes operate in ZCS mode, only the
conduction losses are considered here. It can be found losses of
D2 and D4 are relatively smaller than that of D1 and D3, because
their average current are lower according to Eqs. (11)–(14). The
loss distribution of each SM are shown in Fig. 16. It can be seen
that the switching loss is dominant. Particularly, the loss is
higher when power is transferred from LV to HV sides, since
the string current amplitude is higher under this case.
Based on the losses of Figs. 15 and 16 and by multiplying
their semiconductor numbers, the overall converter loss can be
calculated, as shown in Fig. 17. It can be concluded that the

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1 Conduction loss of each diode

SFD1a W
0 LV To HV HV To LV
300
ZVZCS off 262.7 263.5
iFD1a (5A/div) 250

200
157.9
150
uFD1a(250V/div)
100
71.1
[100ms/div] 50

1 SFD2a 0
D1 D2 D3 D4
0

ZVZCS on Fig. 15. Conduction loss of each diode in the series branches.
iFD2a (5A/div)
Loss distribution of each SM
W LV To HV: 2216.6W HV To LV: 1850.9W
1000 947.5
uFD2a(250V/div)
800 783.3
[100ms/div] 637.3
600 539.2
Z5
400 350.6 385.8
1 256.8
0 ZVZCS SFD1a 167.0
200
1 SFD2a
0 ZVZCS 0
S1 S2 FWD1 FWD2 S1 S2 FWD1 FWD2
iFD1a (5A/div)
iFD2a (5A/div) Conduction loss Switching loss

Fig. 16. Loss distribution of each SM.

uFD2a(250V/div)
uFD1a(250V/div)
[5ms/div] kW Overall Converter Loss
Fig. 14. Experimental results of the closing and opening processes of FD1a and 1400
FD2a: voltages and currents across FD1a and FD2a and corresponding control 1228.3 (0.82%)
1200
logics. 1041.6 (0.69%)
1000
800
overall converter efficiency is about 99.18% when power was 600
transferred from LV to HV side, and 99.31% in the opposite 400
direction. Thererfore, the proposed DC/DC converter can 200
achieve very high conversion efficiency. 0
LV To HV HV To LV
SM overall loss Series branch overall loss
VIII. CONCLUSION
Fig. 17. Overall converter loss of the proposed DC/DC converter.
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this paper for future HVDC interconnections. For avoiding
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Shengbo Wang (S'18) received the B.S. degree in

electrical engineering from the Harbin Institute of
Technology, Harbin, China, in 2018, where she is
currently pursuing the M.S. degrees.
Her research interests include multilevel converters
and modeling.

Dianguo Xu (M’97, SM’12, F’17) received the B.S.

degree in Control Engineering from Harbin
Engineering University, Harbin, China, in 1982, and
the M.S. and Ph.D. degrees in Electrical Engineering
from Harbin Institute of Technology (HIT), Harbin,
China, in 1984 and 1989 respectively.
In 1984, he joined the Department of Electrical
Engineering, HIT as an Assistant Professor. Since
1994, he has been a Professor in the Department of
Electrical Engineering, HIT. He was the Dean of
School of Electrical Engineering and Automation,
HIT, from 2000 to 2010. He is currently the Vice President of HIT. His research
interests include renewable energy generation technology, multi-terminal
HVDC system based on VSC, power quality mitigation, speed sensorless vector
controlled motor drives, high performance PMSM servo system. He has
published over 600 technical papers.
Prof. Xu is an Associate Editor of the IEEE Transactions on Industrial
Electronics, IEEE Transactions on Power Electronics, and the IEEE Journal of
Emerging and Selected Topics in Power Electronics. He also serves as
Chairman of IEEE Harbin Section.

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