1250
4, JULY 2022
Circuit Model with Current Interruption for Hybrid
High Voltage DC Circuit Breakers to Achieve
Precise Current Experiments
Zhonghao Dongye, Student Member, IEEE, Lei Qi , Bing Ji, Xiaoguang Wei,
and Xiang Cui, Senior Member, IEEE
Abstract—The current interruption test based on an LC
resonance circuit for hybrid DC circuit breakers (HVDC CBs)
is widely employed to characterize the current interruption
capability of CBs. In order to ensure a high-fidelity replica
of the fault current in a high voltage application, this paper
first proposes an equivalent model of the test circuit, where
not only parasitic resistances but also the threshold voltages
and on-state resistances of various semiconductor devices are
considered. Moreover, the analytical formula of the test current
is derived by including the working principle of the HVDC CB.
Secondly, the parameter extraction method, which combines finite
element analysis and measurements by an impedance analyzer, is
given in this paper. The extracted result implies that, in current
interruption transients, equivalent resistances of 500 kV CB are
as large as 535 mΩ, which have a significant influence on current
waveforms. Thirdly, the 34 kV/25 kA current interruption test for
the 500 kV CB is conducted. The measured results are proved
to be consistent with the analytical results obtained from the
proposed model, and the relative error is less than 2%.
Index Terms—Current interruption test, high voltage DC
circuit breaker.
I. I NTRODUCTION
OMPARED with a traditional AC grid, flexible direct
C current (DC) transmission technology has a significant
technical advantage for the integration of renewable energy
and long-distance transmission [1]–[4]. However, the low
resistance of the transmission system causes a drastic rise in
the fault current during the flexible DC grid rise fault. It is
recognized the overhead line implementation is susceptible
to temporary faults on the DC side and impedes the higher
Manuscript received May 31, 2020; revised July 26, 2020; accepted August
22, 2020. Date of online publication October 6, 2020; date of current version
June 7, 2022. This work was supported by Science and Technology Project
of State Grid Corporation of China (No. 520201190095).
Z. H. Dongye, L. Qi (Corresponding author, e-mail: qilei@ncepu.edu.cn;
ORCID: https://orcid.org/0000-0002-5175-7607) and X. Cui are with the
State Key Laboratory of Alternate Electrical Power System with Renewable
Energy Sources, North China Electric Power University, Beijing 102206,
China.
B. Ji is with the School of Engineering, University of Leicester, LE1 7RH
Leicester, U.K.
X. G. Wei is with the State Key Laboratory of Advanced Power Transmis-
sion Technology, Global Energy Interconnection Research Institute Co., Ltd.,
Beijing 102209, China.
DOI: 10.17775/CSEEJPES.2020.02270
2096-0042 © 2020 CSEE
CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 8, NO.
requirements for fast and reliable post-fault response to ensure
safe grid operations [5]. High-voltage DC circuit breakers
(HVDC CBs) with fast response have gradually become a
favored protection method for flexible DC grids [6]–[9]. For
example, both the Zhoushan 200 kV five-terminal grid and
Nan’ao 160 kV three-terminal grid have installed HVDC
CBs [10], [11], while the Zhangbei 500 kV grid commits to
equipping 16 HVDC CBs with different topologies [12].
At present, HVDC CBs can be divided into three categories:
the mechanical type, solid-state type, and hybrid type [13]–
[19]. The mechanical solution forms the artificial current zero
point through the commutation circuit so that the DC can
be easily cut-off at zero points. Despite its low cost, the
augmented design complexity, with voltage levels of isolated
power supplies and trigger switches, creates great challenges
when it is applied to the higher voltage level. The solid-state
type leverages controllable power semiconductor devices, such
as IGBT, IEGT, and IGCT, can reliably interrupt fault current
at high speed at the cost of higher conduction loss than other
mechanical solutions. The hybrid solution can be considered
lying in-between both former solutions and combines the low
conduction loss of mechanical switches and the reliable and
high-speed interruption of the power semiconductor solution.
The hybrid style is convenient to integrate and has an out-
standing fast re-closing feature. But it has a high construction
fee due to the high cost of semiconductor devices.
Current interruption tests of HVDC CBs are an indispens-
able part of the CB design. Clearance of the rising fault current
with the utmost speed is crucial to prevent fault propagation
and protect the power grid. The two widely used test meth-
ods are the AC short-circuit generator and the LC resonant
circuit [20]–[25]. Both methods produce a sinusoidal current
to simulate DC short circuit fault current of the required
magnitude for a relatively longer duration. Compared with the
LC resonant circuit, the AC short-circuit generator method
provides a higher source voltage at the energy dissipation
phase, allowing sufficient stress for testing an HVDC CB
regarding its energy handling capability [20]. However, it can
typically be constrained in the testing magnitude (generally
up to tens of kilo amperes). For instance, in [22], a single
2000 MVA AC short-circuit generator can only emulate a
fault current scenario of up to 10 kA, while the 500 kV
hybrid DC circuit breaker (DCCB) and its semiconductors are
DONGYE et al.: CIRCUIT MODEL WITH CURRENT INTERRUPTION FOR HYBRID HIGH VOLTAGE DC CIRCUIT BREAKERS TO ACHIEVE PRECISE CURRENT EXPERIMENTS
capable of interrupting more than 25 kA. Therefore multiple
AC short-circuit generators are required at the expense of
control complexity and the cost premium. In contrast, the
principle and control strategy of the LC resonant circuit is
straightforward [25]. It can be used for large current interrup-
tion tests beyond 25 kA and becomes the focus of this paper.
The purpose of the fault current breaking test is to inves-
tigate whether the HVDC CB under test can turn off fault
currents of several and even tens of kilo amperes within
3∼5 milliseconds, which is identified by the system require-
ments. For instance, the 500 kV CB discussed in this paper
should break at least 25 kA within 3 milliseconds [26]. The
current peak value is one significant parameter to evaluate
the capability of the HVDC CB, which receives significant
attention from field engineers.
However, the previously measured results showed that the
current peak values had a significant deviation from the
expectant values. To deal with this issue, this paper focuses
on the analytical calculation of the hybrid HVDC CB current
and proposes the equivalent circuit model as a tool to deduce
the fault current profile. Moreover, the fault current breaking
tests for both a single submodule in the CB and the 500 kV
hybrid DCCB is conducted to validate the proposed circuit
model and the current analytical expression.
II. C IRCUIT C URRENT A NALYTICAL E XPRESSION O F T HE
I NTERRUPTION T EST FOR H YBRID DCCB S
A. The Interruption Test for Hybrid DCCBs
The schematic of a current interruption test for a 500 kV
hybrid CB is illustrated in Fig. 1 [26], where the CB is
composed of the main branch, a transfer branch, and an
energy absorber branch. The main branch consists of a set
of series ultra-fast mechanical switches and several series-
connected IGBT-bridge submodules. The transfer branch is
made of a large multitude of diode-bridge submodules in series
connection. The absorber branch is comprised of several metal
Main branch
imain A set of mechanical switches
Lm Tm Transfer branch
i
itran
Cm
Absorber branch
MOV
imov
Fig. 1. The schematic of the interruption test for a 500 kV hybrid DCC.
1251
oxide varistors (MOVs). Fig. 2 shows a typical commutating
current waveform measured when the CB is in action, and the
entire fault breaking process could be divided into three stages
as detailed below.
Stage I [t0 ∼ t1 ]: After the capacitor is charged to the
voltage Vch , the main branch and the test circuit thyristor Tm
are turned on at t1 to allow a fault current build up until a peak
amplitude of I1 is reached in this stage, flowing through the
main branch of the CB. After ∆t1 , semiconductor submodules
in the main branch are turned off, while the transfer branch is
turned on, causing current imain in the main branch to gradually
decrease while commutating to the transfer branch.
Stage II [t1 ∼ t2 ]: After the whole fault current i is
approximately transferred to the transfer branch, given a safe
opening distance, the ultra-fast switch in the main branch is
turned off. The fault current continues to rise in the transfer
branch for a period of ∆t2 , after which the transfer branch
semiconductor devices are triggered. Assume the peak current
value at t2 is I2 .
Stage III [t2 ∼ t3 ]: At the end of the fault breaking process,
once the fault current is totally transferred to the absorber
branch, the MOVs extinguish the current in an interval of ∆t3 ,
after which the fault current reaches zero, and the remaining
energy in the system is entirely absorbed by MOVs.
B. Circuit Current Analytical Expression
For the fault breaking process, the test current passes
through different branches in the CB during different stages.
Table I illustrates the symbols used in the following section.
Stage I: The on-state voltage drops on the semiconductor
devices can be expressed as:
vT = VT + rT i (1)
where VT and rT represent the threshold voltage and the on-
state resistance of the device, respectively. The total on-state
resistance and threshold voltage of semiconductor devices in
IGBT-bridge of submodules
Diode-bridge of submodule
MOV MOV
1252 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 8, NO. 4, JULY 2022

TABLE I Vfo_B1
N OMENCLATURE IN THIS PAPER Vfo_m RB1
Lm Rm (RB1) (Vfo_B2)
Symbol Description +− +−
Total parasitic resistance of the inductor bank and the + − + − + v −
Rs m vL_m vR_m R_B
capacitor bank in test circuit
RT m Total on-state resistance of thyristors Hybrid DCCB
Total equivalent resistance of the test circuit except +
Rm i
the CB. (Rs m + RT m ) Cm vC
Rs1 Total parasitic resistance of the CB in Stage I
RT1 Total on-state resistance of the CB in Stage I −
Total equivalent resistance of the CB in Stage I
RB1
(Rs1 + RT1 )
Total parasitic resistance of the test circuit in Stage I
R1
(Rm + RB1 )
Rs2 Total parasitic resistance of the CB in Stage II (a) Stage I and Stage II
RT2 Total on-state resistance of the CB in Stage II Vfo_m
Total equivalent resistance of the CB in Stage II Lm Rm
RB2
(Rs2 + RT2 ) +−
Total parasitic resistance of the test circuit in Stage II + − + −
R2 vL_m vR_m
(Rm + RB2 ) Hybrid DCCB
Vfo m Total threshold voltage of thyristors
Vfo Total threshold voltage of the CB in Stage I +
B1 i
Total threshold voltage of the test circuit Cm vC
Vfo1
(Vfo m +Vfo B1 ) −

14 imain I2
itran
12 (b) Stage III
imov
10
Fig. 3. The equivalent circuit at different stages.
8
i (kA)

I1
6 Vfo m + Vfo B1 . since iC = −Cm × dvc /dt, vR = RB × i,
vL = Lm × di/dt, (2) can be rewritten as:
4

2 d2 vC R1 dvC 1 Vfo1
+ + vC = (3)
Δt1 Δt2 Δt3 d2 t Lm dt Lm Cm Lm Cm
0
t0 t1 t2 t3 The charged voltage of Cm is Vch , and the circuit will not
−2
1 2 3 4 5 6 7 conduct until turning on the CB. So the initial conditions of
t (ms) the circuit are as follows:
Fig. 2. Exemplar measured current waveform. vC (0− ) = Vch , iC (0− ) = 0 (4)

the submodules is defined as RT1 and Vfo B . The stray resis- By solving (3)(4), circuit current i flowing through the CB
tance Rs1 incorporates parasitic components between modules is equal to the capacitor bank current iC and can be given as:
and within the copper busbars. Vch − Vfo1 −α1 t
i= e sin (ωd1 t) (5)
In practice, the capacitor bank or the inductor bank in the ωd1 L1
test circuit is composed of multiple sets of small capacitors
where
or inductors in series and parallel to meet the capacitance  r
and voltage requirements. The total resistance of the inductor  α1 = R1 , ω0 =
 1
bank and the capacitor bank is defined as Rs m . Similarly, the 2Lm Lm Cm (6)
thyristors are connected in series, and the equivalent resistance  ω = pω 2 − α2

d1 0 1
is defined as RT m , and the total threshold voltage is defined
as Vfo m . The stray inductance of the test circuit without the At the end of Stage I, the current reaches the peak value,
CB can be ignored because it is always much smaller than the which can be expressed as:
main inductance Lm .
Vch − Vfo1 −α1 ∆t1
Therefore, In Stage I, the current passes through the main I1 = e sin (ωd1 ∆t1 ) (7)
branch of the CB, and the equivalent circuit is shown in ωd1 Lm
Fig. 3(a) where RB1 is the sum of Rs1 and RT1 , and Rm Stage II: i passes through the transfer branch rather than
is the sum of Rs m and RT m . Let R1 = Rm + RB1 . It can be the main branch, and we define the equivalent resistance of
obtained by Kirchhoff’s voltage law as: the transfer branch as RB2 , and the current can be written as:

−vC + vL + vR + Vfo = 0 (2) i2 = ke−α2 t sin (ωd2 t) (8)

where vL = vL m + vL B , vR = vR m + vR B , and Vfo1 = where

DONGYE et al.: CIRCUIT MODEL WITH CURRENT INTERRUPTION FOR HYBRID HIGH VOLTAGE DC CIRCUIT BREAKERS TO ACHIEVE PRECISE CURRENT EXPERIMENTS 1253

 r
 α = R2 , ω =
 1 III. T HE C URRENT I NTERRUPTION T EST FOR A S INGLE
2 0
2Lm Lm Cm (9) S UBMODULE TO VALIDATE THE C URRENT E QUATION
 ω = pω 2 − α2

d2 0 2 Before conducting the fault current breaking test on a
500 kV hybrid CB, it is necessary to validate the fault current
According to Fig. 3(a), R2 = RB2 + Rm . The commutation breaking capability of submodules in the CB because the sub-
time from the main branch to the transfer branch is mea- modules are the basic units to clear the fault current. Moreover,
sured around 78 µs (Appendix demonstrates more theoretical a downsized platform incorporating a single submodule was
analysis about this transient). Consequently, the commutation built for the fault current breaking test in the lab.
time among different branches can be ignored because they
are much smaller than ∆t1 and ∆t2 , which are several A. Construction of the Test Platform
milliseconds. Furthermore, the initial condition of the second The schematic of this test circuit for a single submodule is
stage is i(∆t1 ) = I1 . Bringing the initial condition into (8), shown in Fig. 5. The test platform is designed to achieve the
we have: fault current of a peak value Imax and a pulse duration T0 that
are not less than 25 kA and 3 ms, respectively.
I1
k= (10)
e−α2 ∆t1 sin (ωd2 ∆t1 ) Diode-bridge submodule

At t2 , the current reaches at the peak value, therefore:

Lm i
−α2 (∆t1 +∆t2 )
I1 e sin [ωd2 (∆t1 + ∆t2 )]
I2 = (11) Tm
sin (ωd2 ∆t1 )

Stage III: The commutation time from the transfer branch to Cm

the absorber branch is around 30 µs, smaller than ∆t3 (around MOV
500 µs). Fig. 3(b) shows the equivalent circuit of this stage.
The current totally passes through the MOV, which can be
regarded as a non-linear resistance [10]. That is to say, imov
can be determined by the V -I curve of the MOV, and this Fig. 5. Schematic of the test circuit for a single submodule.
curve is always provided by the manufacturer, as shown in
Fig. 4. The capacitor bank Cm is charged to a voltage of Vch prior
to the start of the test. Once the IGBT and the thyristor are
800
both turned on, the test circuit starts to build up, shown by
780 the red line in Fig. 5, illustrating the current direction inside
760 the submodule. Fig. 6 shows the current waveform in the
740 LC resonant circuit. When the circuit current reaches Imax ,
v (kV)

720 the IGBT is turned off in a soft-switching fashion, and the

700 submodule capacitor is charged by the emulated fault current
680 during the commutation interval. Once the capacitor voltage
660 reaches the MOV operating voltage, the stored energy in the
640 test circuit will be absorbed by the MOV. The following is the
620 parameter selection procedure of the test platform.
0 5 10 15 20 25
i (kA)
Imax
Fig. 4. V -I characteristic curve of the MOV.

Therefore, the current of the interruption test can be given

as follows:
T0



 0, t ⩽ t0 π LmCm /2
−α1 t
 (Vch − Vfo1 ) e sin(ωd1 t)/(ωd1 Lm ), t0 < t < t1



i = ke −α t
2
sin (ωd2 t) , t1 < t < t2

imov mov ),
(v t2 < t < t 3





 0, t ⩾ t3 Fig. 6. The diagram of the current waveform in the LC resonant circuit.
(12)
Step 1: Regardless of power dissipation within the parasitic
It should be noted that imov (vmov ) in equation (12) is resistances, the energy initially stored in the capacitor prior to
obtained from the curve shown in Fig. 4. the start of the test is not less than the energy stored in the
1254 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 8, NO. 4, JULY 2022

Vch −αt
reactor at the time when the peak current is reached, and the i= e sin (ωd t) (15)
circuit oscillation period is not less than T0 . According to the Lm ωd
current waveform diagram, shown in Fig. 5, it can be seen where
that the capacitance Cm of the capacitor and the inductance s 2
value Lm of the inductor need to satisfy: Rm 1
α= , ωd = − α2 (16)
 2Lm Lm Cm
 1 C V 2 ⩾ 1 L I2
 m ch m max

2 2 Figure 8 shows that the current analytical results for differ-
√ (13)
 π Lm Cm ent inductor values when the capacitor is charged to voltage

 ⩾ T0 Vch of 4.5 kV, taking into account the parasitic resistances
2
which generates the resonator capacitor constraints detailed as: at different inductor values. It can be seen that when Lm =
2
0.2 mH, the current peak value is 37.7 kA, which exceeds the
Lm Imax 4 T02 set value of 25 kA, but the current rise time is 2.9 ms, which
Cm ⩾
2 , Cm ⩾ (14)
Vch π 2 Lm is slightly less than the required 3.0 ms. When Lm = 0.6 mH,
Given the predetermined design requirements, Imax = the current rise time is 5.0 ms, which satisfies the requirement.
25 kA and T0 = 3 ms, while Vch is charged the maximum However, the current peak value is 22.3 kA, which is less than
voltage of the capacitor, Vch = 4.5 kV, the corresponding the set value of 25 kA. It can be implied that the inductor is too
allowable capacitance as a function of reactor inductance is large or too small to meet the design requirements. Therefore,
shown in Fig. 6. According to (14), the selected inductance an inductor with Lm = 0.3 mH is selected in this paper. In
and capacitance values should be above both curves as shown the stage in which the current is absorbed by the MOV, the
in Fig. 7. Since a larger Cm results in a big cost premium, current is also determined by the I-V curve of the MOV, i.e.,
whereas a smaller Cm results in the limited optional range i = imov .
of the inductors, a value of Cm = 20 mF is selected. The
inductor value can be selected between 0.18 mH and 0.64 mH 40
by neglecting the parasitic resistance. 35
(2.9 ms,37.8 kA)
40
LmI 2max 30
Cm= (3.6 ms,31.8 kA)
35 V 2ch
25
4T 20 (4.2 ms,27.2 kA)
30 Cm=
i (kA)

π2Lm 20
(5.0 ms,22.3 kA)
25
Cm (mF)

15
Lm=0.2 mH
20
10 Lm=0.3 mH
15 Lm=0.4 mH
5 Lm=0.6 mH
10
0
5 0 1 2 3 4 5 6
0.18 mH 0.64 mH t (ms)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Lm (mH)
Fig. 8. Analytical current waveforms at different inductances.

Fig. 7. Cm -Lm curves based on (14).

B. The Measured Results
Step 2: The on-state voltage drops on the thyristor, and the The simulation result is verified by an experiment based
submodule is ignored since they are negligibly small compared on the test platform, as shown in Fig. 9. The comparison of
to the breaking voltage. The total parasitic resistances from the fault current between the experimental and simulation results is
inductor and the capacitor bank for selective inductance values illustrated in Fig. 10. A good agreement between both results is
are measured by an impedance analyzer with the results shown evidenced, proving the effectiveness of the proposed analytical
in Table II. method in deriving fault current profiles. The maximum value
TABLE II of the measured current Imax is 26.05 kA, and the pulse
M EASURED R ESISTANCES AT D IFFERENT I NDUCTANCES duration tr is 3.6 ms, matching the design requirements.
Item
Lm /mH 0.2 0.3 0.4 0.6
Rm /mΩ 24.2 28.2 32.2 36.2
IV. C URRENT I NTERRUPTION T EST FOR THE 500 K V
H YBRID DCCB
The current path is unchanged, and the current continues A. Extraction of Equivalent Resistances and Threshold Volt-
rising when the parasitic resistance can be considered as ages
a fixed value. Therefore, the circuit loop current would be Figure 11 presents the equivalent circuit comprised of
expressed as: resistances and threshold voltages for the static conduction of
DONGYE et al.: CIRCUIT MODEL WITH CURRENT INTERRUPTION FOR HYBRID HIGH VOLTAGE DC CIRCUIT BREAKERS TO ACHIEVE PRECISE CURRENT EXPERIMENTS 1255

Rm Vfo RB1(RB2)
Capacitor Banks
Rs_m RT_m Vfo_m Vfo_B RT1(RT2) Rs1(Rs2)

+ − + −
Thyristor
Inductor parasitic parasitic
Oscilloscope thyristors
resistance IGBTs+diodes resistance
Submodule
HVDC CB
MOV
Fig. 11. Demonstration for equivalent resistances and threshold voltages of
the whole circuit.

frequency f , which can be obtained by the following formula:

Fig. 9. Test platform of a single semiconductor submodule. 1
f= √ (17)
2π Lm Cm
30
Measured result Imax=26.05 kA
Based on the measured values of Lm = 4 mH, Cm = 20
25 Analytical result mF from the test circuit, f is 17.8 Hz. The following will
20 introduce the methods for obtaining several resistances and
the threshold voltage mentioned above.
15
i (kA)

1) Rs1 & Rs2

10 The main branch of the 500 kV hybrid CB discussed in
5
this paper consists of 20 IGBT-bridge submodules and a
set of mechanical switches connected in series, while the
tr=3.6 ms
0 transfer branch is composed of 5-layer valves with each layer
−5
consisting of 64 semiconductor submodules. Fig. 12 shows
0 2 4 6 8 a single-layer valve of 64 series-connected submodules in the
t (ms)
transfer branch. Parasitic resistances Rs1 and Rs2 are extracted
Fig. 10. Comparison of measured test result and the analytical result. by finite element analysis (FEA) software. Fig. 12 shows one
layer of the transfer branch in the HVDC CB. According to the
current reference direction shown in Fig. 12, the input surface
a transfer branch in a 500 kV CB. The equivalent resistance is set as the “source” and the output surface as the “sink.”
includes the following parts: 1). Total stray resistance Rs1 The software will calculate the inductance from the source to
(Rs2 ) of the connected busbars inside the CB; 2). Total par- the sink. In this simulation, the IGBT is treated as the copper
asitic resistance Rs m of test circuit capacitors and inductors; block. Moreover, the parasitic resistance of the transfer branch
3). Total on-state resistance RT1 (RT2 ) of the semiconductor is calculated to be 69.27 mΩ using the finite element analysis
devices in the hybrid CB; 4). Thyristor on-state resistance method, and the total busbar parasitic resistance of the transfer
RT m . branch is 346.35 mΩ. It is also possible to obtain the main
Rs1 , Rs2 , and Rs m can be calculated under an equivalent branch connection busbar parasitic resistance of 12.42 mΩ,

Co
nn
ect
ion
Bu
Current reference direction sba
r

Total 64 submodules
Source Two press pack IGBTs

One
submodule Sink

Fig. 12. The single-layer valve of 64 series-connected submodules in the transfer branch.
1256 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 8, NO. 4, JULY 2022

which contains the parasitic resistance of mechanical switches.
So Rs1 = 12.42 mΩ, Rs2 = 346.35 mΩ.
2) Rs m
In order to more accurately obtain the parasitic resistance at
the test frequency f, the capacitor bank and the inductor bank,
including associated connection cables, are characterized by an
impedance analyzer (NF FRA5097). The measurement results
appear in Fig. 13, and it gives the joint parasitic resistance,
which totals 532.84 mΩ at the excitation signal frequency of
f = 17.8 Hz.
Inductance
10
5
mH
circuit failure mode and is preferred in DC grid applications.
In addition, the HVDC CB is primarily for turning off fault
current, and the operation number is very low. So the power
losses are not considered here, and the usual low-cost rectifier
diode is applied in the HVDC CB.
The threshold voltage and on-resistance of thyristors, IG-
BTs, and diodes can be obtained using manufacture datasheets,
which are given in Table IV. Due to the electrical insulation
requirements, ten thyristors in the main test circuit are required
to connect in series, and the effective threshold voltage of the
entire thyristor string, Vfo m , is 9.20 V, and the effective on-
state resistance, RT m , is 2.50 mΩ. Therefore, according to
Fig. 10, Rm = Rs m + RT m =535.34 mΩ.
TABLE IV

0 O N - STATE M ODEL PARAMETERS OF S EVERAL D EVICES

4 mH Devices VT /V rT /mΩ
−5
Thyristor 0.92 0.25
−10 IGBT 0.60 0.642
101 102 103 104 105 Diode 0.90 0.136
f (Hz)
Rarasitic Resistance
500 The single submodule in the main branch consists of two
400 bidirectional switches in parallel branches, as shown in Fig. 14.
300 Both common collector IGBTs with antiparallel diodes and the
mΩ

200 common-emitter IGBTs are configured, with their middle node

314.48 mΩ
100 connected with a capacitor. By neglecting the difference due to
0 device tolerance, the on-state single submodule has a threshold
101 102 103 104 105
f (Hz) voltage of 1.5 V and an on-state resistance of 0.39 mΩ. There
(a) The inductor bank and connecting cable are 20 series IGBT bridge submodules in the main branch.
Capacitance Therefore, the on-state voltage drop Vfo B is 30 V, and the on-
30
state resistance RT1 is 7.80 mΩ. So the equivalent resistance
20 of the main branch of the HVDC CB is the sum of Rs1 and
RT1 , i.e., RB1 = Rs1 + RT1 = 20.22 mΩ.
mF

10
20 mF
0
IGBT-bridge Diode-bridge
−10
101 102 103 104 105
f (Hz)
Parasitic Resistance
500
400
300
mΩ

200
100 218.25 mΩ
0 Fig. 14. On-state current directions in two kind of submodules.
101 102 103 104 105
f (Hz)
(b) The capacitor bank and connecting cable Similarly, the transfer branch adopts the submodule configu-
ration with an IGBT embedded in a diode-bridge, as shown in
Fig. 13. Measured equivalent impedance characteristics. Fig. 14. The on-state resistance of a single submodule consists
of the two parallel IGBTs and two series diodes, so the value
3) Vfo , RT1 , RT2 & RT m
is 0.59 mΩ. The total on-state resistance RT2 is 188.80 mΩ at
Table III shows the ratings of semiconductor devices used
a total number of 320 submodules (5 layers and every layer
in this paper. Although the normal current of the thyristor
has 64 submodules). RB2 = Rs2 + RT2 = 535.15 mΩ.
is 3 kA, the surge current of the thyristor is up to 32 kA,
The above results are shown in Table V. So, the total
which is larger than the required maximum current of the test
threshold voltage Vfo is the sum of Vfo m and Vfo B , i.e., Vfo =
circuit. IGBTs are a press pack type, which has a reliable short
TABLE V
TABLE III O N - STATE PARAMETERS OF THE T EST C IRCUIT
S EMICONDUCTOR D EVICES U SED IN THIS PAPER
Voltage Threshold (V) Parasitic Resistance (mΩ)
Devices Thyristor IGBT Diode Vfo m Vfo B Rm RB1 RB2
Ratings 4.4 kV/3 kA 4.5 kV/3 kA 5.0 kV/3 kA 9.20 30.00 535.34 20.22 535.15
DONGYE et al.: CIRCUIT MODEL WITH CURRENT INTERRUPTION FOR HYBRID HIGH VOLTAGE DC CIRCUIT BREAKERS TO ACHIEVE PRECISE CURRENT EXPERIMENTS 1257

39.2 V. R1 = Rm + RB1 = 555.56 mΩ, R2 = Rm + RB2 = Imax=25.39 kA

25 Simulated result
1070.49 mΩ. R2 is much larger than R1 because of the larger
Measured result
number of transfer branch semiconductor submodules and the
longer connection busbars. In addition, the charged voltage Vch 20
is normally several kilovolts, is greatly larger than Vf0 , which
is several volts. So the Vfo is negligible compared to Vch , and 15

i (kA)
the parasitic resistances heavily influence the peak value of
the test current. I1=11.13 kA
10
This paper conducted a current interruption test to verify the
above analysis. Fig. 15 shows the photo of the test setup [26].
In the test circuit, the inductor bank is 4.0 mH, and the 5
capacitor bank is 20 mF. In order to reduce the cost of the
test, the transfer branch only applies a single-layer valve. So, 0
one-fifth of the transfer branch is used for the test. Therefore, Stage I Stage II Stage III
1 2 3 4 5 6 7 8
R2 = Rm + RB2 /5 = 642.37 mΩ. Fig. 16(a) shows the t (ms)
comparison of the measured results with the simulation results (a) Simulation are based on Table V
when the charged voltage is Vch = 34 kV. The analytical result
agrees well with the measured result. In addition, the impact
of parameter dispersion of the semiconductor devices on the
model result should be studied. If the semiconductor devices
equivalent resistances RT1 and RT2 are changed by ± 5%, the
comparison of the simulated waveforms with the measured one
can be shown as Fig. 16(b). These two simulated waveforms
are consistent with the measured one. The maximum measured
current is 25.30 kA, the simulated maximum value is 25.18 kA
if the parasitic resistances are increased by 5%, and this value
is 25.67 kA if these resistances are decreased by 5%.

500 kV Hybrid
DCCB

(b) RT1 and RT2 are changed by ±5%

Inductor
Fig. 16. Comparison of measured results with analytical results at Vch =
34 kV.

Figure 17 compares the analytical Imax -Vch relationship

Fig. 15. The photo of the test setup [26].
In the case where the test circuit and the HVDC CB are
settled, the magnitude of the circuit current depends on the
capacitor charged voltage. Therefore, it’s necessary to figure
out the charged voltage Vch to achieve the target maximum
current Imax . According to (7) and (11), the relationship
between the charging voltage Vch and the peak current Imax
at the turn-off instant is obtained as follows:
Imax ωd1 Lm eα1 ∆t1 +α2 ∆t2 sin (ωd2 ∆t1 )
Vch = + Vfo
sin (ωd1 ∆t1 ) sin [ωd2 (∆t1 + ∆t2 )]
Ideally, if the parasitic parameters are not considered, the
relationship of the charged voltage Vch and the current can be
expressed as:
Imax ω0 Lm
Vch =
sin[ω0 (∆t1 + ∆t2 )]
obtained by (18) and (19) with the current interruption test
result. It can be seen from Fig. 17(a) that the analytical results
coincide with the measured results based on the proposed
model, and the maximum relative error is less than 2%. In
addition, if the voltage threshold is neglected, the relative error
will arise slightly, but still be less than 3%. In contrast, the
measured results and analytical results based on (19) have
apparent differences, and the relative error is over 31%. This
comparison implies that the proposed model can improve the
precision of the current interruption experiments for hybrid
HV DCCBs.
V. C ONCLUSION
(18)
This paper proposes an equivalent circuit model for the
current interruption test of the HVDC CB, ignoring the com-
mutation time between different branches in the HVDC CB,
and the current trajectories are investigated using the analytical
method. This model includes 1) Total parasitic resistance of
(19) the connected busbars inside the HVDC CB; 2) Total parasitic
resistance of the inductor and capacitor, which are applied
1258 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 8, NO. 4, JULY 2022

25 1.6 Finally, the 34 kV/25 kA current interruption test shows

Measured results
Analytical results 1.4
that the analytical results and the measured results are in
20 good consistency. The differences between analytical results
1.2 and measured results are over 31% if the parasitic resistances

Relative Error (%)

1 are ignored. In contrast, this difference decreases to 2% based
15
Imax (kA)

on the proposed model in this paper.

0.8
10 0.6 A PPENDIX
0.4 The equivalent circuit of the commutation process between
5 the main branch and transfer branch can be depicted as
0.2 Fig. A1. Therefore,
0 0 dim
0 5 10 15 20 25 30 35 40 im Rm + vc m + Lm + Vth m
Vch (kV) dt
(a) Considering parasitic resistances and voltage threshold ditr
= itr Rtr + Ltr + Vth tr (A1)
25 3 dt
Measured results
Analytical results
2.5 Is1 Lm Rm Cm
20
+−
2 Relative Error (%) im + −
Vth_m vCm
15
Imax (kA)

1.5
itr Vth_tr
10 Ltr Rtr
1 +−

5
0.5 Fig. A1. The equivalent circuit of the commutation process.

0 0 Assuming that Is1 is kept constant in this process, (A1) can

0 5 10
20 15
25 30 35 40 be expressed as follows:
Vch (kV)
(b) Neglecting voltage threshold while considering parasitic resistances dvc2 m R1 dvc m vc m Vs1
+ + = (A2)
35 37 dt2 L1 dt L1 Cm L1 Cm
Measured results
30 Analytical results where L1 = Lm + LTr , VTh = VTh tr -VTh m , R1 = Rm + RTr ,
36
Vs1 = Is1 RTr + VTh . When the voltage of Cm in the main
25 branch is over VTh , the commutation process starts, and the
Relative Error (%)

35
initial conditions can be given by:
Imax (kA)

20 
−
34  vc m (0 ) = Vth

15
(A3)
33  Cm dvc m (0− ) = Is1

10 dt
5 32 Assuming that

31
∆ = R12 Cm
2
− 4L1 Cm < 0 (A4)
0
0 5 10 15 20 25 30 35 40
Vch (kV) Substituting (A3) into (A2),
(c) Neglecting parasitic resistances and voltage threshold (
vc m = e−αt (−A1 cos ωd t + A2 sin ωd t) + Vs1
(A5)
Fig. 17. Comparison of measured Imax with analytical ones. im = KCm e−αt sin (ωd t + β)
where
to generate the fault current; 3) Total on-state resistance of
 p
 α = R1 /2L1 , ωd = (1/Lm Cm )2 − α2

the semiconductor devices (IGBTs, diodes, and thyristors); 4) 
Is1 /Cm + A1 α


Threshold voltages of the semiconductor devices. In addition,

 A1 = Is1 Rtr , A2 =


a downsized 4 kV/25 kA prototype of the test circuit is ωd
A1 α + A2 ωd (A6)
implemented to validate the proposed model.  β = arctan
A2 α − A1 ωd


Furthermore, parameters of the test circuit for a 500 kV CB



 q
2
are extracted by combining FEA analysis and measurements K = (A1 + A22 ) (1/Lm Cm )
2


from the impedance analyzer. The equivalent resistances of
When the main branch current im is zero, the process ends.
the 500 kV CB is up to 535 mΩ, having a more significant
Therefore,
impact on test current waveforms than the threshold voltages
of semiconductor devices sin (ωd ∆ts1 + β) = 0 (A7)
DONGYE et al.: CIRCUIT MODEL WITH CURRENT INTERRUPTION FOR HYBRID HIGH VOLTAGE DC CIRCUIT BREAKERS TO ACHIEVE PRECISE CURRENT EXPERIMENTS
Moreover, the commutation time can be expressed by:
π−β
∆ts1 = (A8)
ωd
Table A1 shows the parameters of the HVDC CB discussed
in our paper. It should be noted that only one layer of the
5-layer transfer branch is considered here. Based on Table A1
nd the above equations, ∆ts1 can be calculated as 84 µs.
The measured result is 78 µs. Compared to the fault current
duration time, this commutation process can be ignored.
TABLE A1
PARAMETERS FOR C ALCULATION
Lm Ltr Rm Rtr Cm Vth m Vth tr
10 µH 21 µH 22 mΩ 107 mΩ 82.5 µF 30 V 154 V
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Zhonghao Dongye was born in Linyi, Shandong
Province, China, in 1994. He received the B.S.
degree in Electrical Engineering from North China
Electric Power University, Beijing, China, in 2015.
He is a Ph.D. candidate for Electrical Engineering
at North China Electric Power University, Beijing,
China. His research interests include the application
of wide band-gap devices, advanced power trans-
mission technology. He is working on DC circuit
breakers in medium and high voltage DC grids.
Lei Qi was born in Nanyang, Henan Province,
China, in 1978. He received the B.S., M.S., and
Ph.D. degrees in Electrical Engineering from North
China Electric Power University, Baoding, China, in
2000, 2003, and 2006, respectively. He is currently
a Professor of electrical engineering at North China
Electric Power University. His research interests in-
clude electromagnetic fields theory and application,
electromagnetic compatibility in power systems, and
advanced power transmission technology.
1260
Bing Ji (M’13–SM’18) received Ph.D. degrees in
Power Electronics from Newcastle University, New-
castle upon Tyne, U.K., in 2012. He has undertaken
different research roles in industry and academia
since 2012. He joined the University of Leicester,
Leicester, U.K., in 2015, as a Lecturer of Electrical
Engineering. His current research interests include
reliability and resiliency of power semiconductors,
batteries and converters, intelligent gate drivers,
device and package design optimization, thermal
management, and high-power-density converters in
electric vehicle and aerospace applications.
Xiaoguang Wei received the bachelor of engineer-
ing and master of engineering degrees from North
China Electric Power University in 1999 and 2003,
respectively. He also received a Ph.D. degree in
Engineering from China Electric Power Research In-
stitute in 2007. He is currently working at state grid
smart research institute, DC transmission technology
research department. His research interests include
HVDC transmission, DC power grid and its key
equipment research and development, the connection
of new energy to power grid.
CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 8, NO. 4, JULY 2022
Xiang Cui (M’97–SM’98) was born in Baoding,
Hebei Province, China, in 1960. He received the
B.Sc. and M.Sc. degrees in Electrical Engineering
from North China Electric Power University, Baod-
ing, China, in 1982 and Beijing, China, in 1984
respectively, and the Ph.D. degree in Accelerator
Physics from China Institute of Atomic Energy,
Beijing, China, in 1988. He is currently a Professor
and the Vice Director of State Key Laboratory of
Alternate Electrical Power System with Renewable
Energy Sources, North China Electric Power Uni-
versity, Beijing, China. Prof. Cui’s research interests include computational
electromagnetics, electromagnetic environment and electromagnetic compat-
ibility in power systems, insulation and magnetic problems in high-voltage
apparatus.
Prof. Cui is a Standing Council Member of the China Electrotechnical
Society, a Fellow of IET, a Senior Member of IEEE. He is also an Associate
Editor of IEEE Transactions on Electromagnetic Compatibility.