Electric Power Systems Research 221 (2023) 109403

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Electric Power Systems Research

journal homepage: www.elsevier.com/locate/epsr

Novel hybrid fault current limiter with hybrid resonant breaker in

multi-terminal HVDC transmission system
Gul Ahmad Ludin a, b, *, Hashmatullah Zeerak b, Qudratullah Tayyab a, Ahmad Shah Irshad a,
Hidehito Matayoshi c, Natarajan Prabaharan d, Abdullelah Rasooli b, Tomonobu Senjyu a
a
Electrical and Electronics Engineering Department, University of the Ryukyus, 1 Senbaru, Nishihara-cho, Nakagami, Okinawa 903-0213, Japan
b
Electrical Power Engineering Department, Kabul Polytechnic University, 5th District, Kabul, 1001, Afghanistan
c
Osaka Institute of Technology, Osaka 530-8568, Japan
d
Department of Electrical and Electronics Engineering, School of Electrical and Electronics Engineering, SASTRA Deemed University, Thanjavur, India

A R T I C L E I N F O A B S T R A C T

Keywords: In practical high voltage direct current (HVDC) transmission systems, the current is considerably high when a
HVDC system fault occurs in the dc line. This current must be limited to make its blocking techno-economically feasible by dc
Fault circuit breakers. This paper proposes a new hybrid fault current limiter (HFCL) that is placed and examined
Hybrid FCL
together with a hybrid resonance type dc circuit breaker in a four-terminal modular multi-level converter
Hybrid resonance DC breaker
(MMC)-based HVDC transmission system. HFCL consists of an inline fast mechanical switch and parallel fault
current limiting inductor (FCLI) with a series thyristor-controlled resistor. Since the FCLI is placed offline and on
the other hand, in regular operation, the thyristors are in the off mode which prohibits the losses of conventional
inline FCLI in the literature. The operation principle and design theory are presented. In order to clarify the
effectiveness of the proposed HFCL, a simulation is carried out in MATLAB Simulink software, and the results are
provided and discussed. It is verified that by applying the proposed fault current limiter, the peak of fault current
is extremely limited, and the dc breaker obtains the efficient current blocking.

1. Introduction them, hybrid DCCBs, due to their prominent characteristics such as

Nowadays, HVDC transmission technology is playing a significant
role in electric power integration and transmission due to its techno-
economic superiority over high-voltage alternating current (HVAC)
systems for enormous power over lengthy distances [1–3]. Due to the
grid connection of large-capacity renewable energies, various distrib­
uted generation systems and HVDC transmission lines, the global
research direction is to develop Multi Terminal DC (MTDC) grids.
Because MTDC grid improves stability and reliability of the system and
reduces asset cost [4]. On the other hand, owing to the lack of
zero-crossing in HVDC systems, the fault is a significant obstacle to
implementing this technology. The fault is caused by device failure,
worst weather, accidents, and etc. These failures could cause extended
and expensive outages and damage the line or may destroy the leading
and costly equipment of the system [5]. Because the fault current
sometimes exceeds ten times the rated current [6]. Different types of DC
circuit breakers (DCCBs), i.e., solid-state, mechanical and hybrid brea­
kers, are used to prevent the abovementioned problems [7]. Among
comparatively lower steady-state losses, cost-effectiveness, well-­
capability of handling the fault current and appropriate response time,
have attracted much attention from researchers and industries world­
wide [8]. Although the DC breakers provide valuable characters to
cut-off and clear the fault current, these breakers suffer from capacity
issues due to the high fault current. Also, as the main shortcomings, the
costs, size, and weight of DCCBs increase accordingly [9]. Therefore, by
reducing the breaking current of breakers, the capital cost, size, and
weight will be decreased. To do this and improve the performance, FCL
is used with DCCB, which can limit the high fault current and protect the
HVDC lines against its various implications [10]. Since FCL has no
intrinsic ability to absolutely isolate the fault current, it is used to sup­
press the fault current. Besides, in recent FCLs, its current limiting ele­
ments remain inactive during normal operating conditions, making FCL
suitable for high power ratings and higher fault-current handling re­
quirements [11]. An ideal FCL should meet the following general re­
quirements: minimum impedance during typical operating and
maximum impedance during fault operating conditions; rapid fault peak

* Corresponding author.
E-mail address: gulahmadludin@gmail.com (G.A. Ludin).

https://doi.org/10.1016/j.epsr.2023.109403
Received 19 October 2022; Received in revised form 21 February 2023; Accepted 8 April 2023
Available online 17 April 2023
0378-7796/© 2023 Elsevier B.V. All rights reserved.
G.A. Ludin et al. Electric Power Systems Research 221 (2023) 109403

Fig. 1. General configuration of the MMC-HVDC system.

current limitation within 5-10 msec; auto triggering and fast recovery
Table 1
capability; tolerate the limited fault current of about 50-100 msec or
Parameters of the MMC-HVDC system [8].
until the breaker recover the fault; fault current limiting capability with
high reliability and no risk to operating personnel; having compact Parameter Value
structure, lightweight and economic and applicable at high power and Total distance 240 km
DC voltages. Generally, FCLs are categorized into three types, i.e., DC Voltage 150 kV
superconducting (resistive, inductive, and resistive-inductive), non-­ Resistance 1.39 mΩ/km
Inductance 0.159 mH/km
superconducting (solid-state) and hybrid technology [11,12]. Re­ Rated power P1 = P2 = 30 MW
searchers have conducted various studies on hybrid FCL to improve the P3 = P4 = 15 MW
fault current-suppressing ability. The hybrid FCL which combines the
advantage of two other topologies seems to be a promising option in
HVDC transmission systems [13,14]. In [15], a novel hybrid super­
conducting fault current limiter with a biased magnetic field with its
fault current limiting characteristic is investigated. The authors verified
that the fault current is continuously limited about 89.66%. In [6], a
22.9 kV hybrid superconducting FCL of the first half cycle non-limiting
type has been developed. The authors concluded that compared with
those for purely resistive superconducting fault current limiters, the
total length of needed superconductors for FCL is intensively reduced,
and it has more flexibility with conventional relays. A novel hybrid FCL
based on a new theory, i.e., the push-pull technic, is proposed in [11]. By
proposing this FCL, the current limiting ability is improved by reducing
the rate of rising and peak of fault current. Ref. [16] investigates a
simple hybrid FCL based on an inline inductor with a parallel current
limiting circuit. It is stated that the FCL can be easily applied, and the
usefulness of the FCL without power interruption of healthy parts is
verified by simulation results. A hybrid fault current limiter using liquid
metal for large capacity power systems is developed in [17]. The authors
stated that this FCL achieves low operation loss and high current
Fig. 2. Proposed HFCL topology.
limiting resistance through a fast mechanical switch, a magnetic in­
duction module, and several liquid metal units. Also, it is concluded that
the studied prototype provides the basis for further commercial product the absence of solid-state switches, the on-state loss that existed with
development. Ref. [18] proposed a novel hybrid saturated core type FCL conventional HFCLs in the literature is zero during regular operation
based on DC coils and permanent magnets. Simulation results are pre­ [20]. Simulation is carried out through Simulink software, and the re­
sented, and it is stated that the proposed FCL is effective in fault current sults are presented and discussed to show the usefulness of the proposed
clipping, and its performance depends on the limiting reactor value. HFCL in the system. The rest of the paper is arranged as follows: Section
Similarly, in [19], a novel hybrid superconducting FCL with a controlled II describes the general layout of the HVDC transmission system. The
solid-state device is proposed. Simulation results show that even using proposed hybrid FCL and its operating principle are presented in Section
the thyristors, with the proposed hybrid FCL the fault current is limited III, and its design consideration is explained in Section IV. The simula­
to less than a quarter of half-cycle. tion results are presented and explained in Section V. Section VI com­
This paper proposes a new hybrid FCL to limit the fault current. The pares the proposed HFCL to the recent concepts existed in the literature.
proposed FCL is studied with a hybrid resonance DCCB in a four- Finally, Section VII presents the conclusion of the paper.
terminal MMC-based HVDC transmission system. The layout of HFCL
is similar to a hybrid DCCB that utilizes an on-state mechanical switch 2. System Configuration
with a parallel limiting branch based on solid switches. The limiting
branch consists of FCLI with a series thyristor-controlled resistor. In the In order to test the performance of the proposed HFCL together with
structure of the proposed FCL, the FCLI reduces the rising rate, and DCCB, a half-bridge submodule type MMC-based four-terminal HVDC
resistor reduces the peak amplitude of the fault current. FCLI is placed transmission system is used in this paper. The power flow is controlled
offline; on the other hand, using the mechanical switch in the line and by MMCs at all four terminals (regions). The overall configuration of the

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G.A. Ludin et al. Electric Power Systems Research 221 (2023) 109403

Fig. 3. Proposed HFCL connected with resonance DCCB in MMC-HVDC system.

Fig. 4. Control block diagram of proposed HFCL.

system is illustrated in Fig. 1, and its parameters are shown in Table 1.
3. System configuration
3.1. Topology
The primary circuit diagram of the proposed HFCL, consisting of two
main branches, is shown in Fig. 2. The branches with their functions are
explained below.
• The normal current flow branch is similar to the hybrid DC circuit
breaker and contains a fast mechanical switch (MS) with a 1.5 msec
interruption speed.
• The maximum fault current flow branch, also called the semi-
conductor branch, is composed of peak fault current limiting
inductance (L) and energy dissipation resistor (R) with its parallel
capacitance (C). Due to the characteristics such as being reliable,
robust, cost-effective, simple structure, high rating and natural
commutation capability, the silicon-controlled rectifiers (SCRs) are
used to control the energy dissipation on the resistor [21]. The C
facilitates the forced commutation of SCRs (T1 and T2) by charging

Fig. 5. Fault current handling stages.

3
G.A. Ludin et al.
Fig. 6. Proposed HFCL-HDCCB operating principles.
during the fault current dissipation (absorption by R). During normal
operation, the capacitor is discharged.
3.2. Operating principle
In order to effectively limit, interrupt and clear the fault current
without the whole system disconnection, a resonance type hybrid DC
circuit breaker with the proposed HFCL is used, as shown in Fig. 3. The
operation principle and design consideration of the resonance HDCCB is
detailed in [8]. The control block diagram and simplified simulation
model of the proposed HFCL-HDCCB are respectively depicted in Figs. 4
and 5 and its operation stages are explained below.
3.2.1. Normal operation
The control system regularly checks the synchronous voltage and
current of the DC line, as depicted in Fig. 4. If these signals are within
their rated values, the FCL and CB continue their normal operation, i.e.,
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Electric Power Systems Research 221 (2023) 109403
the current flows through MSFCL and MSCB. In this case, the fault current
limiting branch is inactive i.e., the L, R, T1, T2 and C are in the off mode.
The DC current direction during the normal operation is indicated in
Fig. 6a, and interval (0 ≤ t ≤ t1 ) in Fig. 5.
3.2.2. FCL operation stage
When a line-to-line fault occurs, the current rises and after a time
delay of tfcd and reaching this transient current to a threshold value, the
MSFCL gets a turn-off signal. The MSFCL withstands this high fault current
by its impedance. In this case, the current commutates to the limiting
branch, which increases the inductor’s current and limits the fault cur­
rent’s rise. When the current of inductor reaches a predefined threshold,
the T1 and T2 turn on by increasing the voltage across them, which
conducts the current to the R to reduce its amplitude. SCR (T1 and T2) is
one of the most reliable and robust power electronic switches, available
in high rating, which has natural commutation capability. The current
flow direction of fault occurrence and fault current limiting mode are
G.A. Ludin et al. Electric Power Systems Research 221 (2023) 109403

Fig. 7. Equivalent circuit of HFCL with various stages.

shown in Fig. 6b and interval (t1 ≤ t ≤ t2) in Fig. 5.

3- The peak of fault current rise rate should be lower than the peak of
3.2.3. Fault current interruption stage (CB operation) CB changing current.
After control and limiting the peak of transient current to a secured
predefined threshold (interruptible by DCCB), the capacitor C generates tfcd + tfcl + tfcc < tcd (3)
reverse current, which makes the current of R to be zero and causes the
T1 and T2 to be turned off, which is so called forced commutation. In
this case, the controller turns on the MSFCL, and turns off the MSCB.
Meanwhile, the current commutates to a resonance current generation When the fault occurs, the current commutates from MSFCL to the
branch through triggering S1 and S2 and achieves the zero-crossing limiting branch. In this case, the equivalent circuit for the fault current is
point by resonance phenomena and the current interrupts. The current plotted in Fig. 7.
flow direction in this stage is shown in Fig. 6c and interval (t2 ≤ t ≤ t3) The fault current can be estimated by:
in Fig. 5. VDC VDC
Id (t) = IDC (0) + (t) + (4)
L R
3.2.4. Fault current clearing and reconnection stage
Where, Id (t) is the fault current, IDC (0) is the rated DC current, VDC is
After the current becomes zero by injection the reverse resonance
the rated voltage, L is the current limiting inductance and R is the cur­
current generated by the LrCr circuit, S1 and S2 turn off and thyristors
rent discharging resistor.
T3 and T4 trigger. Finally, the capacitor discharges, and the stored en­
The rate of current rise on the inductor can be expressed as:
ergy of the inductor demagnetizes (dissipates) by Rd and fault imped­
ance. When the commutation completes, the reconnection command Δi VDC
= (5)
sends to MSCB and the current commutates to MSCB to recover (recon­ Δt L
nect) the system. The current flow diagram in this stage is shown in Therefore, for the desired current rise rate, the inductor value can be
Fig. 6d and interval (t3 ≤ t ≤ t4) in Fig. 5. calculated by:

4. Design consideration L=
VDC
(6)
Δi
Δt
4.1. Normal operation
or
In this case, the current is normal and has no inductive effect or VDC
transients because there is no inductance excluding line inductance in L > ( diFCL ) (7)
the path. In addition, the voltage drop and the MS’s power loss are
dt peak

negligible and can be assumed to be zero. By supposing the resistance of Based on the fault current obtained in case 1 (without FCL), the
MS equal to zero, VMS = VDC . IFCL max = 10 kA is assumed. Also, the time the fault current reaches peak
( )
value is assumed to be 2 msec for the design. Therefore, didtFCL peak is set as
4.2. Dynamic operation 10 kA
2 msec
= 5 msec
kA
[23,24]. Putting this value in Eq. (7), the value of L is
calculated, which is set to be 100 mH for the simulation.
The FCL inductance should be selected small enough to decrease the
By applying the KVL in Loop I of Fig. 7 and assuming that the SCRs
cost and assure the smooth commutation process and large enough to
resistor is negligible during conduction, the voltage of the DC line
guarantee the minimization of fault current rise rate. Therefore, the
becomes:
design of the FCL parameters (L, R and C) should fulfil the following
constraints [7,16,22,23]: di
VDC = VL + VR = L + ifault × R (8)
dt
1- The peak fault current of the DC line should be lower than the After performing the simple mathematical calculation on Eq. (8), the
maximum interruptible current of the DC circuit breaker. following equation is obtained.
(iline )peak < (iCB )peak (1) Vdc ( )
ifault = 1 − e− R/L(t)
(9)
R

2- The peak of fault current rise rate should be lower than the peak of By assuming the ifault = ifault max and L=100 mH the value of R is
CB changing current. obtained from Eq. (9).
( ) ( ) Similarly, by applying the KVL in loop II of Fig. 7, the voltage of the
diline
<
diCB
(2) DC line becomes:
dt peak dt peak

5
G.A. Ludin et al. Electric Power Systems Research 221 (2023) 109403

Table 2 Where, = VDC2τ

⋅C
, and τ = RC.
Parameters of the proposed HFCL. The value C is calculated from (10).
Parameter Value Eq. (10) indicates that if the DC voltage becomes constant (dV
dt = 0) by
Inductance (L) 100 mH discharging the fault current through R, the charge current will be zero.
Resistance (R) 100 Ω Considering the FCL requirements and constraint (3), after limiting the
6
Capacitor (C) 0.01x10− μF peak of fault current and before complete discharging, it should be
forwarded to the DCCB for clearing. Therefore, after closing the MCB of
di 1
∫ FCL, this loop is still indicated with a red arrow in Fig. 6(c).
VDC = VL + VC = L + iC dt (10)
dt C
5. Results
In this equation, L dt
di
is derived from Eq. (8) and iC = C dV
dt
is the charge
current of the capacitor. This value is calculated as follow [17]: In order to verify the effectiveness of the proposed HFCL, simulation
is performed in MATLAB Simulink software and the results are presented
(11)
− t
iC = Ae τ
accordingly. The simulated 4-terminal MMC-HVDC system is depicted in

Fig. 8. Fault current with DCCB and without HFCL.

Fig. 9. Fault current with HFCL and without DCCB.

Fig. 10. Current waveform of the MSFCL.

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G.A. Ludin et al. Electric Power Systems Research 221 (2023) 109403

Fig. 11. MSFCL voltage waveform.

Fig. 12. Gating signal of the MSFCL.

Fig. 13. Current waveform of the limiting branch (inductor).

Fig. 1 and the parameters of FCL are presented in Table 2.
The observed events are as follows: From 0 to 3 sec, the system works
under regular conditions and the line carries the rated current, i.e., I =
30 MW
150 kV = 200 A. At 3 sec, a line-to-line (L-L) fault occurs in the trans­
mission line, and the HFCL limits the fault current after 1.5 msec.
Simulation has been performed for three cases. At first, only the
breaker is considered in order to simplify the visualization of the pro­
posed HFCL effect in terms of fault current limitation in the next step.
Secondly, a simple simulation is performed considering only the pro­
posed HFCL in the system. Later, the proposed HFCL-DCCB is
implemented, and the simulation results are shown accordingly.
The DC link current with only CB and without applying the FCL is
shown in Fig. 8. As can be observed, when the fault occurs, the fault
current exceeds 9 kA in this case. The simulation results of the proposed
HFCL without applying the CB are shown in Figs. 9-14. The ability of the
limiter in terms of fault current limiting with various values of L is
depicted in Fig. 9. The current waveform of MSFCL is plotted in Fig. 10. In
the period of 3-3.0015 sec, the current of MSFCL is zero. After this time,
the current increased again due to the absence of the breaker in this case.
The voltage of the MSFCL is depicted in Fig. 11 which proves that the

7
G.A. Ludin et al.
Fig. 14. Current waveform of the SCRs (T1 and T2).
Fig. 15. Fault current with HFCL-HDCCB.
Fig. 16. The DC line voltages at 4-terminals.
fault current is limited without interruption of the whole HVDC system,
and the voltage of the DC line is kept constant, which is almost 150 kV.
In addition, the transient voltage is completely depressed during the
fault. The gating signal of the MSFCL is shown in Fig. 12. The current of
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Electric Power Systems Research 221 (2023) 109403
the limiting branch is shown in Fig. 13 and the current of T1 and T2 are
plotted in Fig. 14. Since these thyristors are mainly used to quickly
discharge the fault current by R, their value is equal to the current of the
inductor. Also, as the current direction is from the inductor side to the
resistor side, the current of T1 is zero.
Simulation results for case 3, i.e., applying the proposed HFCL-
HDCCB are shown in Figs. 15-17. The DC link current with various
values of the L is shown in Fig. 15. As can be observed, with L =
100 mH the current is sensed and limited to 1 kA after reaching the
predefined value (in this study 2 kA). Also, with increasing the value of
the current limiting inductor, the fault current is further limited. This
indicates the better coordination and performance using the proposed
HFCL with HDCCB. The DC voltages of the HVDC lines are illustrated in
Fig. 16, and the active powers of the four terminals are plotted in Fig. 17.
These Figures clarify the fault current clearing process without discon­
nection of the whole HVDC system.
6. Comparison of the proposed HFCL to others
In this section, the comparison has been made to demonstrate the
G.A. Ludin et al. Electric Power Systems Research 221 (2023) 109403

Fig. 17. The active power at 4-terminals.

interruption in the HVDC system. Therefore, the series connection of

Table 3
these devices increases the switching loss, complexity of the control
Comparison of the proposed HFCL-DCCB to others.
system, and associated costs. In [26], a new hybrid DC circuit breaker
FCL Fault current Fault Fault current Losses integrating the FCL circuit is proposed to limit and interrupt the fault
Topology limitation current limitation
current. The proposed FCL-HCB is compared with a traditional structure
rate (kA) reduction time (msec)
(%) based on required semiconductors (IGBTs, thyristors and diodes) and
investment costs. Although, using the proposed FCL-HCB, the peak value
Ref [4] From 21 to 5 23 14 High due to IGBTs
in both normal and
of the fault current is reduced from 8.7 to 5.6kA (by 35.63%) in
limiting path 4.006msec, the inserting of a large number of IGBTs and thyristors in the
Ref [12] From 50 to 32 3 High due to inline limiting stage, increase the complexity and cost of the topology. In [25],
16 L a hybrid breaker with self-adaptive fault current limiting capability is
Ref [17] 4.3 to 0.64 14.9 4 High due to inline
proposed. The authors experimented with a scale-down test circuit of the
L
Ref [19] 7.5 to 3.5 14.67 3 High due to IGBTs proposed design. Although the fault current interrupted from 60A to
in the normal path zero in a short time (1.3msec), inserting a large number of IGBTs in­
Ref [26] 8.7 to 5.6 35.63 4.006 High due to IGBTs creases the complexity, conduction loss and costs.
and thyristors in The proposed HFCL in this paper has a simple structure, lower loss,
the limiting branch
Ref [25] 0.06 to zero - 1.3 High due to the
and cost due to the absence IGBTs and has an appropriate fault current
insertion of IGBTs limiting response. The fault current is limited from 2kA to 1kA (50%) in
in limiting path 1.5 msec (Fig. 15). The comparison of the proposed concept to other
Proposed 2 to 1 50 1.5 Lower due to the HFCL-DCCB is summarized in Table 3.
FCL absence of IGBTs
in both normal and
limiting path and Conclusion
offline L
This paper proposes a new hybrid FCL to reduce the DC fault current
and large capacity DCCB requirements in an MMC-based HVDC trans­
effectiveness of the proposed HFCL compared to other concepts that
mission system. A mechanical breaker is deployed in the main current
exist in the literature. The main concern is the fault current reduction
route to prohibit the switching loss of solid-state switches used in
rate, fault current limitation time and losses of the proposed HFCL.
literature. The current limiting components are placed in the auxiliary
The HFCL proposed in [4] is based on a new theory, i.e., the
branch of the FCL to prohibit power loss in normal operation. The
push-pull principle. Although the authors mentioned that the fault
proposed FCL is connected in series with a hybrid resonance DCCB and
current is limited by 23 % in a short time (between 1.002 to 1.06 sec),
examined based on simulation results. It was confirmed that the rate of
the use of IGBT switches in the normal path and many half-bridge
transient current was suppressed, and the FCL significantly reduced the
submodules based on IGBTs in the limiting path increase the switch­
fault current. Besides, the breaker removes the fault current and the
ing loss and associated costs. In [12], a hybrid current-limiting circuit
HVDC system is restored in an acceptable time range. The proposed
for DC line fault in a multi-terminal VSC-HVDC system is proposed.
structure of FCL is simple, reliable, and cost-effective.
Although the fault current is efficiently limited from around 50kA to
It can be concluded that the proposed hybrid FCL is appropriate for
almost 16kA (32%) in a short time (3 msec), the inline use of the
VSC-HVDC applications and high DC fault current limiting re­
current-limiting inductor increases the normal operation loss of the line.
quirements. As a recommendation, conducting experiments and evalu­
In [17], a novel hybrid DC circuit breaker and fault current limiter with
ating the proposed HFCL-DCCB with physical devices in various fault
optional interruption capability is proposed to limit and interrupt the
locations and line-to-ground faults in a multi-terminal HVDC trans­
fault current. The inline inductors connected to both ends of the breaker
mission system is necessary.
affect the fast-limiting action and lead to normal operation power loss
[25]. The results show that the fault current decreased from 4300A to
CRediT authorship contribution statement
almost 640A in 4 msec (from 1.999 to 2.002sec). An improved FCL
circuit for the VSC-HVDC transmission system is proposed in [19]. The
Gul Ahmad Ludin: Conceptualization, Methodology, Software,
authors deployed IGBT semiconductor switches in the regular current
Validation, Formal analysis, Investigation, Writing – original draft.
path and RL branch in the current limitation branch. The fault current is
Hashmatullah Zeerak: Formal analysis, Writing – review & editing.
efficiently limited from 7.5kA to 3.5kA in 3 msec. It is obvious that a
Qudratullah Tayyab: Software. Ahmad Shah Irshad: Software,
considerably large number of these switches is required to use the FCL
Writing – review & editing. Hidehito Matayoshi: Data curation.
structure based on solid-state switches, i.e., IGBTs, for the current
Natarajan Prabaharan: Writing – review & editing, Visualization.

9
G.A. Ludin et al.
Abdullelah Rasooli: Writing – review & editing. Tomonobu Senjyu:
Conceptualization, Resources, Supervision, Project administration.
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
Data availability
No data was used for the research described in the article.
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