IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 70, NO.

5, MAY 2023 4727

Multiport Current-Limiting Hybrid DC Circuit

Breaker for MTdc Grids
Shuo Zhang , Student Member, IEEE, Guibin Zou , Member, IEEE,
Xiuyan Wei , Student Member, IEEE, Chenghan Zhou, Student Member, IEEE, and Chengquan Zhang

Abstract—The coordination configuration of current-

limiting inductors (CLIs) and hybrid dc circuit breakers
(HCBs) is currently the most commonly used fault handling
method to ensure fault ride-through of multi-terminal dc
grids after the dc-side fault occurs. However, the high cost
of HCB limits its large-scale application. In addition, the
installation of the large CLIs will adversely affect the HCB
performance, such as extending the fault current interrup-
tion time and increasing the energy dissipation pressure of Fig. 1. Topology of the typical HCB.
the arrester. To solve these problems, a multiport current-
limiting HCB (MCL–HCB) is proposed in this article. Com-
pared with the typical HCBs, the MCL–HCB can achieve full rapidly isolated to achieve the converter continuous operation
selective protection of all connected dc lines with signifi- and healthy network fault ride-through [2].
cantly reduced investment costs. Besides, it can suppress The dc circuit breaker (DCCB) can selectively isolate dc
the rising speed of the fault current by embedded CLIs,
while eliminating their negative impacts on the fault current faults with minimum impact on the healthy network. The com-
interruption. The feasibility and superiority of the proposed prehensive review of DCCB technologies has been reported
MCL–HCB are verified by simulations in the PSCAD/EMTDC in [3]. Among the currently proposed DCCBs, the hybrid dc
software and experiments in the scaled-down experimental circuit breaker (HCB) has high action speed and low power loss,
setup. Besides, the performance comparison between the which has a good prospect for applications in MTdc grids [4].
MCL–HCB and existing solutions is elaborated.
The typical HCB is composed of a load current path (LCP), a
Index Terms—Current-limiting inductor (CLI), energy dis- main breaker (MB), and a residual current breaker (RCB), as
sipation, fault ride-through, multiport current-limiting hy- illustrated in Fig. 1. The LCP consists of a load commutation
brid dc circuit breaker (MCL–HCB), multiterminal dc grid
(MTdc).
switch (LCS) and an ultrafast disconnector (UFD). The MB con-
tains hundreds of fully controlled semiconductor switches, and
parallel arresters to dissipate fault current, which is extremely
I. INTRODUCTION expensive and dominates the total cost of the HCB. Since large
number of HCBs is required to achieve full selective protection
HE modular multilevel converter (MMC)-based multiter-
T minal dc (MTdc) grid has the advantages of decoupled
active and reactive power control, no commutation failure, pas-
of the MTdc grid, it is difficult to bear the high cost. To solve this
problem, several economical multiport hybrid dc circuit breakers
(MHCBs) are proposed [5]–[11].
sive network power supply capability, etc., which is suitable
Liu et al. [5] proposed an assembly HCB that can isolate
for the integration of large-scale renewable power generations
the fault on any protected line through the shared MB installed
and has become a research hotspot worldwide [1]. However,
on the dc bus. The dc switchyard proposed in [6] commutates
it is vulnerable to dc-side faults, and the fault current can rise
the fault current into the shared MBs by LCPs in redundant
to tens of times the rated current in several milliseconds after
configuration. The three-port HCB designed for the Tangjiawan
a dc-side fault occurs. Therefore, the dc-side fault must be
±10 kV three-terminal dc distribution network in [7] includes
two complete HCBs based on coupled negative voltage and a
fast mechanical switch. It can interrupt the fault current of 10 kA
Manuscript received 20 October 2021; revised 27 March 2022 and 10 within 2.7 ms. The diode-bridge MHCB in [8] can commutate
June 2022; accepted 28 June 2022. Date of publication 13 July 2022;
date of current version 3 January 2023. This work was supported by the the fault into the MB by LCP on the fault port and diode branches,
National Natural Science Foundation of China under Grant 52077124 and isolate the fault by opening the MB. In [9], the proposed
and Grant 51677109. (Corresponding author: Guibin Zou.) MHCB realizes the current commutation by an integrated LCS
The authors are with the School of Electrical Engineering, Shandong
University, Ji’nan 250061, China (e-mail: 201714182@mail.sdu.edu. instead of individual LCS on each port. The control system of
cn; guibinzou@sdu.edu.cn; weixiuyan@sdu.edu.cn; zhouch1994@ the proposed breaker can be simplified at the expense of lower
mail.sdu.edu.cn; 201914261@mail.sdu.edu.cn). reliability caused by an additional current commutation. The
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIE.2022.3189106. MHCB in [10] is composed of a bidirectional MB and a selector
Digital Object Identifier 10.1109/TIE.2022.3189106 branch for each port. The selector branch is made up by one
0278-0046 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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4728
breaker cell and a string of thyristors. Compared to the MHCB
in [8], the proposed MHCB is more expensive and complex. The
multiline DCCB in [11] consists of a unidirectional MB and 2n
LCPs for n protected lines. After a dc fault occurs, half of the
LCPs, that is, n LCPs should be operated to commutate the fault
current into the MB, which is complex and hard to control. The
MHCB in [12] can reduce the fault current interruption time
(FCIT) by bypassing the current-limiting inductor (CLI) on the
fault port with a small resistor. Since only a CLI in the MHCB is
bypassed, the performance gain is limited. Another advantage of
the MHCB is that it can softly reclose the fault port by inserting
a large resistor in the fault loop.
However, due to the hardware limitation and reliability re-
quirement, the line protection and HCB take at least several
milliseconds in total to isolate the fault, which still cannot match
the dc fault propagation speed. Therefore, fault current limiting
techniques are essential to guarantee the fault ride-through of
the MTdc grid. At present, the CLIs are usually installed to
suppress the rising speed of the fault current, which is effective
and easy to implement [13], [14]. However, the large CLIs have
adverse impacts on the operation of the HCBs, such as extending
the FCIT and increasing the energy dissipation pressure of
the arrester. To avoid the negative impacts of the CLIs, the
typical hybrid current limiting circuit (HCLC) in [15] and its
improved topology in [16] are proposed. They can limit the
fault current by the embedded CLI and bypass the CLI by the
energy dissipation circuit (EDC) during the energy dissipation
of the HCB. Since they do not need full-controlled semicon-
ductor switches, their total costs are acceptable. However, the
resistors in the EDC should dissipate large amount of energy,
which may require special design. Instead of directly configuring
the CLIs, several fault current limiters (FCLs) are proposed
to limit the fault current [17]–[19]. The superconducting FCL
can insert large impedance in the fault loop immediately af-
ter the fault occurs, which has wide application prospects in
MTdc grids [17], [18]. However, the problems of long recovery
time and high investment cost need to be further addressed.
The FCL based on mutual inductance in [19] has a compact
structure and simple control. However, if the load current and
the fault current flow in opposite directions, the load current
has to flow through the diodes and large power losses will be
generated.
The coordinated operation of HCBs and FCLs is expectable in
the MTdc grids. Therefore, there is an opportunity to integrate
the HCB and the FCL into a single device. In addition to the
fault current interruption capability, the bridge-type HCB in
[20] can limit the fault current in two stages by an embedded
inductor and two resistors, respectively. The HCB proposed
in [21] contains a controllable CLI, whose inductance can be
increased to limit the fault current and can be decreased to
facilitate the energy dissipation of the arresters by a controlled
solid-state switch. The multiport current limiting (MCL)–HCBs
in [22], [23] can limit the fault current by inserting a large
inductor in the fault loop. However, the insertion process needs
one or more precharged capacitors to provide negative voltage
to turn-off the thyristor branches, and the reliable turn-off of the
thyristors is hard to guarantee owing to the fast discharging of the
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 70, NO. 5, MAY 2023
Fig. 2. Topology of the proposed MCL–HCB.
precharged capacitors. Besides, compared to directly install the
CLIs, the MCL–HCBs need several milliseconds (the total ac-
tion time of the line protection and the UFD) before limiting the
fault current.
Therefore, considering the problems existing in the currently
proposed FCLs and HCBs, such as the high cost, the complicated
topology and control, the inevitable time delay before fault
current limitation, the high energy dissipation pressure of the
arrester, and long FCIT, a novel MCL–HCB is proposed in this
article, which has the advantages as follows:
1) The expensive MB that consists of many fully controlled
semiconductor switches and large-capacity arresters are
shared by all ports, resulting in low cost.
2) The fault current can be limited by the embedded CLIs
without time delay, and the performance of the line pro-
tections based on the boundary effect of CLIs will not be
influenced.
3) The FCIT and the dissipated energy of the arrester can be
greatly reduced by turning on the inductor bypass branch
(IBB) during energy dissipation process.
The rest of this article is organized as follows. The topology
and operation principles of the MCL–HCB are elaborated in
Section II. In Sections III and IV, the effectiveness of the MCL–
HCB is verified by simulations and experiments, respectively. In
addition, the performance comparison between the MCL–HCB
and existing solutions is conducted. Finally, Section V concludes
this article.
II. TOPOLOGY AND OPERATION PRINCIPLE OF MCL–HCB
A. Basic Topology
The topology of the proposed MCL–HCB is illustrated in
Fig. 2, which has n ports and can substitute n typical HCBs and
FCLs. It has a CLI Lck , an LCP including LCSk and UFDk , two
diode branches Duk and Dlk , a thyristor branch Tk for port Pk
(k = 1, 2, …, n), a shared IBB, and a shared MB. Compared
with the typical HCB, the MB in the MCL–HCB only needs
unidirectional current interruption capability. Therefore, half of
the insulated gate bipolar transistors (IGBTs) can be saved. The
IBB has same structure but different rating as the MB. The CLIs
are responsible for limiting the fault current.
ZHANG et al.: MULTIPORT CURRENT-LIMITING HYBRID DC CIRCUIT BREAKER FOR MTDC GRIDS 4729

Fig. 3. Simplified model of n-terminal dc grid.

B. Analysis Model 2, …, n) satisfy

⎧ di
The equivalent model of the n-terminal dc grid illustrated ⎪ −vck + (Leqk + Lk + Lck ) dtpk + Rk ipk
⎪
⎪
in Fig. 3 is used to analyze the operation principles of the ⎪
⎪ di
+(Lc1 + Lr1 ) dtp1 + Rr1 ip1 = 0
⎪
⎪ t
MCL–HCB. To simplify the analysis with sufficient accuracy, ⎨
the following aspects should be considered: vck (t) = Udc − Ceqk1
t0 ipk dt (1)
⎪
⎪ n  t di
1) The Line k is modeled as a series branch of the lumped ⎪
⎪ ip1 (t) = ipk (t) = Ipre1 + t0 dtp1 dt
⎪
⎪
inductor Lk and the lumped resistor Rk . ⎪
⎩ k=2  t di
2) The MMCk is modeled as a capacitor Ceqk with the initial ipk (t) = Iprek + t0 dtpk dt.
voltage Udc in series with an inductor Leqk [24].
3) The load current of port k is denoted by Iprek . By solving (1), the port currents can be obtained in Laplace
4) The ideal model of the arrester in MB and IBB is domain as follows:
⎧
adopted, which means its voltage will change imme- Udc +s[(Leqk +Lk +Lck )Iprek +(Lc1 +Lr1 )Ipre1 ]
⎪
⎪
n
diately to the residual voltage once the fault current ⎪
⎪ k=2
s2 (Leqk +Lk +Lck )+sRk +C −1
⎪
⎪ Ip1 (s) = eqk
e−st0
is commutated into it. In addition, the residual volt- ⎪
⎨ n
1+ k=2
s2 (Lc1 +Lr1 )+sR1
s2 (Leqk +Lk +Lck )+sRk +C −1
ages of the arrester in MB and IBB are Ur1 and Ur2 , eqk
⎪
⎪ I (s) =
Udc +s[(Leqk +Lk +Lck )Iprek +(Lc1 +Lr1 )Ipre1 ] −st0
e
respectively. ⎪
⎪
pk 2
s (Leqk +Lk +Lck )+sRk +Ceqk −1
⎪
⎪
5) The conduction resistances of the CLIs, the UFDs, and ⎪
⎩ [ 1
sR +s 2
(L +L r1 ] p1
) I (s)
− s2 (L +L +L )+sR +C −1 .
c1

the semiconductor switches are neglected. eqk k ck k eqk

6) The semiconductor switches in the MCL–HCB are con- (2)

sidered as ideal components.
C. Operation Principle
Before the fault occurs, the LCP of each port, the IBB, and the
MB are in the on state, while the thyristor branches T1 –Tn are in
the off state. Therefore, the load currents only flow through LCPs
and CLIs, and no additional power losses are generated. After
the fault occurs, the operation process of the MCL–HCB can
be divided into three stages: fault current limiting, fault current
interruption, and CLI freewheeling current clearance, which will
be analyzed below in detail.
1) Stage 1—Fault Current Limiting: It is assumed that the
short-circuit fault F occurs at time t0 . Then, the fault current
starts to rise and is injected into the fault point, as illustrated in
Fig. 4(a). The rising speed of the fault current will be suppressed
by the embedded CLIs without any time delay. In this period,
the fault port current ip1 and the healthy port current ipk (k =
At time t1 , the MCL–HCB receives the trip signal from the
line protection. The action time of the line protection ranges in
the timeframe of milliseconds [2]. Then, the thyristor branch
T1 on the fault port is turned on and the LCS1 is turned off
to commutate the fault current into the MB. This commutation
process lasts tens of microseconds [9] and ends at time t2 . Then,
the UFD1 is commanded to open, as illustrated in Fig. 4(b). The
UFD based on Thomson-coil actuator has extremely fast action
speed in the zero-current state, and its typical opening time is
2 to 3 ms [25]. It is assumed that the UFD1 is fully opened at
time t3 . During the time period from time t0 to time t3 , the port
currents still satisfy (1) and (2). Besides, since dic1 /dt and dick /dt
are positive, according to (3), the voltage potentials vu2 , …, vun
are higher than the voltage potential vu1 . Therefore, the diode
branches Du2 , …, Dun of healthy ports are blocked by the reverse
voltage and the fault current will not flow through the IBB
dic1 dick
vuk = vu1 + Lc1 + Lck . (3)
dt dt

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4730 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 70, NO. 5, MAY 2023

Fig. 4. Current paths of the MCL–HCB in different periods. (a) t0 < t < t2 . (b) t2 < t < t3 . (c) t3 < t < t4 . (d) t > t4 .

2) Stage 2—Fault Current Interruption: After the UFD is arrester in the MB is defined as the FCIT, which is |t4 −t3 | for
fully opened at time t3 , the MB is turned off and the fault current the proposed MCL–HCB. The dissipated energy of the arrester
in the MB is commutated into the arrester to be dissipated. At in the MB can be obtained as follows:
the same time, due to the high residual voltage of the arrester  t4
in the MB, the voltage potential vu1 is higher than the voltage Ea1 = Ur1 ip1 dt. (6)
potentials vu2 , …, vun . Therefore, the diode branches Du2 , …, t3
Dun are conducted and the CLI currents will freewheel through 3) Stage 3—CLI Freewheeling Current Clearance: Af-
the IBB, as shown in Fig. 4(c). The freewheeling path of the CLI ter the fault current is interrupted at time t4 , the IBB
current is: Lc1 –T1 –Ti (IBB)–Duk –Lck –Lc1 . In this period, the is turned off, and the CLI freewheeling current will be
following equations are satisfied: forced into the parallel arrester to be dissipated, as illus-
⎧ di trated in Fig. 4(d). The freewheeling current decays to zero
⎪
⎪ −vck + (Leqk + Lk ) dtpk + Rk ipk + Ur1
⎪
⎪ at time t5 . During this process, the following equations are
⎪ dip1
⎪+Lr1 dt + Rr1 ip1 = 0  t
⎪
⎨ satisfied:
vck (t) = vck (t3 ) − Ceqk
1
t3 ipk dt
⎧
(4) ⎨ Lck didtck + Lc1 didtc1 + Ur2 = 0
⎪
⎪ 
n  t dip1
⎪ 
⎪ip1 (t) = k=2 ipk (t) = ip1 (t3 ) + t3 dt dt
n
⎪ (7)
⎪
⎪ ⎩ iBB (t) = ic1 (t) = ick (t).
⎩  t di k=2
ipk (t) = ipk (t3 ) + t3 dtpk dt.
Then, the current iBB (t) of the IBB can be obtained as follows:
By solving (4), the port currents can be obtained in Laplace 
domain as follows: Ur2 nk=2 L−1
iBB (t) = ic1 (t4 ) −  ck
t. (8)
⎧ n vck −Ur1 +s[(Leqk +Lk )ipk (t3 )+Lr1 ip1 (t3 )] 1 + Lc1 nk=2 L−1
⎪
⎪
ck
⎪
⎪
k=2
s2 (Leqk +Lk )+sRk +C −1
⎪
⎪ Ip1 (s) = n
k
e−st3 Since the CLI current of the fault port remains unchanged
⎨ 1+ k=2
s2 Lr1 +sR1
s2 (Leqk +Lk )+sRk +C −1 during Stage 2, ic1 (t4 ) in (8) is equal to ip1 (t3 ). The CLI free-
k
⎪
⎪ Ipk (s) =
vck −Ur1 +s[(Leqk +Lk )ipk (t3 )+Lr1 ip1 (t3 )] −st3
e wheeling time Tf and the dissipated energy Ea2 of the arrester
⎪
⎪ 2
s (Leqk +Lk )+sRk +Ck −1
⎪
⎪ (sR1 +s2 Lr1 )Ip1 (s) in the IBB can be obtained as follows:
⎩ − s2 (L +L )+sR +C −1 . ⎧ n
⎨ Tf = t5 − t4 = c1 4 U( c1 k=2 Lck )
−1
eqk k k k
⎪ i (t ) 1+L
(5) n
r2 L−1k=2 ck
It is assumed that the fault current in the MB decays to zero ⎪ 
⎩ Ea2 = t5 Ur2 iBB dt = 1
Lc1 + n 1 [ic1 (t4 )]2 .
at time t4 . After that, the RCB1 can be opened to totally isolate t4 2 k=2 L−1
ck
the fault line. In this article, the energy dissipation time of the (9)

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ZHANG et al.: MULTIPORT CURRENT-LIMITING HYBRID DC CIRCUIT BREAKER FOR MTDC GRIDS 4731

in the MB is as follows:
n n n
Ea10 = El1 + Elk + Esk + Eck (12)
k=2 k=2 k=1

where
⎧
⎪ El1 = 2 Lr1 Ip1. max , Elk = 2 (Leqk + Lk ) Ipk. max
1 2 1 2
⎪
⎨
Eck = 12 Lck Ipk.
2
max (13)
⎪
⎪  t3 +Tc0
⎩
Esk = t3 Udc ipk dt = 12 Udc Ipk. max Tc0
where El1 and Elk denote the stored energy in the dc line; Eck
denotes the stored energy in the CLI; and Esk denotes the energy
provided by the converters. As for the MCL–HCB, the stored
energy will be dissipated by the MB and the IBB together, and
the dissipated energy Ea1 and Ea2 of the arrester in MB and IBB
is
⎧ n n
⎪
⎪ Ea1 = El1 + Elk + Esk
⎪
⎪
⎪
⎨ k=2 k=2
Fig. 5. Flowchart of the operation sequences of the proposed n
MCL–HCB. Ea2 = Eck
⎪
⎪
⎪
⎪
k=1

n 
n n
⎪
⎩ Esum = Ea1 + Ea2 = El1 + Elk + Esk + Eck
It should be noted that small arrester residual voltage in the k=2 k=2 k=1
IBB will satisfy the requirement of the current clearance. After (14)
time t5 , the thyristor unit T1 will be automatically turned off. where El1 , Elk , and Eck in (14) are the same as those in (13),
Then, the MCL–HCB is ready for the next fault. while Esk in (14) is as follows:
 t3 +Tc
1
D. Flowchart Esk = Udc ipk dt = Udc Ipk. max Tc . (15)
t3 2
The operation sequences of the proposed MCL–HCB are
summarized in the flowchart in Fig. 5. Since Tc is much smaller than Tc0 , Esk in (14) is smaller than
that in (12). Therefore, the total dissipated energy of the arrester
E. Influence of IBB on Fault Isolation in the MB and the IBB is much smaller than that of the typical
HCB. Besides, since the fault current energy is dissipated by
As analyzed in Section II-C, the CLI currents will freewheel the MB and the IBB together in the MCL–HCB, the energy
through the IBB in Stage 2 and then be cleared by the arrester dissipation pressure of the MB can be greatly reduced.
in the IBB in Stage 3. In this part, the influences of the IBB on
fault isolation are discussed in detail.
III. PARAMETER DESIGN
In order to simplify the analysis, the line resistance Rk in (5) is
omitted due to its small value (several milliohms per kilometer). A. CLI
In addition, the capacitor voltage is considered constant at Udc . The CLIs are responsible for limiting the fault current and are
By applying the above assumptions, the FCIT Tc of the fault designed based on the system requirements such as the converter
port P1 can be obtained by (5) as follows: fault ride-through [26]. The optimization configuration of the

1 + Lr1 nk=2 (Leqk + Lk )−1 CLI has been thoroughly investigated in the literature [26]–[30],
Tc = ip1 (t3 )  . (10) which will not be discussed here.
(Ur1 − Udc ) nk=2 (Leqk + Lk )−1
In contrast, if only CLIs and the typical HCBs are configured, B. Residual Voltage and Capacity of Arrester in MB
the FCIT Tc0 is as follows:
 The residual voltage of arrester in the MB determines the
1 + (Lc1 + Lr1 ) nk=2 (Leqk + Lk + Lck )−1 FCIT and further influences its dissipated energy during the
Tc0 = ip1 (t3 )  .
(Ur1 − Udc ) nk=2 (Leqk + Lk + Lck )−1 fault isolation. As can be seen in (10), the increase of the
(11) residual voltage Ur1 will lead to smaller FCIT, which will
It is obvious that Tc0 is much larger than Tc (Tc0 is nearly further decrease the arrester dissipated energy according to (12)
three times Tc for the simulation model in Section V). Besides, and (13). However, more IGBT modules will be required if the
the energy dissipated by the arrester in the MB includes the residual voltage of the arrester increases, which will increase
energy stored in the inductance component in the fault loop and the total cost of the MCL–HCB. Therefore, considering the
the energy provided by the converters. As for the solution based above tradeoff relationship, this article refers to the design
on CLIs and typical HCBs, the dissipated energy of the arrester parameters of the HCB that has been put into operation in the

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4732
±500 kV Zhangbei four-terminal dc grid [25], the residual
voltage of the arrester in the MB is selected as 1.6 p.u.
Once the residual voltage of the arrester is determined, its
capacity should be derived. The MCL–HCB should interrupt the
fault current after the short-circuit fault occurs on any location
of the connected dc lines. Therefore, assume that several faults
are set on each dc line at interval of 5% of the line length, and
the dissipated energy of the arrester in the MB after the above
fault scenarios are calculated using (2), (5), and (6). The arrester
capacity should be larger than the maximum value Ecm1 of the
calculated results. In real applications, some safe margin should
be considered to ensure the reliability. Therefore, considering
the reliable coefficient Krel , the arrester capacity of the arrester
in the MB is determined as Krel Ecm .
C. Residual Voltage and Capacity of Arrester in IBB
As can be seen in (9), the residual voltage of the arrester
in the IBB only influences the CLI freewheeling time Tf ,
but is irrelevant to its dissipated energy Ea2 . The increase of
the residual voltage of the arrester in the IBB will lead to
shorter CLI freewheeling time, which will also increase the
implementation cost of the IBB since the IGBT modules in the
IBB should withstand higher voltage. Therefore, considering
the above tradeoff relationship, the residual voltage of the
arrester in the IBB is selected as 10% of the rated dc voltage.
As for the capacity of the arrester in the IBB, after the
dissipated energy of the arrester in the MB under different fault
locations is calculated as shown in Section III-B, the dissipated
energy of the IBB is also calculated by (9). The arrester capacity
of IBB should be larger than the maximum value Ecm2 of the
calculated results. By considering the reliable coefficient Krel ,
the capacity of the arrester in the IBB is determined as Krel Ecm2 .
D. Semiconductor Switch Count
During the period from time t0 to time t3 , according to Fig. 3(a)
and (b) and (3), the diode branches Du2 , …, Dun and the thyristor
branches T2 , …, Tn should withstand the voltage across the
CLIs, and the following relationship is satisfied:
0 < vu1 < vuk < vck < Udc . (16)
Then, the above equation can be obtained, which means the
withstand voltages of the diode branches Du2 , …, Dun and the
thyristor branches T2 , …, Tn are less than the dc grid voltage
Udc , as follows:
vuk − vu1 < Udc . (17)
In the Stage 2, the CLI currents freewheel through the IBB,
and the voltage potentials vu1 , …, uvn are theoretically the same.
Therefore, the diode branches Du2 , …, Dun and the thyristor
branches T2 , …, Tn will not withstand voltage. However, the
IGBTs in the MB should withstand the residual voltage Ur1 of
the parallel arrester, which is also endured by the diode branches
Dl2 , …, Dln .
In the Stage 3, the IGBTs in the IBB are turned off and should
withstand the residual voltage Ur2 of the parallel arrester. This
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 70, NO. 5, MAY 2023
TABLE I
MAJOR PARAMETERS OF SIMULATION MODEL
voltage will also be endured by the diode branch Du1 and the
thyristor branches T2 , …, Tn .
It should be noted that the fault can occur on any port.
Therefore, the IGBTs in the MB and the IBB should withstand
the voltage of Ur1 , Ur2 , respectively. In addition, during the fault
isolation process, the maximum voltages of the diode branches
Du1 , …, Dun , and the thyristor branches T1 , …, Tn are the dc
grid voltage Udc , while the maximum voltages of the diode
branches Dl1 , …, Dln are the arrester residual voltage Ur1 in
the MB. Besides, the maximum current of each branch can be
obtained by Section II-C. Therefore, based on the withstand volt-
age and maximum current magnitude of each branch obtained
in this part and the datasheets of the selected semiconductor
switches, the total number of semiconductor switches can be
obtained.
IV. SIMULATION VERIFICATION
A. Simulation Model
The three-terminal asymmetrical monopolar model is built
in PSCAD/EMTDC software to verify the effectiveness of the
proposed MCL–HCB, whose topology is the same as the MTdc
grid in Fig. 3 with three terminals. The detailed models of the
MMC and the arrester are adopted. The other key parameters of
the simulation model are listed in Table I. The current reference
directions are defined in Fig. 3. Besides, the voltage and the
current are associated reference directions.
B. Simulation Results
The short-circuit fault F occurs at 5.0 s, which is set in the
middle of Line 1. The MCL–HCB receives the trip signal at
5.003 s and starts to isolate the fault. The operation sequences of
the MCL–HCB are illustrated in Fig. 5. The simulation results of
the MCL–HCB during the fault isolation are shown in Figs. 6 and
7. Besides, the MCL–HCB in the simulation model is replaced
by the same CLIs as in the MCL–HCB and the typical HCBs
in Fig. 1, and another simulation with the same fault scenario
is conducted. The performance comparison between the MCL–
HCB and the solution based on typical HCBs is illustrated in
Figs. 8 and 9.
ZHANG et al.: MULTIPORT CURRENT-LIMITING HYBRID DC CIRCUIT BREAKER FOR MTDC GRIDS 4733

Fig. 6. Simulation results of the fault isolation with the MCL–HCB.

(a) Port currents ip1 –ip3 . (b) Currents ic1 –ic3 of the CLIs. (c) Currents
iMB and iIBB of the MB and IBB. (d) Dissipated energy Ea1 and Ea2 of
the arresters in the MB and IBB.

As can be seen from Fig. 6, the fault currents of the ports

P1 , P2 , and P3 reach peak values of 9.17, 2.36, and 6.88 kA,
respectively, during the fault isolation process. After the MB is
turned off at 5.005 s, its voltage rises to the residual voltage of the
parallel arrester. Then, the fault current decays to zero 5.0080
s. Therefore, the FCIT of the MCL–HCB can be determined
as 3.0 ms. Besides, the dissipated energy of the arrester in the
MB is 11.1 MJ. During the energy dissipation process of the
arrester in the MB, the CLI currents freewheel through the IBB
and remain nearly unchanged. After the fault current decays to
zero, the IBB is turned off and its voltage rises to the residual
voltage of the parallel arrester. Then, the CLI currents start to
be dissipated by the arrester in the IBB. The current clearance
process lasts about 45 ms. During this period, the dissipated
energy of the arrester in the IBB is 9.7 MJ. In addition, according
Fig. 7. Voltage waveforms of the key components in the MCL–HCB
during fault isolation. (a) CLI voltages. (b) Voltages of thyristor branches
T1 –T3 . (c) Voltages of diode branches Du1 –Du3 . (d) Voltages of diode
branches Dl1 –Dl3 . (e) Voltages of MB and IBB.
to Fig. 7, during the fault isolation process, the voltages across
the thyristor branches T1 –T3 and the diode branches Du1 –Du3
are less than the system nominal voltage. Besides, the maximum
voltage of the diode branches Dl2 and Dl3 on the nonfault ports
is around 800 kV, which is the residual voltage of the arresters in
the MB. In conclusion, the simulation results of the component
voltages are consistent with the analysis in Section III-C.

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4734
Fig. 8. Simulation results of the fault isolation with the typical HCB.
(a) Port current ip1 –ip3 . (b) Current iMB of MB. (c) Dissipated energy
Ea10 of arresters in the MB.
Fig. 9. Simulation waveforms of the healthy port currents under differ-
ent solutions. (a) Port current ip2 . (b) Port current ip3 .
As can be seen in Fig. 8, if only the CLIs and the typical
HCBs are configured, the peak values of all the ports are the
same with those of the MCL–HCB. However, the FCIT and
the dissipated energy of the arrester in the MB are 9.2 ms and
33.3 MJ, respectively. Therefore, by adopting the MCL–HCB,
the FCIT and the dissipated energy of the arrester in the MB
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 70, NO. 5, MAY 2023
Fig. 10. Topology and photograph of the scaled-down experimental
setup. (a) Topology. (b) Photograph.
can be reduced by 67.4% and 66.7%. Even considering the
dissipated energy of the arrester in the IBB, the MCL–HCB
can reduce the dissipated energy of the arrester by 37.5%. It
should be noted that the above analysis only takes the dissipated
energy of a single HCB into consideration. If multiple lines are
considered, the cost of the solution based on typical HCBs will
increase linearly, while the cost of the MCL–HCB only increase
slightly.
The currents of the healthy ports in Fig. 9 indicate that
although the clearance of the CLI freewheeling currents in the
MCL–HCB needs tens of milliseconds, the recovery of the
healthy lines is still faster than the solution based on the typical
HCBs.
C. Performance Comparison
The MCL–HCB proposed in this article is compared with
the existing solutions. The configuration details of different
solutions are as follows: Solution I—the MCL–HCB proposed
in this article; Solution II—only the CLIs and the typical HCBs;
Solution III—the HCLCs in [15] and the typical HCBs; Solution
IV—the improved HCLC in [16] and the typical HCBs; Solution
V—only the CLIs and the MHCB in [8]; Solution VI—only
the CLIs and the MHCB in [11]; Solution VII—the MHCB in
[12]; and Solution VIII—the MCL–HCB proposed in [22]. It
is assumed that the IGBT module 5SNA3000K452300 (4.5 kV,
4961 USD), the thyristor K0900ME650 (6.5 kV, 400.5 USD),
and the diode VS-SD1100C20C (2 kV, 72.3 USD) are utilized in
all solutions. The redundant configuration of the components is
not considered. The number of IGBTs in the LCS is omitted.
Besides, the costs of the arrester and the energy dissipation
resistor in [12] are both considered as 15485 USD/MJ. The
cost of the UFD is considered as 0.15 MUSD. The performance
factors of different solutions are listed in Table II. It should be
ZHANG et al.: MULTIPORT CURRENT-LIMITING HYBRID DC CIRCUIT BREAKER FOR MTDC GRIDS 4735

TABLE II
PERFORMANCE COMPARISON OF DIFFERENT SOLUTIONS

noted that the term “total arrester capacity” in Table II means TABLE III
MAJOR PARAMETERS OF EXPERIMENTAL SETUP
the total required capacity of the arresters in the typical HCBs
or MHCBs to protect all the dc lines.
As can be seen, since the MB in the typical HCB requires
a large number of IGBTs to withstand a transient interruption
voltage of hundreds of kilovolts, the total cost of all the solutions
based on the typical HCBs (Solutions II–IV) is several times that
of the solutions based on the MHCB. In addition, since the CLIs
have negative impacts on the performance of the DCCBs, the
solutions with only the CLIs configured (e.g., Solutions II, V,
and VI) require much larger arrester capacity and have longer
FCIT than the other solutions. For example, the total required
reverse voltage on the thyristors to help them turn OFF. Therefore,
arrester capacity and the FCIT of Solutions II are nearly two
the costs of the capacitor and its charging equipment should be
times those of Solution III and three times those of Solution
considered. Besides, since the precharged capacitor discharges
IV, respectively. Besides, the total required arrester capacity and
rapidly, it is difficult to guarantee the reliable turn OFF of the
the FCIT of Solutions V are nearly 1.5 times and 3 times that of
thyristors.
Solution I, respectively.
In summary, the solution based on the MCL–HCB proposed
As for the MCL–HCBs in Solutions I and VII, Solution I has
in this article has the smallest investment cost. Besides, it can
the superiorities over Solution VII as follows:
interrupt the fault current faster than the other solutions and
1) Significantly reduce the component cost. The diode
dissipate less energy during the fault isolation.
branches and the thyristor branches in the MCL–HCB
of Section VII should withstand the residual voltage
of the MB, which is 1–2 times of the nominal sys- V. EXPERIMENTAL VERIFICATION
tem voltage. However, only the diode branches Dl1 – A. Experimental Setup
Dln in Solution I should withstand the residual volt-
The topology schematic and photograph of the scaled-down
age of the MB, while the diode branches Du1 –Dun and
experimental setup established in the laboratory to verify the
the thyristor branches T1 –Tn should withstand the volt-
feasibility of the proposed MCL–HCB are illustrated in Fig. 10.
age less than the nominal system voltage. According
The key parameters of the experimental setup are listed in
to Table II, if Solution I is adopted, 18.8% of diodes
Table III. Since LCSs, UFDs, RCBs, and thyristors of the ports
and 37.9% of thyristors can be saved compared with
P2 and P3 will not operate during the experiment, they are not
Solution VII.
configured in the experimental setup, which are marked by the
2) Significantly reduce the arrester cost and the energy dis-
dotted squares. The UFD is implemented by IGBT modules.
sipation pressure. The MCL–HCB in Solution VII only
Once the LCS is turned off, the UFD will be turned off with a
bypasses the CLI on the faulted line through a resistor
delay of 1 ms. The voltage and current are measured by sensors
during the energy dissipation of the arrester in the MB,
and uploaded to a personal computer by series communication.
while the MCL–HCB in Solution I bypasses all the CLIs
by the IBB. Therefore, the performance of Solution I
is much better than Solution VII. It can be seen from B. Experimental Results
Table II that the required arrester capacity and the FCIT During normal operation, LCS1 , UFD1 , RCB1 , and Ti in the
of Solution I are only 50.8% and 68.9% of Solution VII, IBB and the MB the MCL–HCB are in the on state, while the
respectively. thyristors T1 , the MB, and the fault unit F are in the off state.
The MCL–HCB in Solution VIII commutates the fault current The fault unit F is turned on at first, and the fault current rises
into a large CLI to suppress its rising speed. Since the com- rapidly. After 1 ms, the thyristor T1 is turned on and the LCS1 is
mutation process takes several milliseconds, it has the longest turned off. Then, the UFD and the MB are turned off after 1 ms.
FCIT. Besides, a precharged capacitor is required to applying The experimental results are illustrated in Fig. 11. Then, after

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4736 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 70, NO. 5, MAY 2023

Fig. 12. Port currents of configuration scheme of CLIs and typical

HCBs.

VI. CONCLUSION
A. Contributions
To reliably limit and interrupt the fault current, a simple and
easily applied MCL–HCB is proposed in this article. The pro-
posed device integrates the function of the FCL and the DCCB
together. It utilizes embedded CLIs to limit the fault current
without any time delay and eliminates the negative impacts of
the CLIs by configuring an additional IBB.
By adopting the proposed MCL–HCB, the FCIT and the dis-
sipated energy of the arrester can be greatly reduced. Compared
to the solution based on the CLIs and the typical HCBs, the
total cost, the dissipated energy of the arrester, and the FCIT
of the MCL–HCB can all be reduced by more than 2/3 for the
studied case in this article. Besides, it has compact structure and
simple control. Simulations and experiments have verified the
effectiveness of the proposed MCL–HCB.

B. Practical Limitations of MCL–HCB

Although the proposed MCL–HCB performs well in simula-
tions and scaled-down experiments, there are still some practical
limitations to consider before being applied to HVdc grids,
which are as follows:
1) The MCL–HCB contains many units, including signal
Fig. 11. Experimental results of the fault isolation with the MCL–HCB. measurement, UFD operation, and component driving,
(a) Port currents. (b) CLI currents. (c) MB and the IBB currents. (d)
Voltages across the MB and the IBB. which work at different voltage potential and require
power supply. Besides, the operation voltage of the MCL–
HCB is very high. Therefore, the power supply system of
the fault current decays to zero, the IBB is turned off. The MOV the MCL–HCB should be specially designed.
in the IBB starts to dissipate the CLI freewheeling current. In 2) There are a large number of detection, processing, calcu-
addition, the port currents when only the CLIs and typical HCBs lation, and drive units in the MCL–HCB. Therefore, the
being configured are presented in Fig. 12. strict electromagnetic compatibility requirements should
As can be seen from Fig. 11, if the MCL–HCB is adopted, the be satisfied to avoid the misoperation of the breaker.
FCIT is about 0.2 ms. Besides, the dissipated energy of the MOV 3) The arrester is the core component of the MCL–HCB
in the MB and the IBB is 0.15 and 8.77 J, respectively. As for during the fault current interruption. To dissipate the large
the condition that only CLIs and typical HCBs are configured, fault energy, the arresters are required to be connected in
the FCIT is about 2.82 ms, and the dissipated energy of the parallel to increase their capacity. However, due to inher-
typical HCB is 19.99 J. Therefore, by adopting the proposed ent imperfections in the manufacturing process, not all
MCL–HCB, the FCIT can be reduced by 92.9%. Besides, the the arresters have identical V-I characteristics. Therefore,
dissipated energy of the arrester can be reduced by 55.4%. It the dissipated energy among the parallel arresters is un-
should be noted that a single MCL–HCB connects to multiple equally distributed, which will cause thermal overloading
dc lines, and the reduced arrester capacity of all the HCBs are of one or more arresters and further result in their damage.
considerable. Although the proposed MCL–HCB can reduce the total

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ZHANG et al.: MULTIPORT CURRENT-LIMITING HYBRID DC CIRCUIT BREAKER FOR MTDC GRIDS
dissipated energy and split the remaining energy to be
dissipated by two units, the issue of the arresters should
also be considered.
4) The existed current sensors may have maximum de-
tectable current magnitude and limited bandwidth for
HVdc application. The current sensors based on Ro-
gowski coil can carry tens of kiloamps over an extended
bandwidth up to tens of MHz [31], which can satisfy the
requirement of the HVdc breaker.
5) During the normal operation, the LCS in the proposed
MCL–HCB should conduct the load current. To ensure
that the junction temperature of the IGBT is lower than the
limit, it is necessary to configure a more efficient cooling
system for the LCS, like the water-cooling system. Be-
sides, the LCS in the MCL–HCB should withstand larger
voltage than the LCS in the typical HCB in Fig. 1 during
current commutation. In the typical HCB, the voltage
across the LCS should be larger than the voltage drop
on the MB to commutate the fault current into the MB.
However, in the proposed breaker, the voltage across the
LCS should be larger than the total voltage drops of
the MB, a thyristor branch Tk , and a diode branch Dlk .
Therefore, more IGBT modules should be included in
the LCS of the MCL–HCB. Fortunately, the LCS in the
proposed breaker is unidirectional, which can save half
IGBT modules compared to the bidirectional LCS in the
typical HCB.
6) The MCL–HCB cannot handle the dc bus fault. Although
the dc bus is usually configured indoors and has low
fault probability, the dc bus fault isolation should be
considered. If the proposed breakers are adopted in the
MTdc grid, the dc bus fault isolation will rely on the
breakers on the remote end of the dc line connected to
the dc bus.
7) Compared to semiconductor switches, the UFDs in the
MCL–HCB have higher possibility to fail due to its me-
chanical operation. Once the UFD fails to operate, the
breaker will not perform as intended. Therefore, the reli-
able open of the UFD is extremely important. The UFD
in the MCL–HCB can be designed as several vacuum
breakers in series as have been adopted in the typical
HCB, which cannot only improve the open speed, but
also increase the reliability by redundant configuration.
C. Future Article
Next step, we plan to design a medium-voltage prototype of
the MCL–HCB to further verify its performance. The LCS in
the proposed MCL–HCB causes power losses during normal
operation and requires cooling systems, which will reduce grid
efficiency and increase costs. To overcome these limitations, we
will explore a better approach to achieve reliable current com-
mutation with low power losses to replace the LCS in the future
article. Besides, the MB and the IBB of the proposed MCL–HCB
consist of a large number of fully controlled semiconductor
switches, resulting in high implementation cost. Therefore, in
future article, we will investigate the use of half-controlled
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4737
semiconductor switches or other economical methods to realize
the functions of MB and IBB to further reduce the cost.
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the Ph.D. degree in electrical engineering with
the School of Electrical Engineering, Shandong
University, Ji’nan, China.
His research interests include power system
protection and active distribution networks.
Shuo Zhang (Student Member, IEEE) received Chengquan Zhang received the B.Sc. and
the B.Sc. and Ph.D. degrees in electrical en- M.Sc. degrees in electrical engineering from
gineering from Shandong University, Ji’nan, Shandong University, Ji’nan, China, in 2019 and
China, in 2017 and 2022, respectively. 2022, respectively.
He is currently a Postdoctoral Researcher His research interests include HVdc protec-
with the Shandong University, Ji’nan, China. His tion and circuit breaker.
research interests include HVdc control and pro-
tection and power electronics.

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