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Design and Analysis of 8-Bit Multiplier for Low Power VLSI Applications

Conference Paper · October 2022

DOI: 10.1109/MysuruCon55714.2022.9972421

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 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon)

Design and Analysis of 8-Bit Multiplier for Low

Power VLSI Applications
Divyansh Jangalwa1 M. Nagabushanam2 M. C. Parameshwara3
Department of Electronics and Department of Electronics and Department of Electronics and
Communication Engineering Communication Engineering Communication Engineering
2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon) | 978-1-6654-9790-9/22/$31.00 ©2022 IEEE | DOI: 10.1109/MysuruCon55714.2022.9972421

M. S. Ramaiah Institute of Technology M. S. Ramaiah Institute of Technology Vemana Institute of Technology

Bangalore, India Bangalore, India Bangalore, India
djangalwa123@gmail.com nagabhushanam1971@msrit.edu pmcvit@gmail.com

Abstract—Multiplier is the most essential and primitive element
of multiply and accumulate (MAC) unit, and is typically found
in many digital signal processing (DSP) applications.
Conventionally the multiplication operation is carried out
through repeated addition; hence multipliers use extensively the
full adders (FAs) for the addition process. The energy efficiency
of the multiplier is determined in terms of power delay
consumed per bit operation. Thus, FA plays a vital role in
determining the overall efficiency of the multiplier. In this
paper, a study, design, and simulation of an 8-bit additive
multiply module (AMM) using different FA circuit architectures
is presented. Further, the designed AMM is compared against
the traditional Wallace and Dadda tree multipliers in terms of
design metrics. To perform comparison of all the multipliers,
they are described using RTL codes, simulated and verified
using Cadences’ EDA tools. To extract power and area metrics,
the verified designs are further synthesized under common
constraints using Cadences’ generic 180 nm technology file.
Keywords—Additive Multiply Module, Dadda Tree Multiplier,
Wallace Tree Multiplier, full adder architecture.
I. INTRODUCTION
The FA and multiplier circuits (FMCs) being the
primitive the blocks of multiply and accumulate circuit
(MAC) determines the overall performance of the DSP
system [1-3]. These FMCs consume a significant amount
of power in any DSP-based system and hence it requires
optimizing the performance of FMCs for targeted
applications [4]. In today's world of rapidly expanding
soft computing and digital technology, there is a huge
demand for power-efficient hand-held gadgets. These
gadgets are essentially battery-operated and need to
process computationally intensive operations. These
highly intensive operations consume a lot of power and
hence battery may soon dry out. Therefore, the power
consumption of a device is an important consideration [5-
10] that the designers need to give immediate attention.
Thus, the power optimization task constrains the
designers to design and develop energy-efficient gadgets.
Most portable electronic gadgets, such as cellular
telephones, iPods, and laptops, as well as the present
Internet of Things (IoT) devices, need to consume low
power without any compromise in performance. A
significant power-consuming element in microprocessor
ALU seems to be the multiplier. The device's power
consumption can be lowered at many design levels,
including the logic, circuit, gate, and transistor levels. To
increase the speed of multiplication, it is necessary to
speed up partial product accumulation. The performance
of the multiplier is critical, in determining the overall
performance of the system. In the literature, we can find
different types of adders and multiplier architectures such
as an array multiplier, Booth's multiplier, Booth-Wallace
Modified multiplier, and Wallace tree multiplier (WTM),
Dadda tree multiplier (DTM) [3-4][11-15].
In this study, we present the study of an 8-bit AMM based
on different FA architectures that are reported in the
current literature. The organization of the paper is as
follows. Section I is Introduction. Section II presents the
literature survey; Section III presents the concept of
AMM multiplication process. Section IV discusses the
design and results of AMM and its counterpart
architectures. Finally, Section V concludes this paper.
II. LITERATURE SURVEY
Significant efforts are being made around the world to
develop multipliers for low-power VLSI applications.
This section provides an overview of the recently
proposed multipliers aimed at improving the design of
low-power multipliers. A thorough discussion of previous
work is included in the literature survey. The referred
works provide an insight limitation and propose a novel-
based multiplier to further reduce power for VLSI
Applications, the following are the most recent works
mentioned in the overview.
P. Choppala et al.[2] proposed a multiplier design that is
area efficient, low power, and Full Swing Hybrid
Multipliers. This research paper focuses on Gate Diffusion
Input based hybrid FA of a 1-bit with only 14 transistors,
within the standard array and WT multipliers. This work
implements a hybrid adder and Wallace Tree multipliers
within the array; thus the names H-A and H-WT are kept.
The use of WT raises power consumption and is
compensated by the use of Gate Diffusion Input
technology, which also decreases the area. But as a
limitation that the GDI structures fail to achieve full
swing, it can be overcome by the use of H-A & H-WT
multipliers. Ultimately partial products are added by CSA.
Tanner EDA tool was used to implement the proposed
designs with 250 nm technology and power consumption
for the designs is 583 µW and 693 µW.
A. Jain et al. [3] implemented an 8×8 Multiplier which is
an integration of Vedic Mathematics and Booth WT
Multiplier. It uses the Radix-4 Booth algorithm, Wallace
Tree algorithm, and fusion of Modified Booth and
Wallace algorithms. It also uses the Vedic multiplication
algorithm and it combines the Vedic-Booth-Wallace
algorithms and the new proposed multiplier are designed
which results in a reduction in delay and area.

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 M. Munawar et al. [4] implemented a modified version of
the DT multiplier which uses a carry select adder and
binary to an excess-1 converter, as a result, it increases its
efficiency in terms of power and speed. The modified
multiplier is Implemented and compared with existing
multipliers in terms of delay, dynamic power, and PDP.
The analysis depicts that the proposed multiplier
outperforms other multipliers in terms of performance.
M. C. Parameshwara and M. Nagabushanam [5] proposed
a 4 novel reversible FAs which are based on cutting-edge Fig.1. An abstract model of4×2 AMM
FA architecture design. The merits of proposed RFAs are
compared to those of reported reversible FAs on the basis (1)
of QGMs. According to the result comparison, the The output of each AMM submodule, in general, is
proposed RFAs are efficient in terms of the number of represented as in Eqn. 2 (from Fig.1), where Pi is an
constant inputs/garbage outputs and the quantum cost. intermediate partial product
Che-Wei Tung et al. [6] proposed pipeline MAC
(2)
architecture with high speed and low power design.
Where carry propagations of additions frequently result in All the generated intermediate PP are shifted and added as
higher power consumption and path delay in a per their respective weights as shown in Fig.2. An
conventional MAC. Additions to the partial product example of M=187×235=43945 using a binary 8×8 AMM
reduction process were incorporated to address these is illustrated in Fig.3. The process of addition and
issues. The implemented MAC design does not perform pipelining of all intermediate partial products generated
the operation of addition and accumulation of most from each sub-module of AMM is pictorially represented
significant bits until the partial product (pp) reduction in the block diagram shown in Fig.4
process of the following multiplication. To properly deal
with an overflow in the PP reduction process, an adder
with lower bit size is used to accumulate the carries.
Experiment analysis reveals that the implemented MAC
design can significantly decrease both the power
consumption of the circuit and the area occupied by it
under the same timing constraint as compared with
existing works.
Kokila Bharti Jaiswal et al. [7] implemented a modified
version of FA using multiplexers and an EX-OR gate.
When the modified FA is used in the reduction stage of
the WT multiplier, the delay, area, and average power are Fig.2. A pictorial representation of an 8 × 8 multiplicationvia 4 × 2
reduced by 17.65 percent, 45.75 percent, and 37.45 AMM
percent respectively, when compared to existing methods.
The synthesis results indicate the proposed design
dissipates 1.106 mW of power for an 8-bit multiplier and
is appropriate for low power, area applications.

III. MULTIPLICATION PROCESS USING AMM

The multiplication of two eight numbers to get a final

product M=X×Y is explained as follows [12]. To multiply
X with Y using the AMM, the multiplicand X is halved
into two equal parts namely lower half bits (XL) and
higher half bits (XH) respectively. The multiplier is also
divided into four equal parts viz. Y1, Y2, Y3, and Y4,
where the weight of the bits will increase from Y1 to Y4.
The multiplication of XL and XH with each part of Y is
carried out using an independent additive multiply block
as shown in Fig.1.The pictorial representation of the
process of multiplying two numbers using AMM is Fig.3. An example of 8×8 multiplication using AMM module
illustrated with an example of 8×8 multiplication in Fig.2,
along with an example shown in Fig.3. In Fig.2 and Fig.3,
the X and Y represent multiplicand and multiplier
respectively. The final product using AMM multiplier in
general is represented as in Eqn.1.

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 multiplier is less than WTM and DTM and could be used
for various low-power VLSI applications.

TABLE 1 AREA & POWER COMPARISON OF ALL THE

MULTIPLIERS

Multi FA
Area in Leakage Dynamic Total Power
plier archite
µm2 Power in nW Power in μW in μW
cture
WTM 4916.42 249.25 419.48 419.73

DTM Generic 4497.29 233.65 373.86 374.09

AMM 4716.84 242.20 362.74 362.98

XOR-
5229.1 210.05 371.16 371.37
MUX
XNOR-
5229.1 204.62 318.20 318.40
WTM MUX
XOR/XN
OR- 4916.42 249.25 419.48 419.73
MUX
XOR-
4816.63 193.92 336.30 336.49
MUX
XNOR-
4816.63 188.36 283.52 283.71
DTM MUX
XOR/XN
OR- 4497.29 233.65 373.86 374.09
MUX
XOR-
Fig.4. Block diagram of binary 8×8 AMM 5036.17 202.42 310.97 311.17
MUX
XNOR-
AMM 5036.17 196.90 268.81 269.00
Beginners are taught how to multiply long-term on base- MUX
XOR/XN
10 things using this way. An 8-bit AMM (Additive OR- 4716.84 242.20 362.74 362.98
Multiply Module) multiplier was built using Verilog's 4x2 MUX
AMMs. The primary goal of this work is to optimize the
power consumption of 8-bit multiplier.
Table 1 shows the comparison of parameters like area,
power of WTM, DTM, and AMM with all three FA
IV. RESULTS, AND DISCUSSION architectures viz. XOR-Mux, XNOR-Mux, and
XOR/XNOR-Mux. It can be seen clearly from Table 1that
AMM with XNOR-MUX FA has the least power
The 8×8-bitWTM, DTM, and AMM multiplier consumption and hence it can be used for several low-
schematics are designed using Verilog RTL codes based power VLSI applications.
on generic FA architecture [1,5] and tested for various
input data combinations and the functionality is verified,
the proposed designs are also synthesized with Cadence
Genus tool (180 nm standard cell library).The proposed
multipliers are then implemented with different FA
architectures viz. XOR-Mux, XNOR-Mux, and
XOR/XNOR-Mux [5] to further study the power
behaviour of the multipliers under different FA
architectures.

The performances are compared by extracting area,

leakage power, and dynamic power of various multipliers
under different architectures of FAs, which are listed
inTable1.In this table, the lowest and highest values are
highlighted using ‘Blue’ and ‘Red’ text. The following
results show that the power consumed by the AMM
Fig.5. Area of estimation of various multipliers
Fig.5 shows the graphical representation of area
estimation for different multipliers. In summarizing that
the area of DTM using generic FA consumes the least
area compared to other multipliers.

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Fig.6. Power consumption of various multipliers based on generic
FA
Fig.6showsthe comparison of power consumption of
various multipliers based on generic FA, the summary of
this is as follows:
• Among the leakage power comparison, the
DTM has the lowest leakage power and WTM
has the highest leakage power consumption.
• Among dynamic and total power consumption
the AMM has the least power consumption and
WTM has the highest power consumption.
Fig. 7 Power consumed by various multipliers using different FA
architectures.
Fig. 7 shows the comparison of power consumption of
various multipliers based on XOR-Mux, XNOR-Mux, and
XOR/XNOR-Mux FAs, the summary of this is as follows:
• Among the leakage power comparison, the DTM
has the lowest leakage power and WTM has the
highest leakage power consumption.
• Among dynamic and total power consumption
the AMM has the least power consumption and
WTM has the highest power consumption.
V. CONCLUSION
In this paper, a design of three multiplier architectures
namely Wallace tree, Dadda tree, and Additive multiplier
module have been designed with various FA circuit
architectures using Verilog RTL codes, simulated, and
synthesized using Cadences’ Genus tool based on
standard cell library (180 nm). Based on the synthesis
results the design parameters such as power and area have
been extracted compared, and important inferences have
been drawn.
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