Asymmetrical Three-Phase Multilevel Inverter for

Grid-Integrated PLL-Less System

Rohit Kumar
Student Member, IEEE
Department of Electrical Engineering,
Visvesvaraya National Institute of
Technology (VNIT), Nagpur, India
rkkumarr68@gmail.com
2023 IEEE 3rd International Conference on Sustainable Energy and Future Electric Transportation (SEFET) | 979-8-3503-1997-2/23/$31.00 ©2023 IEEE | DOI: 10.1109/SEFET57834.2023.10244867
Madhuri A. Chaudhari Pradyumn Chaturvedi
Senior Member, IEEE Senior Member, IEEE
Department of Electrical Engineering, Department of Electrical Engineering,
Visvesvaraya National Institute of Visvesvaraya National Institute of
Technology (VNIT), Nagpur, India Technology (VNIT), Nagpur, India
machaudhari@eee.vnit.ac.in pc220774@gmail.com

K. S. Raja Sekhar
Student Member, IEEE
Department of Electrical Engineering,
Visvesvaraya National Institute of
Technology (VNIT), Nagpur, India
rajasekhar.vnit@gmail.com

Abstract— Nowadays, the conventional power system is Solar-PV

deregulating into Distributed Generation (DG) like Renewable
Energy Sources (RES). This advancement helps in improving
the environmental issues over fossil fuel-based generation. DG
can be operated either as an islanding and/or as a grid-
integrated power system. The uncertain nature of the grid at the
Point of Common Coupling (PCC) has a significant impact on
the stability of the DG grid-integrated Multilevel Inverter
(MLI). The mathematical burden due to Park’s transformation
is reduced by utilizing stationary frame-based control
techniques, and the delay due to PLL is avoided using PLL-less
control. The proposed topology of MLI with asymmetrical
configuration with input DC source ratio of 3:1 integrated with
AC grid. This topology consists of the level generation and
polarity generation units. The proposed MLI topology develops
a nine-level output voltage by five switches per phase. This
paper also presents the mathematical modeling of Voltage
Modulated Direct Power Control (VM-DPC). The strategy for
MLI under various dynamic conditions like load variations
(Pload, Qload), and different available power at PCC for DG
interfaced MLI (Pref, Qref) with AC microgrid is developed. A 15-
kVA system is simulated in MATLAB/Simulink and tested
under dynamic conditions to verify the design of the proposed
system.
Keywords—Distributed Generation (DG), MLI Topology,
LSPWM, VM-DPC, SRF, PLL-Less
I. INTRODUCTION
PCC
DC-DC DC-AC AC Bus
AC-DC DC-AC
Wind
AC Grid
Residential Industrial
Load Load
Micro-Grid
DC-DC DC-AC
BESS
Fig. 1. Architechture of AC micro-grid.
When the output level increases, the device count
significantly increases, hence cost, and power losses of the
system increased [5]. To solve this issue, various topologies
are proposed. For the high-power RES application, the high-
power inverter is required, and MLIs are introduced for high
output voltage levels with low power rating semiconductor
devices. The design of an MLI depends on various factors
such as the device count, gate driver circuit, and the number
of dc sources [6]. The synchronization of the grid and inverter
is accomplished using the PLL. Hence, the response of the
system depends on the PLL performance. The PLL requires
the fundamental value of grid frequency and voltage for grid
synchronization [7]. In weak grid conditions, the PLL affects

T
HE Multi-Level Inverter (MLI) becomes a tenable
option in DG-based renewable energy, industrial and
residential loads for dc to ac conversion. Due to the
ingress of renewable energy sources (wind, solar-PV,
etc.,), MLI gives effective and efficient conversion of electric
power compared with conventional 3-phase VSI. In general,
the AC microgrid contains RES along with residential and
industrial loads as shown in Fig. 1 [1-2]. The output of MLI is
staircase i.e., approximated to sinusoidal. So it has great
achievements with low THD, reduction in filter size, low
power loss, and good power quality. In MLI, the power quality
of output is enhanced by increasing the number of output
levels. The symmetrical, asymmetrical dc sources are used to
gain higher levels of output voltage [3]. There are many MLI
topologies, which are formed by different arrangements of DC
sources and switches. The classical MLI topologies are Flying
Capacitor (FCMLI), Diode Clamped/Neutral Point Clamped
(NPCMLI), and Cascaded H-bridge (CHBMLI). These
inverters are popular for their simple structure, easy control,
and high efficiency [4].
the system’s stability. In the case of frequency condition, the
output impedance is affected because of the presence of PLL,
due to which the performance of the overall system is
disoriented [8].
In this paper, an MLI topology is preferred with
asymmetrical two DC sources and five IGBT switches per
phase. This configuration is operated with the LSPWM
control technique to improve DC source utilization. The
significance of voltage-modulated direct power control (VM-
DPC) operation for grid-tied three-phase, nine-level inverter
without PLL, under various available power (Pref, Qref) and
load demand (Pload, Qload) are studied and analyzed. The
control technique is designed to extract the maximum
available power at the DC end of the solar-PV system, which
is to be injected into PCC.
This paper is organized as the configuration of the
proposed MLI and its description is illustrated in Section II.
Section III focuses on the design of the LCL filter and an
overview of grid-tied MLI without PLL. The mathematical

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modeling of VM-DPC is illustrated in Section IV. In Section unit (level generation unit) of the presented topology which is
V, the simulation results and discussion of the VM-DPC later fed to the polarity reversal unit with different polarities
controller with MLI for grid-integrated are presented. The combination [9].
conclusion is the last Section VI, which consolidates the
important points of the paper. C. Operating Modes
The proposed multilevel inverter topology works both for
II. PROPOSED MULTILEVEL INVERTER TOPOLOGY symmetrical as well as asymmetrical DC voltage sources.
A. Description of the Proposed MLI Topology TABLE I. COMPARATIVE ANALYSIS OF THE PROPOSED MLI WITH
The proposed MLI topology is a combination of a level CLASSICAL MLI FOR NINE-LEVEL
generator and a polarity generator unit. The basic unit of the Topologies → NPC FC MLI CHB- Proposed
presented MLI topology is shown in Fig. 2. It consists of five Characteristics ↓ MLI [1] [3, 4] MLI [5] MLI
switches, out of which two switches S1, and S2 are Unidirectional 16 16 16 7
bidirectional, and the remaining three switches, S3, S4, and S5 switches
are unidirectional. The bidirectional switch is used to reduce Bidirectional 0 0 0 2
the device stress and fault-tolerant operation. The proposed switches
topology works either in a symmetrical configuration which Balancing 0 7 0 0
gives a five-level output voltage or in an asymmetric Capacitors
configuration which gives a maximum of nine-level output Clamping diodes 12 0 0 0
voltage. The presented three-phase, nine-level MLI is with DC Bus 8 8 4 2
asymmetric two dc sources configuration ratio of 3:1. The Capacitors
conventional MLI topologies consist of all power switches Input DC 1 1 4 2
working synchronously to generate high-frequency Sources
waveforms both in positive as well as in negative polarity. But No. of Carrier 8 8 8 4
in this topology, the burden of generating a negative voltage signals
waveform is obtained by the polarity generator circuit i.e., the DC Bus Sharing DC Bus DC Bus Separate Separate
conventional H-Bridge inverter. Hence, only positive voltage Sharing Sharing DC DC
generation switches are required to have high-frequency source source
switches whereas the H-bridge works on input power Asymmetrical Not Not possible possible
frequency which helps in generating polarity for both positive configuration possible possible
as well as negative steps at the output terminal. Redundancy No yes yes yes
Structure No No Yes Yes
This MLI topology is modular and can be used for high-
Modularity
level voltage outputs. Another advantage of the presented
Voltage Average High Very Very
MLI topology is that it reduces the requirement of switching
Unbalancing small small
devices and the complexity of the gate driver circuit as
Problem
compared to other conventional MLI topologies. The
Flexibility No No yes yes
LSPWM carrier waves required for generating output voltage
reduce to half when other conventional MLIs. This is because i) Symmetrical Operating Mode
the basic level generator unit generates the positive levels
In the symmetrical mode of operation, all the DC sources
followed by the polarity generator H-bridge. This advantage
present in the basic topology have equal values i.e., Vdc1 = Vdc2
is significant because for higher-level MLIs the carrier waves
= Vdc. In this mode of operation, the levels of the output
requirement is very large. Hence, this topology is
voltage are double the total number of DC sources present in
advantageous for a high-level generation. A comparative
the basic topology and the 0th level. The basic unit of presented
study of various classical and proposed MLI topologies for the
topology output levels produced is five-levels. Some
nine-level is given in Table I.
switching states are unused or redundant.

S1 ii) Asymmetrical Operating Mode

T1 T3
In this mode of operation, all the DC sources present in
S5
S3
ia Via basic topology are not equal but set in a particular ratio
+ +
Vdc1 - Vdc2 VL concerning one voltage source. The advantage of asymmetric
-
ib
DC source configuration is that; it generates more steps in
Vib output voltage without changing switching devices. Using
S2 T4 T2
S4 asymmetrical sources, the presented topology can produce all
ic
the possible levels of combinations of voltage sources by
Level Generation Phase-A Polarity Generation
Vic addition and subtraction. If DC voltage sources are in the ratio
Phase-B of 3:1, it will produce voltage level of all possible
Phase-C combinations ±(Vdc1+Vdc2), ±(Vdc1), ±(Vdc1-Vdc2), ±(Vdc2), and
Fig. 2. Configuration of proposed multilevel inverter. 0. All possible switching states of asymmetric source
configuration for nine-level output with redundant states are
B. Polarity Generation Unit shown in Table II. Fig. 3 (a) to (f) shows the circuit diagrams
The polarity reversal unit consists of a simple H-bridge. for various modes of operation. Hence the basic unit of the
The polarity generation unit consisting of four unidirectional proposed topology can produce a maximum of levels of
power frequency switches (T1, T2, T3, T4) is shown in Fig. 2. output. In this mode of operation output levels are nine, and
The magnitude of the output voltage is generated by the basic the carrier LSPWM waves required for other conventional

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topologies are eight but, in this topology, it is half of that in Amplitude modulation index (ma); 𝑚𝑎 =
𝑉𝑚
(1)
conventional topology i.e., four. Thus; utilization of switches 𝑉𝑐𝑟(𝑚−1)

is more while operating on a higher level. Frequency modulation index (mf); 𝑚𝑓 =

𝑓𝑐𝑟
(2)
𝑓𝑚
TABLE II. SWITCHING STATE AND OUTPUT VOLTAGE OF NINE-
LEVEL MLI Here; the ‘Vm’ and ‘fm’ are the amplitude and frequency of the
modulating waveform respectively. The ‘Vcr’ and ‘fcr’ are the
Sr. Voltage Output amplitude and frequency of the carrier waveform respectively.
No. S1 S2 S3 S4 S5 State No. Voltage (VL) There is various combination of carrier waveforms in the
1 0 0 1 0 1 1 Vdc1+Vdc2 LSPWM technique as follows; in-phase opposition
2 1 0 0 0 1 2
Vdc1
disposition, in-phase disposition, and alternate-phase
3 0 0 1 1 0 3 opposition disposition.
4 1 0 0 1 0 4 Vdc1 -Vdc2
5 0 1 0 0 1 5 Vdc2 III. GRID-TIED MLI WITH LCL-FILTER WITH-OUT PLL
6 0 1 0 1 0 6 0 Nowadays, the grid-integrated multilevel inverter is
gaining very high attention since DC-AC conversion is needed
Sr. No. 1 Sr. No. 2 to integrate RES into the AC microgrid. The Stationary
S1 S1
Reference Frame (SRF, αβ0) controller model without PLL is
S3
S5
S3
S5 applied to control the active and reactive power of a grid-tied
Vdc1+ + + + three-phase, nine-level asymmetrical MLI [10]. In the PLL-
- Vdc2 VL = Vdc1 - V dc2 VL =
- -
(Vdc1+Vdc2) Vdc1 Less system, measure three-phase grid voltage (vg_abc) and
S2 S2 current (iabc) directly converted into SRF and supplied to the
S4 S4 controller by taking the real and reactive power as a reference
(a) (b) (Pref, Qref) input, which controls the modulation index of
S1
Sr. No. 3
S1
Sr. No. 4 LSPWM to control the MLI. An AC grid-integrated to a three-
phase, nine-level MLI with VM-DPC Control is shown in Fig.
S5 S5
+
S3
+ +
S3
+
5. The VM-DPC based PLL-Less controller with the grid-
Vdc1
- - V dc2
VL =
Vdc1
- - V dc2
VL = integrated system has various advantages like [11]
Vdc1 (Vdc1-Vdc2)
S2 S2  Dynamic response of the system is improved.
S4 S4
 The tracking performance of reference power
(c) (d)
variations is smooth.
Sr. No. 5 Sr. No. 6
S1 S1
 The complexity due to PLL is removed, and the
computation burden due to synchronous rotating
S5 S5 farm (i.e., dq0 to αβ0 or αβ0 to dq0) is avoided.
S3 S3
+ + + +
Vdc1
- - Vdc2 Vdc1
- - Vdc2  Decreases the computation time.
VL = Vdc2 VL = 0
3-phase, 9-Level 3-phase LCL-
S2 S2 MLI Topology Filter
3-phase AC-Grid
S4 S4 Phase-C
RES ia PCC vga
Phase-B Via Li Lg
Phase-A
(e) (f) DC Vg_abc
Energy
ii_abc Rd ig_abc ib vgb
Vib
Source
Fig. 3. (a) to (f), different modes of operation of the proposed MLI as per Cf
+ iC_abc
Table II. Vic
ic vgc
Vdc -

D. Control Technique for the Proposed MLI jXL

Variable
S1 S2 S 3 S 4 S 5 ia ib ic Load
The Level shift pulse width modulation (LSPWM) is used Gate
Pulses
R

to control the proposed MLI. In LSPWM, all carrier signals

VM-DPC Control
have the same frequency and peak-to-peak amplitude [9]. For abc
αβ0
an MLI with m-voltage levels {(m-1)/2} carrier signals are iα iβ vα
abc
required. Four carrier signals are disposed over one another Pg
Qg VM-DPC
P Active &
Reactive
vβ vg_abc

with 5 kHz which is compared with reference modulating Pref Algorithm Q Power iα iC_abc
Qref calculation iβ
signals having a frequency of 50 Hz as shown in Fig. 4. LSPWM
va_ref u
ua α
uβ αβ0 ii_abc
αβ0 icα
vb_ref ub
Modulating signal Carrier signal icβ
uc abc
vc_ref
÷ Vm
Amplitude

Fig. 5. AC grid-integrated three-phase, nine-level MLI with VM-DPC .

A. LCL-Filter Design
For reducing the harmonics, the LCL filter is used. This
connects the grid to MLI. It provides enhanced high-order
Amplitude

harmonic attenuation capabilities in addition to increased

dynamic capabilities [12]. From Fig. 6, the inductor on the
MLI side (Li), the inductor on the grid side (Lg), the damping
Time (Sec)
resistance (Rd), and the filter capacitor (Cf) are the per-phase
equivalent circuit parameters of the LCL filter. The filter
Fig. 4. PWM for proposed MLI by LSPWM. element on the MLI side ‘Li’ is given as;

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 𝑉𝑑𝑐 R jωL
𝐿𝑖 = (3)
16∗𝑓𝑠𝑤 ∗∆𝐼𝐿𝑚

𝑆𝑛 ∗√2 iabc
∆𝐼𝐿𝑚 = 0.1 ∗ 𝐼𝑚 Here; { 𝐼𝑚 = } (4) vi_abc
√3∗𝑉𝑛 Vg_abc
Here; Im is the maximum current via Li, while ΔILm is the
maximum ripple current. ΔILm is usually limited to 10% to
25% of Im. The ‘Vdc’ is the DC input voltage to MLI, ‘Sn’ is 3-
phase a nominal power, ‘Vn’ is nominal grid line voltage, and Fig. 7. Equivalent circuit diagram of grid-integrated 3-phase, 9-level MLI.
‘fsw’ is the switching frequency of 3-phase, 9-level MLI.
Now, the current that was injected into PCC ‘iabc’ can be
ii Li ig Lg expressed as,

ic Rd Vg 𝑉𝑖𝑎 − 𝑉𝑔𝑎 = 𝐿
𝑑𝑖𝑎
+ 𝑖𝑎 𝑅
Vi 𝑑𝑡
𝑑𝑖𝑏
Cf 𝑉𝑖𝑏 − 𝑉𝑔𝑏 = 𝐿 + 𝑖𝑏 𝑅 (8)
𝑑𝑡
𝑑𝑖𝑐
{ 𝑉𝑖𝑐 − 𝑉𝑔𝑐 = 𝐿 𝑑𝑡 + 𝑖𝑐 𝑅
Fig. 6. Per-phase equivalent circuit of LCL filter. The 3-phase parameters are transferred to the 2-phase by
using Clark transformation (i.e., abc to αβ0) for reducing the
The grid inductance ‘Lg’ is given as; number control variable. Then equation (9) can be written as,
𝐿𝑔 = 𝑟 ∗ 𝐿𝑖 & 𝐿 𝑇𝑜𝑡𝑎𝑙 = 𝐿𝑔 + 𝐿𝑖 (5) 𝑉𝑖𝛼 − 𝑉𝑔𝛼 = 𝐿
𝑑𝑖𝑎
+ 𝑖𝛼 𝑅
𝑑𝑡
{ (9)
The ratio of grid to inverter side inductance, ‘r’, is given 𝑉𝑖𝛽 − 𝑉𝑔𝛽 = 𝐿
𝑑𝑖𝛽
+ 𝑖𝛽 𝑅
as 0.6 to 1. The choice of ‘r’ affects the ripple sensitivity 𝑑𝑡
attenuation at a specific frequency. The instantaneous power (i.e., P and Q) equations in the
The reactive power absorption is set to 5% of stationary reference frame (SRF) ‘αβ0’ is given as,
nominal/rated power available (Sn), and the filter capacitor 3
𝑃 = [(𝑣𝑔𝛼 𝑖𝛼 + 𝑣𝑔𝛽 𝑖𝛽 )]
value is constrained by the reduction in power factor at rated { 2
(10)
3
power. [13]. The filter capacitor ‘Cf’ is given as; 𝑄 = [(𝑣𝑔𝛽 𝑖𝛼 − 𝑣𝑔𝛼 𝑖𝛽 )]
2
𝑉𝑛2
𝑄= 1 = 0.05 ∗ 𝑆𝑛 Differentiating equation (10), the dynamic equations obtained
{ 𝜔∗𝐶𝑓
(6) as,
0.05∗𝑆𝑛
𝐶𝑓 = = 0.05 ∗ 𝐶𝑏 𝑑𝑃 3 𝑑𝑖𝛼 𝑑𝑣𝑔𝛼 𝑑𝑖𝛽 𝑑𝑣𝑔𝛽
𝜔∗𝑉𝑛2 = {𝑣𝑔𝛼 + 𝑖𝛼 + 𝑣𝑔𝛽 + 𝑖𝛽 }
𝑑𝑡 2 𝑑𝑡 𝑑𝑡 𝑑𝑡 𝑑𝑡
1 𝑉𝑛2
{𝑑𝑄 3 𝑑𝑖𝛼 𝑑𝑣𝑔𝛽 𝑑𝑖𝛽 𝑑𝑣𝑔𝛼
(11)
Here; 𝐶𝑏 = , 𝑍𝑏 = , ‘ꞷ’ (rad/sec) is line frequency, Zb = {𝑣𝑔𝛽 + 𝑖𝛼 − 𝑣𝑔𝛼 + 𝑖𝛽 }
𝜔∗𝑍𝑏 𝑆𝑛 𝑑𝑡 2 𝑑𝑡 𝑑𝑡 𝑑𝑡 𝑑𝑡
and Cb are base impedance and base capacitor respectively. For simplifying the dynamic equations, considering a stiff
The damping resistance ‘Rd’ is grid, the PCC voltage in stationary αβ0 frame is given as,
1 𝐿 +𝐿𝑔 𝑑𝑣𝑔𝛼
𝑅𝑑 = Here; 𝜔0 = √ 𝑖 (7) 𝑣𝑔𝛼 = 𝑉𝑔 𝑐𝑜𝑠(𝜔𝑡) , = −𝜔𝑉𝑔 𝑠𝑖𝑛(𝜔𝑡) = − 𝜔𝑣𝑔𝛽
3∗𝜔0 ∗𝐶𝑓 𝐿𝐿 𝑖 𝑔 𝐶𝑓 𝑑𝑡
{ 𝑑𝑣𝛽 (12)
Here, ‘ω0’ (rad/sec) = resonance frequency of the LCL 𝑣𝑔𝛽 = 𝑉𝑔 𝑠𝑖𝑛(𝜔𝑡) ,
𝑑𝑡
= 𝜔𝑉𝑔 𝑐𝑜𝑠(𝜔𝑡) = 𝜔𝑣𝑔𝛼
filter. To minimize the magnitude of the spike during damping
and improve the system response time with minimal power Where, ‘Vg’ is the peak value of PCC voltage.
losses, the value of ‘Rd’ must be determined at the resonance 𝑉𝑔 = √𝑣𝑔𝛼 2 + 𝑣𝑔𝛽 2 (13)
frequency. The LCL filter parameters from equations (3) to (7)
are Li = 2.5 mH, Lg = 2.1 mH, Cf = 7.95 μF, and Rd = 4 Ω. By solving equations (9), (10), (11), (12), and (13) the
dynamic power equations are obtained as,
IV. MATHEMATICAL MODELING OF VOLTAGE
𝑑𝑃 𝑅 3
MODULATED DIRECT POWER CONTROL (VM-DPC) = − 𝑃 − 𝜔𝑄 + (𝑣𝑔𝛼 ∗ 𝑣𝑖𝛼 + 𝑣𝑔𝛽 ∗ 𝑣𝑖𝛽 − 𝑉𝑔 2 )
The VM-DPC control technique contains a PI-controller { 𝑑𝑡 𝑑𝑄
𝐿
𝑅
2𝐿
3 (14)
with the decoupled algorithm. The VM-DPC method = − 𝑄 + 𝜔𝑃 + (𝑣𝑔𝛽 ∗ 𝑣𝑖𝛼 − 𝑣𝑔𝛼 ∗ 𝑣𝑖𝛽 )
𝑑𝑡 𝐿 2𝐿
combines the properties of DQ and DPC control techniques The dynamics of instantaneous real and reactive power in
[14]. The active, and reactive power errors are fed to the PI- an SRF are represented by equation (14). It is a time-varying
controller. Fig. 7 depicts the pre-phase equivalent circuit multiple-inputs multiple-outputs (MIMO) system. The MIMO
diagram of grid-integrated MLI. The modeled equations of is switching to a SISO system and taking ‘uP’ and ‘uQ’ to be
grid- integrated MLI through an equivalent inductance considered as control inputs.
‘L=Li+Lg’, and equivalent resistance ‘R’. The PLL-Less VM-
DPC has two loops; the outer real and, reactive power loops 𝑢𝑃 = (𝑣𝑔𝛼 ∗ 𝑣𝑖𝛼 + 𝑣𝑔𝛽 ∗ 𝑣𝑖𝛽 )
use PI-controllers to produce the reference dq currents, { (15)
𝑢𝑄 = (𝑣𝑔𝛽 ∗ 𝑣𝑖𝛼 − 𝑣𝑔𝛼 ∗ 𝑣𝑖𝛽 )
respectively, and the inner closed loop uses PI-controllers to
control the currents to produce the reference voltage for The ‘viα’ and ‘viβ’ are the modulating signal inputs. It finds out
producing the appropriately controlled signals. from equation (16),

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 𝑣𝑔𝛼 ∗𝑢𝑃 +𝑣𝑔𝛽∗𝑢𝑄 +𝑉𝑔 2 𝑣𝑔𝛼 There are two inputs given in this controller iqref and idref,
𝑣𝑖𝛼 = which is active and reactive power control, the controller
𝑉𝑔 2
{ (16) equation is [15]
𝑣𝑔𝛽∗𝑢𝑃 −𝑣𝑔𝛼 ∗𝑢𝑄 +𝑉𝑔 2 𝑣𝑔𝛽
𝑣𝑖𝛽 = 𝐾𝑖𝑝
𝑉𝑔 2 𝑖𝑑𝑟𝑒𝑓 = (𝑃𝑟𝑒𝑓 − 𝑃)(𝐾𝑝𝑝 + )
𝑆
{ (23)
From equation (14), and (15) can be written as, 𝑖𝑞𝑟𝑒𝑓 = (𝑄𝑟𝑒𝑓 − 𝑄)(𝐾𝑝𝑞 +
𝐾𝑖𝑞
)
𝑆
𝑑𝑃 𝑅 3
= − 𝑃 − 𝜔𝑄 + (𝑢𝑃 − 𝑉𝑔 2 ) The Kpp, Kip, and Kpq, Kiq are PI-controller gains for the real
{ 𝑑𝑡 𝑑𝑄
𝐿
𝑅
2𝐿
3 (17) and reactive power control loop in the VM-DPC control
= − 𝑄 + 𝜔𝑃 + 𝑢𝑄
𝑑𝑡 𝐿 2𝐿 technique as shown in Fig. 8.
The VM-DPC control technique is directly derived from V. SIMULATION RESULTS AND ANALYSIS
the vector current control method, however, direct power is
considered here, an instant of currents. The transient and The MATLAB/ Simulink platform is used to produce the
steady-state behaviors and tracking performance of the VM- simulation results for the proposed work. The parameters of
DPC control is perfect. The block diagram of derived the grid-tied three-phase, nine-level MLI are considered in
controller equations is shown in Fig. 8. The equations (12), Table III. The PI-controller of VM-DPC PLL-Less control
and (15) can be written as; (i.e., Kp and Ki) are obtained by using the pole-zero
cancellation method [16]. The parameters of the outer real and
𝑢𝑃 𝑐𝑜𝑠(𝜔𝑡) 𝑠𝑖𝑛(𝜔𝑡) 𝑣𝑖𝛼 𝑢𝑑 reactive power control loop and inner control loop
[𝑢 ] = 𝑉𝑔 [ ] [ ] = 𝑉𝑔 [−𝑢 ] (18)
𝑄 𝑠𝑖𝑛(𝜔𝑡) −𝑐𝑜𝑠(𝜔𝑡) 𝑣𝑖𝛽 𝑞 (Decoupling algorithm) for VM-DPC are shown in Table IV.
Here, ud and uq are the MLI output voltage components in The grid- integrated MLI with VM-DPC control technique is
synchronous reference ‘dq0’ frame. This ud and uq are examined under various cases via a simulation study.
transformed to stationary frame ‘αβ0’, which is converting A. Grid-integrated MLI with fixed Load Demand
them to abc frame (ua, ub, and uc), used as reference signals
The dynamic response for PLL-Less VM-DPC of the grid-
for the LSPWM. The generated pulses control the switching
tied MLI due to variations in Pref, Pactual, and Qref, Qactual are
pattern of the proposed MLI.
considered under constant load demand. The connected load
Active Power Control at PCC is 8.5 kW and 6.5 kVAr, and simulation results for this
P Kpp circumstance are depicted in Fig. 9.
Pref -
+ +
+ TABLE III. GRID-INTEGRATED TABLE IV. PI-
Kip 1
idref Voltage Modulated Direct Power Control
MLI & LCL FILTER PARAMETERS CONTROLLER PARAMETERS
S
OF ACTIVE, REACTIVE AND
ud
Pg ˣ igd -
+
Kpd +
Kid
+
+ uα αβ0
Parameters Values DECOUPLING ALGORITHM
÷ S ua Vdc Vdc1 =246 V,
S1
Vgα Vgβ ud uα Vdc2 =82 V Parameters Values
ωL 1 ub S2
1.5Vgd Vgd
= Vl-l 400 V Kpp 1
Vgβ -Vgα uq uβ S3
ωL S4 f 50 Hz Kip 10
uβ uc Cf 7.95 µF
÷ Kiq -
S5 Kpq 5
Qg - Kpq+ + abc
LSPWM Li, Lg 2.5 mH, 2.1 mH Kiq 50
ˣ igq + S uq Rd 4Ω Kp_Decoupling 0.8
Kpr iqref fcr 5 kHz
Qref
+ Sbase 15 kVA Ki_Decoupling 600
+
- +
Kir 1
Q S
Case-I Case-II Case-III Case-IV
Qref , Qref_actual (KVAR)
Pref , Pref_actual (KW) &

Reactive Power Control

Qactual
Fig. 8. Block diagram of voltage modulated direct power control.
Qref
The dynamics equations of instantaneous real and reactive
power in synchronous reference dq-frame are calculated as; Pref Pactual
3
𝑃𝑔 = (𝑣𝑔𝑑 𝑖𝑔𝑑 + 𝑣𝑔𝑞 𝑖𝑔𝑞 )
2
{ 3 (19) (a) Pload
𝑄𝑔 = (𝑣𝑔𝑞 𝑖𝑔𝑑 − 𝑣𝑔𝑑 𝑖𝑔𝑞 )
2
Qgrid, Qload (KVAR)
Pgrid, Pload (KW) &

In the dq0-reference frame, the instantaneous voltage will Qload Pgrid

coincide with the d-axis (i.e., Vgq= 0). Hence, Pg and Qg
generated by the MLI can be calculated as;
3 3 Qgrid
𝑃𝑔 = 𝑣𝑔𝑑 𝑖𝑔𝑑 & 𝑄𝑔 = (−𝑣𝑔𝑑 )𝑖𝑔𝑞 (20)
2 2

Here, Vgq =Vg, Pg and Qg are same as ‘P’ and ‘Q’ respectively. (b) Time (Sec)
𝑑𝑝 3 𝑑𝑖𝑔𝑑 𝑑𝑄 3 𝑑𝑖𝑔𝑑
= (𝑉𝑔 )& = (−𝑉𝑔 ) (21) Fig. 9. Dynamic response of (a) Pref, Pactual, Qref and Qactual (b) Pgrid, Qgrid,
𝑑𝑡 2 𝑑𝑡 𝑑𝑡 2 𝑑𝑡
Pload and Qload.
By equating and solving equations (17), (18), and (21)
𝑑𝑖𝑔𝑑 𝑅 1
In Case-I; The MLI is delivering the reference real and
𝑑𝑡
= − 𝑖𝑔𝑑 − 𝜔𝑖𝑔𝑞 + (𝑢𝑑 − 𝑉𝑔 )
𝐿 𝐿
reactive power as, Pref = 7.5 kW and Qref = 13 kVAr to the PCC
{ 𝑑𝑖𝑔𝑞 𝑅 1
(22) respectively during 0 to 0.5 sec, then the MLI current (ia) is
= − 𝑖𝑔𝑞 + 𝜔𝑖𝑔𝑑 + 𝑢𝑞 lagging by 600 from PCC/MLI phase voltage (via/vga) as shown
𝑑𝑡 𝐿 𝐿

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in Fig. 10. The Pgrid = 1 kW and Qgrid = -6.5 kVAr to full fill
the load demand at PCC.
In Case-II; The active and reactive power is increased as
Pref = 10 kW and Qref =11.20 kVAr to the PCC respectively
during 0.5 to 1.0 sec, then the phase difference between ia and
via/vga is 480 lag. The Pgrid = -1.5 kW and Qgrid = - 4.7 kVAr to
full fill the load demand.
In Case-III; The real and reactive power injecting (i.e., Pref
= 10.61 kW and Qref = 10.61 kVAr) to the PCC during 1 to 1.5
sec. The ia is lagging by 450 from via/vga. The Pgrid = -2.11 kW
and Qgrid = - 4.11 kVAr to full fill the load demand.
In Case-IV; the MLI is delivering only real power (i.e., Pref
= 15 kW and Qref = 0) to PCC during 1.5 to 2.0 sec, the
remaining power from MLI as -6.5 kW will deliver to the grid
and the grid will supply (Qload -Qref) as, 6.5 kVAr to load. The
ia and via/vga are in phase with each other.
-7.2 kVAr to full fill the load demand (i.e., Pload = 8 kW, Qload
= 4 kVAr).
In Case-III; The MLI is delivering the active and reactive
power as, Pref = 10.60 kW and Qref = 10.60 kVAr to the PCC
respectively during 1 to 1.5 sec. The Pgrid = 1.4 kW and Qgrid
= -2.6 kVAr to full fill the load demand (i.e., Pload = 12 kW,
Qload = 8 kVAr).
In Case-IV; the Pref = 15 kW and Qref = 0, the power from
MLI i.e., 1 kW will deliver to the grid and the grid will supply
(Qref -Qload) as, 9 kVAr to load (i.e., Pload = 14 kW, Qload = 9
kVAr) during 1.5 to 2.0 sec.
By observing all cases; it is determined that the DC side of
the converter is operating at its maximum real power capacity.
The observations for all cases under variations in Pref, Qref,
Pload, and Qload are mentioned in Table V.

Qref , Qref_actual (KVAR)

Case-I Case-II Case-III Case-IV

Pref , Pref_actual (KW) &

By observing all cases; it is concluded that the maximum
available real power at the DC end of the converter is utilized. Qactual
The observations for all cases due to The variations in Pref and
Qref at constant load are observed for all cases in Table V. Qref
Case-I Case-II Case-III Case-IV Pactual
Via Ia*4
Via (V) & Ia (A)

Pref

(a)
Qgrid, Qload (KVAR)
Pgrid, Pload (KW) &

Pload
(a) Qload
Vga Ia*4 Pgrid
Vga (V) & Ia (A)

Qgrid

(b) Time (Sec)

(b) Fig. 11. Dynamic response of (a) Pref, Pactual, Qref and Qactual (b) Pgrid, Qgrid,
Vga Iga*10 Pload and Qload.

Case-I Case-II Case-III Case-IV

Via Ia*4
Via (V) & Ia (A)
Vga (V) & Iag (A)

(a)
Vga
Vga (V) & Ia (A)

Ia*4

(c) Time (Sec)

Fig. 10. Dynamic response of (a) Via & Ia (b) Vga & Ia (c) Vga & Iga.

B. Grid-integrated MLI with variable Pload, Qload, Pref & Qref (b)
Vga Iga*10
The dynamic response for PLL-Less VM-DPC of the grid-
tied MLI due to variations in Pref, Pactual, Qref, Qactual, Pload, and
Qload are considered. The variable loads are connected at PCC,
for this condition simulation results as shown in Fig. 11. The
phase difference between ia and via/vga due to different input
Vga (V) & Iag (A)

real and reactive power (Pref, Qref) are shown in Fig. 12.
In Case-I; The MLI is delivering the reference real and
reactive power as, Pref = 7.5 kW and Qref = 13 kVAr to the PCC
respectively during 0 to 0.5 sec. The Pgrid = -2.5 kW and Qgrid (c)
= -10 kVAr to full fill the load demand (i.e., Pload = 5 kW, Qload Time (Sec)

= 3 kVAr) at PCC. Fig. 12. Dynamic response of (a) Via & Ia (b) Vga & Ia (c) Vga & Iga.
In Case-II; The MLI is delivering the active and reactive
power as, Pref = 10 kW and Qref = 11.20 kVAr to the PCC The analysis of total harmonic distortion for line current
respectively during 0.5 to 1 sec. The Pgrid = -2 kW and Qgrid = and MLI terminal line voltage for grid-integrated three-phase,

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