Impact of Reverse Gate Oxide Stacking on Gate All

Around Tunnel FET for High Frequency Analog

and RF Applications
Amit Das Binod Kumar Kanaujia
2020 IEEE 17th India Council International Conference (INDICON) | 978-1-7281-6916-3/20/$31.00 ©2020 IEEE | DOI: 10.1109/INDICON49873.2020.9342175

School of Computational and Integrative Sciences, School of Computational and Integrative Sciences,
Jawaharlal Nehru University, Jawaharlal Nehru University,
New Delhi-110067, India. New Delhi-110067, India.
amitofficial7492@gmail.com bkkanaujia@yahoo.co.in

Vandana Nath Sonam Rewari R. S. Gupta

University School Of Information and Department of Electronics and Department of Electronics and
Communication Technology, Communication Engineering, Communication Engineering,
Guru Gobind Singh Indraprastha Delhi Technological University, Maharaja Agrasen Institute of
University, New Delhi-110042, India. Technology,
New Delhi-110078, India. rewarisonam@gmail.com New Delhi-110086, India.
vandanausit@gmail.com rsgupta1943@gmail.com

Abstract—We have studied the impact of the reverse gate
oxide stacking technique on a typical Gate All Around Tunnel
Field Effect Transistor (GAA TFET). For this, we have
compared it’s performance with the conventional GAA TFET.
By reverse gate oxide stacking, we mean that it is a gate oxide
stacking technique in which a high-k dielectric constant oxide
(k1) is just fabricated above the channel and another oxide
layer with a low-k dielectric constant value (k2) is formed just
above the previous oxide layer where k1>k2. This significantly
improves the device performance. In this paper, DC and AC
analysis has been done for both the structures and a detailed
comparison has been made for both the structures to
demonstrate the usability and efficacy of the proposed reverse
gate oxide stacking technique. Various AC performance
parameters have been analysed for the proposed reverse gate
oxide stacking on the GAA TFET.
Keywords— Ambipolarity, Band to Band Tunnelling, Gate
All Around Tunnel Field Effect Transistor (GAA TFET), Gate
Induced Drain Leakage, Metal Oxide Semi-Conductor Field
Effect Transistor (MOSFET), Reverse Gate Oxide Stacking and
Subthreshold Slope (SS).
I. INTRODUCTION
Tunnel Field-Effect Transistor [1] is the greatest-
engineered devices in the field of FET devices. TFET
devices came into the existence to overcome the ultra
scaling limitations of the MOSFET devices. Various short
channel effects such as punch-through, gate induced drain
leakage (GIDL), high subthreshold slope, high threshold
voltage and a poor high-frequency response became
apparent in different MOSFET devices due to their
continuous scaling. These shortcomings cannot be removed
by using the semiconductors having lower energy band-gap
energy or some novel structures using multiple gates
because the conventional MOSFET uses the thermionic
978-1-7281-6916-3/20/$31.00 ©2020 IEEE
emission as the carrier transport mechanism. Thus, to
overcome the various shortcomings of the conventional
MOSFET [2] device, a new device was proposed and came
into the picture, i.e. TUNNEL FIELD EFFECT
TRANSISTOR (TFET). The carrier transport mechanism of
TFET uses band to band tunnelling and also the
subthreshold slope (SS) of this device can go below
60mv/decade [3]. The band to band tunnelling in these
devices is due to the extremely thin depletion layer at the
source-channel and drain-channel interface arising due to
the extremely highly doped source and the drain which
allows the charge carriers to directly tunnel from the source
to drain instead of overcoming the potential barrier. This
also leads to lowering of on-state current. High threshold
voltage and ambipolar conduction are the few limitations of
TFET devices. Now, the main challenge for the engineers
was to boost the low on-state current without degrading the
other device parameters. Till now, many variants for the
TFET have been proposed to overcome the various
shortcomings. Variants such as TFET with multiple gates
[4,5] and high gate oxide dielectric or a TFET with a thin
silicon body were proposed to boost its on-state current.
Other variants of TFET with asymmetric drain-source
doping or TFET with an underlap gate were proposed to
overcome its ambipolarity problem. Ambipolarity is the
conduction arising because of both electrons and holes
which are predominant in the TFET devices because here
doping of the source and the drain are not of the same type
(p-type/n-type) which gives rise to the ambipolar
conduction. This ambipolar behaviour is highly undesirable
in devices because it increases the noise effect and decreases
the noise immunity in our FET devices. On the other hand,
researchers are concentrating on using high-k gate dielectric
material as gate oxide to solve the low on-state current (ION)

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 problem of TFET. Using a lower band gap material for the
construction of TFET or junctionless TFET devices had
shown a great improvement in switching behaviour and low
parasitic capacitance at lower voltages [6]. These parasitic
or junction capacitance limits the device frequency response
which affects the device RF performance. The low band-gap
material engineering had shown a great improvement in
switching behaviour and a low capacitance at lower
voltages. Study shows that using graphene as the alternative
material for the channel can drastically increase the ratio of
on-current and off-current. A new geometry for TFET was
also proposed-Gate All Around (GAA) [7] which further
improves the device characteristics. The second geometry
feature involves the gate oxide stacking technique. Both
these geometries improve the device overall performance.
Moreover, observations show that a TFET with a gate oxide
stacking and source delta doping [8] can significantly
improve the subthreshold slope (SS) characteristics of any
device. This paper concentrates meticulously on the reverse
gate oxide stacking technique on GAA TFET and analysed Fig. 1(b). Cut-plane view(two-dimensonal) of a typical GAA TFET.
its DC & AC behaviour for analog and RF applications. The
latest version of ATLAS SILVACO TCAD software has TABLE I. STRUCTURAL PARAMETERS OF DEVICES
been used for analyzing and simulation [9].
DEVICE PARAMETERS
II. STRUCTURAL DESCRIPTION AND SOFTWARE
DESCRIPTION
The 3D (three-dimensional) view and the cross-sectional PARAMETERS VALUES
(cut plane) view of a typical GAA TFET has been picturized
in fig. 1(a) and fig. 1(b) respectively. Similarly, the 3D Channel Radius (Rch) 10 nm
(three-dimensional) view and the cut plane view of a typical Channel Length (Lch) 50 nm
GAA TFET with the reverse gate oxide stacking has been
picturized in fig. 2(a) and fig. 2(b) respectively. The 3D Oxide Dielectric Constant (k) 3.9/21
structure shows the cylindrical structure of both the devices
Source Doping (NA) 1020 cm-3
whereas the cross-sectional view corresponds to the cut
plane view of both the structures. Channel Thickness (tch) 20 nm

Oxide Thickness
02 nm
(individual layer)

Channel Doping 1016 cm-3

Electrode Length 01 nm

Source Radius (RS) 10 nm

Drain Radius (RD) 10 nm

Gate Work Function (ΦGate) 4.4 ev

Drain Doping (ND) 1018 cm-3

Silicon has been used as a base material for the

Fig. 1(a). 3D (three-dimensional) view of a typical GAA TFET.
construction of both the devices and can be considered as a
homojunction device because the semiconductor material
used for the fabrication of source, channel and drain is same.
The individual thickness or the depth of any gate oxide layer
used is 2nm for both the simulated devices. Value of the
common gate oxide layer has lower dielectric constant value

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of k=3.9 (low-k value) and that of the other layer has higher
dielectric constant value of k=21(high-k value). In the
reverse gate oxide stacking, the oxide layer having higher
dielectric constant value is kept near to the channel while
the oxide layer having lower dielectric constant value is kept
near to the gate. The thickness of each electrode is kept
1nm. The permittivity of the SiO2 layer is 3.9 whereas the
permittivity of HfO2 is 21. The channel length (LCh) taken
under consideration is 50 nm in length. The radius of the
channel taken into consideration for the simulation purpose
is 10 nm. Radius of the drain and source part is also 10 nm
with a depth (length) of 10 nm.
Fig. 2(a). 3D (three-dimensional) view of the GAA TFET with the reverse
gate oxide stacking.
Fig. 2(b). Cut-plane view(two-dimensonal) of the GAA TFET with the
reverse gate oxide stacking.
Table 1 summarizes overall framework for both variants
in this simulation work. The channel is uniformly doped in
both the devices. The doping level of the source is higher
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than that of the drain. This has been done to suppress the
ambipolar behavior which is inherent in any TFET device.
Doping of the channel is kept low as compared to the source
which has been done to increase the drain current. The latest
version of ATLAS SILVACO TCAD software has been
used for analyzing and simulation. Generation model that
has been used here is BBT.Kl proposed by Klaassen and this
model includes both direct and indirect transitions. This is a
localized model which is based upon tunneling from band-
to-band. The numerical method used here to analyze the
complicated mesh equations is based upon Newton-Gummel
method.
III. GRAPHS AND RESULT DISCUSSION
This section describes the DC as well as AC
performance and analysis of both the variants. Fig. 3
graphically visualizes the drain current (IDS) with the
variable potential of drain terminal (VDS) at a constant
potential of the gate terminal (VGS=0.5 V) whereas fig. 4
graphically visualizes the drain current with the variable
potential of gate terminal at a constant potential of the drain
terminal (VDS=1 V).
Fig. 3. Drain current (IDS) vs the potential of drain terminal (VDS) in both
the variants.
In case of fig. 3, it has to be keeping in mind that the
selection of gate voltage is important and a slight variation
in the gate voltage can affect the output characteristics. We
know that the drain current is dependent on the overdrive
voltage and this overdrive voltage reckon on the potential of
gate terminal (VGS) and the threshold voltage (Vt). So,
selection of gate potential will ostentatiously affect the drain
current since this gate voltage is responsible for the channel
formation in the GAA TFET device. In case of fig. 4, the
potential of drain terminal highly affects the movement of
charge carrier flowing across the channel. The improved on-
current or drain current is a result due to increased overdrive
voltage which is affected by the capacitive stacking. The
stacking of gate oxide layer in reverse gate oxide stacking
technique allows the same amount of drain current at a
lower overdrive voltage. Thus, we can see an improvement
in the drain current due to both the gate voltage and the
drain voltage.
Fig. 4. Drain current (IDS) vs the potential of gate terminal (VGS) in both
the variants.
Fig. 5. Transconductance (gm) vs the potential of gate terminal (VGS) in
both the variants.
Fig. 5 shows the graphical variation of transconductance
for both the variants of TFET. Transconductance refers to
the ratio of on-current or output drain current or drain-to-
source current and input gate potential at any constant drain
voltage. It’s an important device metric for any device to
analyze the analog performance. The reverse gate stacking
definitely improves the basic features of the conventional
TFET. The drain current flowing in a typical TFET device is
directly proportional to device transconductance parameter.
This device transconductance parameter is directly
dependent upon the gate oxide capacitance. Now, adding a
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gate oxide layer with a high permeability allows us to obtain
a relatively high gate oxide capacitance keeping the same
thickness. So using a gate oxide layer with a high
permeability improves the effective gate oxide capacitance
which increases the device transconductance parameter.
This improvement in the value of device transconductance
value will thereby increase the drain current by a substantial
amount. The improvement in the value and the magnitude of
on-current or drain current will further improve the
transconductance value. A non zero drain current at VD=0V
in the ID-VD curve indicates the presence of leakage current
due to the short channel. Features like the drain current and
transconductance gets improved with the reverse gate
stacking technique which is always desirable since high
drain current and high transconductance gives high voltage
gain for RF and analog applications. A higher value of
transconductance ensures large transconductance-
generation-factor for any device which is defined as the
inherent competency of the device to transmogrify the
available DC power efficiently into output AC gain. Higher
drain current with minimum channel resistance is always
needed for a faithful amplification process since minimum
channel resistance enables less hindrance to charge carriers.
This minimum channel resistance or on-resistance improves
the drain current in the device and a high current can be seen
flowing across the channel. The reverse gate oxide stacking
technique in GAA TFET helps in minimizing the channel
resistance which is evident in the fig. 3, 4 and 5.
Fig. 6. Comparison of the subthreshold slope (SS) for both the variants.
Fig. 6 and fig. 7 graphically show the column graph
comparison of the subthreshold slope and ION/IOFF ratio for
both the variants. Lower sub-threshold slope (SS) leads to
low power consumption which is advantageous in low
power electronics and a higher ION/IOFF ratio is desirable for
better switching action and high frequency applications. A
low subthreshold slope always gives a high value of drain
current at low value of gate voltage. The reverse gate oxide
stacking increases the SS by a small value with a fractional
change less than 0.06 which can be neglected, but the high k
dielectric leads to the increment of the ION/IOFF ratio which
indicates high switching speed (needed in switching action
for analog applications). ION current is basically the drain
current that is flowing across the channel in both the
devices. The reverse gate oxide stacking technique in GAA
TFET improves the drain current which ultimately improves
the ION/IOFF ratio of the device.
Fig. 7. Comparison of the on-current (ION) and off-current ratio (IOFF) for
both the variants.
Fig. 8. Variation of the cut-off frequency (fτ) with the potential of gate
terminal (VGS) in GAA TFET and GAA TFET with reverse gate stacking
technique.
Fig. 8 shows the graphical variation of cut-off frequency
(fτ) or 3-dB frequency for GAA TFET and GAA TFET with
the reverse gate oxide stacking [8-11]. Cut-off frequency
limits the high frequency operation of any device, so a high
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cut-off frequency is always desirable. A larger cut-off
frequency indicates that the device can be easily used for
wideband applications. And a GAA TFET with the reverse
gate oxide stacking gives a high on-current, a high ION/IOFF
ratio and a high 3-dB or cut-off frequency when compared
to the conventional structure. The cut-off frequency of a
GAA TFET is limited by mainly its junction capacitance
and coupling capacitance. Also, this cut-off frequency
directly varies with the transconductance and the
transconductance improves with the reverse gate oxide
stacking technique. Compared to a single layer gate oxide, a
double layer gate oxide stacking is much better because of
the better electrical response offered by the device. The
equivalent gate oxide thickness is much lesser than the
actual gate oxide thickness in the case of reverse gate oxide
stacking.
Fig. 9. Variation of the transconductance frequency product (TFP) with the
potential of gate terminal (VGS) in GAA TFET and GAA TFET with
reverse gate oxide stacking technique.
Fig. 9 shows the graphical plot of the transconductance
frequency product (TFP) and the applied potential in the
gate terminal for both the device variants. TFP for any
device is defined as the product the transconductance and
the cut-off frequency and practically, its value must be high.
A high TFP is always desirable for analog and RF
applications and its value improve with the reverse gate
oxide stacking because of the increment in the value of
transconductance and cut-off frequency because of the
addition of the extra gate oxide layer with high permeability
above the body/channel of the variant. This additional layer
improves the current flowing in the device and the cut-off
frequency, which is responsible for the improvement in the
value of TFP. The selection as well as the placement of the
gate oxide layer plays a very vital part in influencing the
electrical characteristics and the analog performance. The
addition of a gate oxide layer in reverse gate oxide stacking
has improved the various device metrics of the conventional
GAA TFET and hence, this reverse gate oxide technique is
useful in improving the device overall performance.
IV. CONCLUSION
This paper proposes a very different reverse gate oxide
engineering technique for GAA TFET and the simulation
results are juxtaposed, compared and graphically analyzed
with the conventional structure of GAA TFET. DC and AC
analysis have been done to check its suitability for high
frequency analog and RF applications. The simulation
results implies that the addition of the reverse gate oxide
stacking in the conventional GAA TFET shows a
tremendous improvement in the analog performance (fτ,
TFP, ION/IOFF ratio). Other important parameters like
transconductance (gm) and drain current (ID) gets improved
with the reverse gate oxide stacking used in GAA TFET.
Although various parameters got improved but the value of
SS degrades by a fractional amount and even the drain
current does not get substantially improved with the reverse
gate oxide stacking. But considering the overall DC and AC
performance of both the devices, these simulation results
clearly indicates that the reverse gate oxide stacking is
useful in improving the RF analog behaviour of GAA
TFET. The result of this DC and AC analysis implies that
the reverse gate oxide stacking technique can be used with
GAA TFET for various practical analog applications like
amplifiers, data storage devices, high speed switching
circuits where switching speed must be high, low power
electronics , biosensing applications etc.
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