III-V / Si Heterojunction based Dual Material Stack

Gate Oxide TFETs for Low Power Applications

2021 7th International Conference on Signal Processing and Communication (ICSC) | 978-1-6654-2739-5/21/$31.00 ©2021 IEEE | DOI: 10.1109/ICSC53193.2021.9673374

Dharmender Kaushal Nigam

Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Jaypee Institute of Information Technology Jaypee Institute of Information Technology
Noida, India Noida, India
dharmender.nishad@gmail.com kaushal.nigam@jiit.ac.in

Satyendra Kumar
Department of Electronics and Communication Engineering
Jaypee Institute of Information Technology
Noida, India
satyendra.kumar@jiit.ac.in

Abstract—This article investigates the DC, analog/radio fre-
quency, and linearity performance parameters of various dual-
material stacked gate oxide hetero-junction tunnel field-effect
transistor (DMSGO-HTFET) structures using III-V materials
on the source and silicon in the channel and drain regions,
respectively, forming a hetero-junction at the source-channel
junction. In addition, a stacked gate oxide (SiO2 +Hf O2 ) with
workfunction engineering is used to improve the ON-state current
(ION ) of the device. In this regard, In0.53 Ga0.47 As-Si hetero-
junction based DMSGO-HTFET, GaSb-Si hetero-junction based
DMSGO-HTFET are analyzed using technology-computer aided
design (TCAD) simulations, and the performance is compared
with conventional all-Si DMSGO-TFET in terms of transfer
characteristics, output characteristics, transconductance (gm ),
cut-off frequency (fT ), gain-bandwidth product (GBP), transcon-
ductance frequency product (TFP), transit time (τ ), and linearity
performance parameters such as higher-order transconductance
(gm2 , gm3 ), second and third-order voltage intercept points
(VIP2, VIP3), third-order input-interception point (IIP3), and
inter-modulation-distortion (IMD3) are analyzed. This compara-
tive analysis reveals that GaSb-Si hetero-junction based DMSGO-
HTFET exhibits 294 % and 586 % increase in ION , 169 % and
543 % increase in gm , 162 % and 532 % increase in fT , 162 %
and 533 % increase in GBP as compared to In0.53 Ga0.47 As/Si
hetero-junction based DMSGO-HTFET and conventional all-
Si DMSGO-TFET respectively. The average subthreshold swing
(25.7 mV/decade) and also major improvements in linearity
performance parameters which ensures the proposed device is
suitable for low power switching and radio frequency applica-
tions.
keywords—Dual material, Stack gate oxide, Low band gap,
Hetero-junction, Workfunction
I. I NTRODUCTION
The tunnel field-effect transistors (TFETs) have attracted
much attention due to significantly lower sub-threshold swing
(SS) lower than 60 mV/decade compared to conventional
metal–oxide–semiconductor FETs (MOSFETs), lower temper-
ature dependency, immunity towards short channel effects
(SCEs), lower leakage current [1–6]. However, due to in-
adequate interband tunneling, the ON-state current of TFET
is lower than MOSFET, which prohibits its use for energy-
efficient switching and analog/radio frequency applications
[7,8]. To enhance the ON-state current, various device struc-
tures have been explored by the researchers, such as work-
function engineering [7-9], gate dielectric engineering [10,11],
electrically doped TFET [12,13], stacked gate oxide structure
[14,15], L-shaped TFET [16], pocket doped TFET [17], di-
electric pocket TFET [18], extended source TFET [19], gate
to source overlap [20]. These methods focused primarily on
tunneling width variation and a higher lateral electric field at
the source-channel interface to improve the tunneling current
and analog/radio frequency performance of the conventional
all-silicon TFET. However, due to their large bandgap (Eg )
and effective mass, conventional all-silicon TFET exhibits
a lower inter-band tunneling rate [21]. Therefore, hetero-
junction with low bandgap material in the source is a better
choice for improving the ON-state current. Table II shows
the lattice constants and low bandgap materials used for
hetero-junction formation in silicon channel-TFET [24]. In this
regard, various III-V hetero-junction structures based on low
bandgap materials such as Ge, InAs, InGaAs, InP, GaSb, and
GaAsSb in the source region have been investigated [22-30].
Furthermore, In0.53 Ga0.47 As-Si and GaSb-Si hetero TFETs
can be fabricated using the approach mentioned in [24, 30,
32].
The main limitation of III-V material-based TFETs is that
their OFF-state current is higher than the conventional all-Si-
based TFETs [3]. Hence, device structural engineering, along
with source material, has been used to improve the ON-state
current, subthreshold swing and decrease the IOF F of the de-
vice. In literature, the DC and radio frequency performance of
In0.53 Ga0.47 As-Si and GaSb-Si hetero-junction VTFETs are
investigated [17]. The stacked gate oxide with work function

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 engineering enhances the lateral electric field and improves
the DC and RF performance of the TFET [15]. Therefore, in
this work, the DC characteristics, analog/radio frequency, and
linearity performance of III-V / Si hetero-junction DMSGO-
HTFET structures are compared with all-Si DMSGO-TFET
and recent literature using the TCAD tool.
(a) (b)
(a)
(c)
Fig. 1: 2D structural view of (a) D1 [15], (b) D2 (c) D3
This paper is organized as follows: The structural, simula-
tion details and process flow are discussed in Section 2. Impact
of III-V /Si hetero-structure on DC, analog/radio frequency
and linearity performance parameters are presented in section
3. Lastly, the main findings of this work are concluded in
Section 4.
II. D EVICE STRUCTURE , PARAMETERS , SIMULATION
STRATEGY AND PROCESS FLOW
The Proposed hetero-junction TFET structure uses III-V
semiconductors in the source region and silicon in the chan-
nel and drain regions respectively, forming hetero-junction
at the source-channel junction. Fig. 1(a)-(c) illustrates the
2D structural views of all-Si DMSGO-TFET (say, D1),
In0.53 Ga0.47 As-Si hetero-junction DMSGO-HTFET (say,
D2), and GaSb-Si based hetero-junction DMSGO-HTFET
(say, D3) respectively. Table I presents the list of design
parameters and dimensions used in the simulation. The source
region doping (NA ) of 1×1020 cm−3 , the drain region doping
(ND ) of 5×1018 cm−3 is considered. The length of the stack
gate (LG ) is considered 50 nm with SiO2 layer thickness of
(0.8 nm) and Hf O2 oxide layer thickness of (1.2 nm) [15].
Further, the entire gate electrode is split into three segments
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labelled as tunnelling gate (M1 ), control gate (M2 ), and
auxiliary gate (M3 = M1 ) with respective segment lengths (L1 ,
L2 , L3 ) and segment work-functions (ϕ1 , ϕ2 , ϕ3 ). The control
gate work-function (ϕ2 ) is taken as 4.4 eV which corresponds
to molybdenum (Mo) material (4.36 eV - 4.95 eV). Tunneling
gate work-function (ϕ1 ) and auxiliary gate work-function (ϕ3 )
values taken as 4.0 eV which corresponds to aluminum (Al)
(4.0 eV - 4.26 eV) [8].
A. Simulation models
The performance of the proposed III-V / Si DMSGO-
HTFET is analyzed using TCAD simulations. For this, the
non-local BTBT model, which utilizes Wentzel-Kramers-
Brillouin (WKB) method is considered, for measuring tun-
neling probability across the junction. TAT.NLDEPTH model
is used to improve the results because lattice and thermal co-
efficient mismatch between two different materials can cause
defects in the hetero-junction. The Shockley-Read-Hall model
is enabled for taking into account the recombination effect.
The bandgap narrowing (BGN) model is used to account for
heavily doped concentrations in source and drain regions.
The proposed III-V / Si DMSGO-HTFET can be fabricated
using techniques similar to those reported earlier [9], [19].
Fig. 2(a)-(i) illustrates the fabrication process flow for the
proposed device. Fig. 2(a) depicts the formation of a thin
intrinsic silicon film, while Fig. 2(b) shows the p-i-n structure
formation using ion implantation. Then, SiO2 can be grown
on the p-i-n structure by oxidation process as illustrated in
Fig. 2(c). Then, Hf O2 layer is deposited, using atomic layer
deposition (ALD), as illustrated in Fig. 2(d). After that, as
shown in Fig. 2(e), the creation of the control gate can be done
using masking and metallization of Mo material. Additionally,
auxiliary and tunnel gates can also be metalized using the
self-aligned symmetrical spacer method, as shown in Fig. 2(f).
Next, selective etching can be done for electrode formation, as
indicated in Fig. 2(g). Similarly, the back gate can be formed,
as illustrated in Fig. 2(h). Lastly, Fig. 2(i) illustrates the
metallization of source and drain contacts using Mo material
as it provides the work-function ranges from 4.36 eV to 4.95
eV.
III. R ESULTS AND DISCUSSION
This section investigates the DC characteristics, ana-
log/radio frequency, and linearity performance parameters of
D1, D2 and D3.
A. DC characteristics
Fig. 3(a) and Fig. 3(b) illustrates the OFF state condition
(i.e. VGS = 0V) and ON-state condition (VGS = 1.0 V, and
VDS = 0.5 V) band diagrams of the three devices D1, D2, and
D3 respectively. Fig. 3(a) clearly illustrates that, in the OFF
state tunneling of electrons does not occur from the valence
band of the source to the conduction band of the channel
due to the nonalignment of energy bands in D1, D2, and
D3. However, in the ON state, applied positive VGS decreases
the tunneling width, allowing interband tunneling as illustrated
 TABLE I: List of device parameters used in simulation
Parameters Si InGaAs-Si GaSb-Si
Gate Length (LG ) 50 nm 50 nm 50 nm
SiO2 thickness (TSiO2 ) 0.8 nm 0.8 nm 0.8 nm
Hf O2 thickness (THf O2 ) 1.2 nm 1.2 nm 1.2 nm
Silicon Film Thickness (Tsi ) 10 nm 10 nm 10 nm
Channel doping (Nch ) 1×1017 cm−3 1×1017 cm−3 1×1017 cm−3
Source doping(p type) (NS ) 1×1020 cm−3 1×1020 cm−3 1×1020 cm−3
Drain doping(n type) (ND ) 5×1018 cm−3 5×1018 cm−3 5×1018 cm−3
Hf O2 dielectric constant (K) 25 25 25
Tunneling gate Length (L1 ) 10 nm 10 nm 10 nm
Control gate Length (L2 ) 25 nm 25 nm 25 nm
Auxiliary gate Length (L3 ) 15 nm 15 nm 15 nm
Tunneling gate work-function (ϕ1 ) 4.0 eV 4.0 eV 4.0 eV
Control gate work-function (ϕ2 ) 4.4 eV 4.4 eV 4.4 eV
Auxiliary gate work-function (ϕ3 ) 4.0 eV 4.0 eV 4.0 eV
Tunneling Mass of Hole in GaSb - - 0.4000
Tunneling Mass of Electron in GaSb - - 0.0410
Tunneling Mass of Hole in In0.53 Ga0.47 As - 0.457 -
Tunneling Mass of Electron in In0.53 Ga0.47 As - 0.0410 -
Tunneling Mass of hole in Silicon 0.24m0 0.24m0 0.24m0
Tunneling Mass of Electron in Silicon 0.20m0 0.20m0 0.20m0

TABLE II: Band gap and Lattice constant of III-V and IV mass of electrons in the source region of D2 and D3. Fig.
materials for hetero-junction formation with silicon at 300K 3(d) illustrates the IDS -VDS characteristics plot at VGS = 0.5
[24] V. From the figure, it has been noted that the drain current
Material Lattice constant Bandgap IDS rises initially and then saturates due to velocity saturation
as VDS increases from 0 to 0.4 V. The tunneling current
Si 5.43 A 1.12 eV
Ge 5.65 A 0.67 eV
does not change significantly beyond VDS = 0.4 V onwards,
In0.53 Ga0.47 As 5.87 A 0.74 eV hence the drain current remains constant. From the IDS -VGS
InAs 6.05 A 0.37 eV characteristics shown in Fig. 3(c) various device parameters
GaSb 6.09 A 0.69 eV
such as ION , ION /IOF F , SSavg and VT for the devices D1,
D2 and D3 are extracted and listed in Table III and plotted in
Fig 4. (a) and Fig. 4(b). The results in Fig 4. (a), Fig. 4(b)
in Fig. 3(b). The results also indicate that GaSb / Si hetero- and Table III shows that device D3 shows better performance
junction significantly decreases the tunneling barrier width at than D1 and D2 at the same biasing conditions.
the source junction resulting in an improved drain current after
a certain positive VGS . B. Analog/radio frequency Performance improvement
The inter-band tunneling probability of the carrier (TW KB ) This section investigates the analog/radio frequency (RF)
at the tunneling barrier is computed using Wentzel-Kramer- performance parameters such as the gm , parasitic capacitance
Brillouin (WKB) approximation [3,19]. (Cgs , Cgd ), fT , GBP, τ , and TFP of the devices D1, D2 and
 √ q  D3. Fig. 5(a) illustrates the gm variation with VGS for D1, D2
4λ 2m∗ Eg 3 and D3 respectively. The gm reflects the gain of the device,
TW KB ∝ exp −  (1)
3qh(Eg + ∆ϕ) a larger gm is useful for analog/radio frequency applications.
Moreover, gm plays a crucial role in attaining higher fT and
Where m∗ is the effective mass of an electron, q represents GBP values. The results also illustrate that D3 device attains
the electron charge, h represents Plank’s constant, Eg is the larger value of gm ( 1.38 mS/µm), whereas at the same biasing
effective bandgap, λ represents the tunneling width and ∆ϕ conditions D2 and D1 shows 0.51 mS/µm and 0.21 mS/µm
represents the energy overlap window where tunneling occurs. respectively.
From this approximation, it can be seen that, to increase the The Cgd and Cgs are also crucial analog/radio frequency
tunneling probability the band gap (Eg ), the effective mass performance evaluation parameters for any FET. Fig. 5(b)
(m*) of the carrier, and the tunneling barrier width (λ) should and (c) illustrates the comparative plots of the Cgs and Cgd
be minimized. Where Eg and m* are material-specific, λ is respectively, for D1, D2, and D3 devices. The above results
influenced by other factors such as device geometry, doping shows that the magnitude of Cgs is smaller than Cgd for all the
profiles, and gate capacitance. three devices D1, D2, and D3. Moreover, Cgd variation with
The IDS -VGS and IDS -VDS characteristics of the three gate voltage is negligible in all the three devices, whereas D3
devices D1, D2 and D3 are compared in Fig. 3(c) and Fig. has higher Cgs than D1 and D3.
3(d) respectively. Fig. 3(c) shows the drain current of D2 and The cut-off frequency (fT ) is considered as one of the
D3 devices are higher compared to D1 due to lower effective crucial parameters for the RF performance assessment of the

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 (a)
(f) 1.5
CB DMSGO-HTFET
OFF state
1.5
CB
DMSGO-HTFET ON state

VGS = 1.0 V,
1.0 VGS = 0 V, 1.0
Si Si
VDS = 0.5 V VDS = 0.5 V
InGaAs-Si InGaAs-Si

Energy (eV)
0.5 GaSb-Si 0.5
GaSb-Si

Energy (eV)
-
0.0 0.0 e Tunneling
VB VB
-
e Tunneling
-0.5 -0.5

-1.0 -1.0

(b) -1.5 -1.5

SOURCE DRAIN SOURCE DRAIN

(g) -2.0
0.00 0.02
CHANNEL

0.04 0.06 0.08 0.10

-2.0
0.00 0.02
CHANNEL

0.04 0.06 0.08 0.10

Position along channel (µm) Position along channel (µm)

(a) (b)
-3
10 9.0 0.30
DMSGO-HTFET

(A/µm)
V = 0.5 V

(µA/µm)
GS

(µA/µm)
-5
10 VDS = 0.5V 7.5 0.25

(c) 10
-7

6.0 0.20

DS

DS

DS
-9 Si

Drain current, I
10

Drain current, I

Drain current, I
InGaAs-Si 4.5 0.15

(h) 10
-11 GaSb-Si
Si

InGaAs-Si 0.10
3.0
-13
10 GaSb-Si

1.5 0.05
-15
10

0.00
-17 0.0
10
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0

Gate Voltage, V (V)

GS Drain Voltage, V (V)
DS

(d) (c)
(d)

Fig. 3: (a) Comparative OFF state band variation (b) ON

state band variation (c) IDS -VGS characteristics (d) IDS -VDS
characteristics for D1, D2, and D3 devices at 300K.
(i)

(e) decrease in gm because of mobility degradation [28]. The fT

Fig. 2: Fabrication process flow of III-V / Si based DMSGO-
HTFET (a) Intrinsic silicon growth, (b) Epitaxial growth of
p-i-n layers, (c) Oxidation to grow 0.8 nm thick SiO2 ,
(d) Atomic layer deposition to grow Hf O2 , (e) Control
gate deposition, (f) Auxiliary and tunnel gate deposition, (g)
Etching for metal gate electrode formation, (h) Back gate
formation, (i) Metallization and source and drain contacts.
device. It is the frequency at which the short-circuited current
gain becomes unity or 0(dB). The fT , is formulated using the
expression [26]:
gm
fT =
2π(Cgs + Cgd )
Since Cgs is smaller than Cgd for all the devices, and the
value of fT is dominated by gm and Cgd . Fig. 5(d) shows
D3 attains highest fT , and smallest for D1. Moreover, fT
increases initially with VGS , then starts to decrease after a
certain value of VGS after reaching the peak point due to
of all the three devices are presented in Table III.
The GBP is also one of the important parameter to consider
for RF performance assessment of the device at wide range of
applications. For a dc voltage gain of 10, GBP is formulated
as per the equation [11]:
gm
GBP = (3)
2π10Cgd
From the comparative plots shown in Fig. 6a, GBP of D3
is higher than D1 and D2 due to higher gm for D3 at the
same biasing conditions. Also, the GBP increases initially with
VGS due to an increase in transconductance (gm ) then starts
decreasing after reaching its peak point due to a decrease in
gm because of mobility degradation.
The TGF determines how quickly the current reaches a
specified transconductance value. Fig. 6(b) depicts the com-
parison of TGF variation with VGS . Higher TGF is observed in
DMSGO-DP-TFET at low VGS and decreases with increasing
VGS because IDS variation is small. The TGF is formulated
(2) by the expression [11]:
 
gm
T GF = (4)
IDS
TFP is another significant parameter to consider when
assessing the RF performance of the device. Devices with
higher TFP are preferred in moderate to high speed designs.

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 -3 14
10 10
1.80 0.24
DM SGO-HTFET VDS = 0.5 V DMSGO-HTFET
DMSGO-HTFET

(mS)
0.22
I VGS = 1.0 V 1.50
ON V = 0.5 V V = 0.5 V

Capacitance, Cgs(fF)
DS DS

m
I /I 0.20

Transconductance, g
ON OFF 1.20 Si
(A/µm)

OFF
Si-GaSb 0.18
0.90

I
Si-InGaAs
-4

/
13
10 10
0.16

ON
ON

Si
0.60

I
0.14 Si-GaSb
I

0.30 Si-InGaAs
0.12

0.00
0.10
(a)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
-5 12
10 10 Gate Voltage, V (V) Gate Voltage, V (V)
GS GS
Si InGaAs-Si GaSb-Si
(a) (b)

0.55
50
V 3.0 100
T
DMSGO-HTFET DMSGO-HTFET
0.50
Si
SS

Average SS, (mV/decade)

AVG 45 2.5
)

80 Si

Capacitance, Cgd(fF)
Si-GaSb
T
Threshold Voltage, ( V

0.45 Si-GaSb
Si-InGaAs
40 2.0
Si-InGaAs

(GH )
60

Z
0.40
1.5
35 V = 0.5 V

T
40 DS
0.35

f
1.0
VDS = 0.5V
30
0.30 20
0.5

25
0.25
0
0.0
(b) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.20 20
Gate Voltage, V (V) Gate Voltage, V (V)
Si InGaAs-Si GaSb-Si GS GS

(c)
(d)

Fig. 4: (a) Comparative ION and ION /IOF F variation (b) VT

and average Subthreshold swing variation for for D1, D2, and Fig. 5: (a) Comparative gm - VGS variation (b) Cgs - VGS
D3 at room temperature. variation (c) Cgd - VGS variation (d) fT - VGS variation for
for D1, D2, and D3 at room temperature.

Fig. 6(c) illustrates the comparative TFP variation with VGS

for all three devices. From the comparative results, it has been 
gm1

observed that D3 exhibits higher TFP due to high gm and fT V IP 2 = 4 × (7)
gm2
values. Furthermore, TFP increases initially with VGS due to
an increase in gm and fT , but, after a certain value of VGS , it
r
gm1
starts to decrease due to reduced transconductance (gm ) and V IP 3 = 24 × ( ) (8)
gm3
fT due to mobility degradation. The TFP is formulated using
the expression [11,18]. 9
IM D3 = [ × (V IP 3)2 × (gm3 )]2 × RS (9)

gm
 2
TFP = fT (5)
IDS
 
2 gm1
IIP 3 = × (10)
The transit time (τ ) is important parameter to evaluate the 3 gm3 × RS
time requirement to move the charge carriers from source to Fig. 7(a) illustrates the gm2 variation with VGS for D1, D2 and
drain. Therefore, it reports the speed of the device. Fig. 6(d) D3 devices. A device with higher gm2 and gm3 values at lower
shows the transit time variation with VGS . From the same VGS is said to have better linearity [16]. Fig. 7(a) illustrates
figure it has been observed that as VGS increases, τ decreases the peak point of gm2 is higher for D3 device at lower VGS
due to increase in fT . In addition, D3 has the shortest transit compared to D1 and D2. Fig. 7(b) illustrates the gm3 variation
time and better switching speed as compared to the other two with VGS for D1, D2 and D3 devices. Similar to gm2 , the
structures. The τ is formulated by using the expression [18] gm3 peak occurs at lower VGS for D3 in comparison with
1 D1 and D2 devices. This indicates that the proposed D3 has
τ= (6)
2π10fT better linearity followed by D2, and D1 respectively. Fig. 7(c)
illustrates the comparative plots for VIP2 variation with VGS at
C. Linearity Performance analysis VDS = 0.5 V. A higher VIP2 is needed for minimal distortion.
This section presents the linearity and distortion parameters Further, it has been noted that the VIP2 of D3 is higher than the
such as higher order transconductance (gm2 , gm3 ), VIP2, other two structures indicating better linearity and minimum
VIP3, IMD3, and IIP3 for D1, D2, and D3 devices. Where distortion. Fig. 7(d) shows the comparative VIP3 variation with
these parameters are explained in [15,22,31]. VGS at VDS = 0.5 V. It has been observed that VIP3 of D3 is

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 TABLE III: Comparison of DC, analog/RF parameters
Parameters Si (This Work∗ ) InGaAs-Si (This Work∗ ) GaSb-Si (This Work∗ ) Ref(17) Ref(16) Ref (11)
ION (A/µm) 4.8×10−5 8.34×10−5 3.29×10−4 2.06×10−5 1.9×10−6 1.85×10−5
IOF F (A/µm) 1.46×10−17 3.52×10−17 1.84 ×10−17 2.76×10−17 2×10−17 1.26 ×10−16
ION /IOF F 3.28×1012 2.37×1012 1.79 ×1013 7.5×1011 9.5×1010 1.46 ×1011
VT H (V) 0.45 0.47 0.25 0.31 0.65 0.7
SSavg (mV /decade) 45.3 49.7 25.7 26 79.8 40.44
gm (s) 2.1×10−4 5.13×10−4 1.38×10−3 66×10−6 7 ×10−6 7.4×10−5
fT (GHz) 13.2 31.8 83.6 46 0.7 0.17
GBP (GHz) 1.38 3.33 8.74 7 0.4 0.16
TFP (GHz) 59.1 196 350 550 - 500

10 450 4 15
DMSGO-HTFET VDS = 0.5 V
DMSGO-HTFET DMSGO-HTFET
DMSGO-HTFET
VDS = 0.5 V VDS = 0.5 V 10
400 Si VDS = 0.5 V
3
Si 5
8 Si InGaAs-Si
350 InGaAS-Si
(GHZ/V)

0
InGaAs-Si GaSb-Si 2 GaSb-Si

(mA/V )
(mA/V )
(GHZ)

3
2
300 -5
GaSb-Si
6
250 1 -10 Si

m2

m3
-15 InGaAS-Si
200
GBP

g
0 GaSb-Si
4 -20
TFP

150
-25
-1
100 -30
2

50 -2 -35
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

0 0 Gate Voltage, V (V) Gate Voltage, V

GS
(V)
GS

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 (a) (b)

Gate Voltage, V (V) Gate Voltage, V (V)

GS GS
10 5
(b)
(a) DMSGO-HTFET V
DS
= 0.5 V
DMSGO-HTFET
VDS = 0.5 V
8

2 Si 4
80 6
10
DMSGO-HTFET InGaAS-Si
DMSGO-HTFET
VDS = 0.5 V 4
Si
0 GaSb-Si
10 InGaAS-Si
)

VDS = 0.5 V 3

VIP3 (V)
VIP2 (V)

2
-1

(S )

GaSb-Si
-2 Si
(V

60 10 0
Si
Transit time,

InGaAs-Si 2
TGF = gm/IDS

-2
-4
InGaAs-Si 10
GaSb-Si -4

40 GaSb-Si 10
-6 1
-6

-8 -8
10
0
-10
-10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
20 10
Gate Voltage, V (V) Gate Voltage, V (V)
GS GS
-12
10
(c) (d)

-14
0 10
50 15
0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 DMSGO-HTFET DMSGO-HTFET

Gate Voltage, V (V) Gate Voltage, V (V) 0 0

GS
GS

(c) (d) -50 -15 VDS = 0.5 V

VDS = 0.5 V
IMD3 (dBm)

IIP3 (dBm)

-100 -30
Si Si

Fig. 6: (a) Comparative GBP - VGS variation (b) TFP - VGS -150
InGaAS-Si

GaSb-Si
-45
InGaAS-Si

GaSb-Si

variation (c) TGF - VGS variation (d) fT - VGS variation for -200 -60

D1, D2, and D3 at room temperature -250 -75

-300 -90
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

Gate Voltage, V (V) Gate Voltage, V (V)

GS GS

(e) (f)
higher than the other two structures indicating better linearity
and minimum distortion at lower VGS . IMD3 originates from
the non-linearity characteristics of IDS -VGS and seems to be a
Fig. 7: comparision of (a) gm2 - VGS variation (b) gm3 - VGS
distorting signal in wireless communication systems. Devices
variation (c) VIP2 variation with VGS (d) VIP3 variation with
with lower IMD3 values can have the ability to tolerate higher
VGS (e) IMD3 variation with VGS (f) IIP3 variation with VGS
signal distortion [31] . Fig. 7(e) shows the comparative IMD3
for D1, D2, and D3 at room temperature.
variation with VGS at VDS = 0.5 V. Further, IMD3 of D1 is
noted to be the smallest, indicating that the intermodulation-
distortion performance of D1 is the best of the above devices.
IV. C ONLUSION
The higher IIP3 value shows the device is more linear. Fig.
7(f) shows the comparative IIP3 variation with VGS at VDS In this work, the DC characteristics, analog / radio fre-
= 0.5 V. It has been observed that the IIP3 of D3 is higher, quency, and linearity performance of III-V / Si based hetero-
which indicates that D3 is more linear than D2 and D1. junction TFET structures such as, GaSb/Si based hetero-

335

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 junction DMSGO-HTFET, and In0.53 Ga0.47 As/Si based
hetero-junction DMSGO-HTFETs has been investigated us-
ing TCAD simulations. The performance of the proposed
hetero-junction TFETs are compared with conventional all-
Si DMSGO-TFET in terms of transfer characteristics, output
characteristics, gm , fT , GBP, TFP, and transit time (tau).
From the simulation study, it is noted that the proposed
device D3 exhibits lower SS (below 25.7 mV/ dec), lower
VT ( 0.25 V), higher ION /IOF F ratio (in the order of 1013 ),
higher gm (1.38×10−3 ), higher fT (83.6 GHz), and higher
GBP (8.74 GHz ) as compared to D1 and D2 devices. The
proposed hetero-junction TFETs also exhibit better linearity
performance as compared to the all-Si DMSGO-TFET and
recent literature shown in table III, which indicates the pro-
posed device outperforms compared to the recent literature,
making the proposed GaSb/Si based hetero-junction DMSGO-
HTFET suitable for low power switching and radio frequency
applications.
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