2021 Devices for Integrated Circuit (DevIC), 19-20 May, 2021, Kalyani, India 621

An SOI n-p-n Double Gate TFET for Low Power

Applications
Deepjyoti Deb Rupam Goswami Ratul Kr Baruah
Department of ECE, Tezpur University Department of ECE, Tezpur University Department of ECE, Tezpur University
Tezpur-784028, Assam India Tezpur-784028, Assam India Tezpur-784028, Assam India
deepjyotid82@gmail.com rup.gos@gmail.com rkbarua@gmail.com

Rajesh Saha
2021 Devices for Integrated Circuit (DevIC) | 978-1-7281-9955-9/20/$31.00 ©2021 IEEE | DOI: 10.1109/DevIC50843.2021.9455827

Kavindra Kandpal
Department of ECE, IIIT Allahabad Department of ECE, MNIT Jaipur,
Prayagraj, Uttar Pradesh 211015 Jaipur, Rajasthan 302017
kavindra@iiita.ac.in rajesh.ece@mnit.ac.in

Abstract— This article proposes a tunnel field effect
transistor (TFET) based on n-p-n silicon body with double gates,
one each over the two p-n junctions. The p-type source region is
elevated as compared to the two n-type drain regions in order to
create sufficient length for gate placement, and cover the
junction. Electrical parameters have been systematically
investigated through calibrated TCAD (technology computer
aided design) simulations with objectives to reduce the
ambipolar currents, and increase the ratio of on and off
currents. Gate-on-drain length is an important parameter to
control ambipolarity in the device, similar to gate-drain
underlap length in conventional TFETs. Sub-60 mV/dec
subthreshold swings, and drain current usually in order of tens
of μA/μm have been observed. Gate workfunction engineering
further shows the tuning of threshold voltage, and other
electrical parameters.
Keywords- SOI TFET, double gate, n-p-n, TCAD, BTBT
I. INTRODUCTION
The lookout for alternatives to metal oxide field effect
transistors (MOSFETs) for low power applications has been
met with a number of novel devices in the past two decades
[1]-[3]. Of such emerging devices which possess the promises
to counter effects of downscaling, tunnel field effect
transistors (TFETs) have acquired great attention due to their
ability to offer sub-kT/q subthreshold swing (SS) and low
leakage current [4]-[6]. The phenomenon of quantum
tunneling in TFETs as opposed to thermionic emission in
MOSFETs attributes negligible short channel effects to the
former. Most commonly a gated reverse-biased p-i-n
structure, TFETs come with drawbacks of low on-state current
( ), and acute ambipolarity. There have been many
architectures, and techniques proposed so far to tackle these
drawbacks. Of them, the double gate TFETs [7], gate-drain
underlap TFETs [8], p-n-p-n TFETs [9], halo-pocket TFETs
[10], heterojunction TFETs [11], and hetero-gate TFETs [12]
are some of the prominent ones.
This article proposes a TFET based on n-p-n structure
instead of the conventional p-i-n structure, and reports the
different electrical parameters corresponding to the variations
in its geometrical, and material parameters. The n-p-n
architecture is convenient to fabricate because of its similarity
with the bipolar junction transistors. To facilitate the
placement of the gate structures, the sandwiched p-type source
is elevated by some nanometers with reference to the n-type
drain regions. This type of design adds to the advantage of
creating a double-gate architecture with a shared source in the
middle.
Section II of this article introduces the schematic of the
device architecture, and simulation set-up, whereas, Section
III discusses the results. Section IV concludes the article.
II. ARCHITECTURE AND SIMULATION SET-UP
The architecture of the proposed TFET is shown in Fig. 1.
The architecture has two p-n junctions, and by reverse-biasing
both junctions, tunneling can be achieved at positive gate bias.
The architecture does not employ the conventional intrinsic
region as channel, and hence, the doping concentrations of the
drain regions must be optimized to counter the ambipolar
current as well as maintain an appreciable . The gate
dielectric thickness is kept constant at 3 nm for all simulations.
Variations in drain doping concentration ( ) , silicon
thickness ( ), source length ( ), gate-on-drain length ( ),
and source elevation ( ) are carried out to optimize the
architecture at drain-to-source voltage ( ) of 0.5 V.
Simulations have been carried out on Sentaurus TCAD
[13]. Bandgap narrowing effect, doping dependent mobility
model, and Fermi-Dirac statistics have been considered to
take into account the high doping concentration in the device.
Calibrated Schenk band-to-band tunneling (BTBT) model has
been used for the quantum tunneling effects. The calibration
has been done for the TFET in [14], and the model parameters
achieved after calibration are = 7 × 10 ,
= 1.25 × 10$ % .&
/ , and ℏ) = 18.6 % .
Fig. 1. (a) 2-D Schematic of proposed architecture; (b) Energy band diagram
of the proposed TFET at = 1 and = 0.5
III. RESULTS AND DISCUSSION
This section discusses the results associated with the
variation of different device parameters. The optimization of
the parameters has been carried out in the following order:

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 2021 Devices for Integrated Circuit (DevIC), 19-20 May, 2021, Kalyani, India 622

- - Φ- - - - to arrive at the most TABLE II. ELECTRICAL PARAMETERS FOR VARIATION IN GATE-ON-DRAIN
LENGTHS
significant results.
Figure 2 shows the transfer characteristics for different @A6 (nm) ⟹ 70 60 50 40 30 20
values of , keeping the following parameters ION (µA/µm) 22.5 22.5 22.5 22.5 22.5 21.6
constant: = 30 / , = 90 nm , = 10 / , = IOFF (fA/µm) 3320 108 4.27 25.0 12.7 12.9
120 nm , and Φ- = 4.66 % . In a conventional p-i-n ION/IOFF ( 109) 0.007 0.208 5.26 90 177 167
geometry, asymmetric source/ drain doping style is used to IAMB (aA/µm) 7.24 5.23 4.012 3.32 2.95 2.73
lower the ambipolar current. Similar method when adopted
SS (mV/dec) 62.83 51.69 44.81 40.31 37.12 36.64
here depicts similar results. With the decrease in drain doping
concentration, the ambipolar current reduces because the VTH(V) 0.804 0.806 0.806 0.810 0.810 0.785
junction depletion width in case of lower drain doping is wide
so that it reduces the tunneling probability on application of Figure 4 shows the transfer characteristics for different
negative gate-to-source voltages ( ). From Table I, gate metal workfunctions (Φ- ), considering the optimized
= 3 × 10 $ 4
has been selected for further values of , and from earlier steps. The plots shift to
optimization. the right with the increase in Φ- , thus leading to higher
threshold voltage ( BC ), and lower . An optimized Φ- of
4.66 eV is considered for further optimization of parameters.

Fig. 2. Transfer characteristics for different drain doping concentration

TABLE I. ELECTRICAL PARAMETERS FOR VARIATION IN DRAIN DOPING Fig. 4. Transfer characteristics for different gate metal workfunctions
CONCENTRATION
Figure 5 (a) depicts the transfer characteristics for
56789: (cm-3)⟹ 1016 1017 2 1017 3 1017 1018
variation in silicon body thickness ( ) considering the
ION (µA/µm) 20.2 20.2 21.5 22.5 26.8
optimized values of , , and Φ- from earlier steps.
IOFF (nA/µm) 1.72 3.37 4.55 5.36 11.2
As the device thickness is reduced, the drain current in the on-
ION/IOFF ( 103) 11.7 5.99 4.73 4.20 2.39 state increases for = 10 nm as compared to = 30 nm.
IAMB (nA/µm) 3.64 7.21 9.47 11.5 23.3 Similar results have been reported in [15].
SS (mV/dec) 59.51 59.5 54.4 58.66 58.06
VTH(V) 0.815 0.814 0.809 0.808 0.798

Figure 3 shows the transfer characteristics for different

gate-on-drain lengths ( ) , considering the optimized
from the earlier step. With the reduction in , the
ambipolar current reduces due to the reduction of the influence
of gate on the drain energy bands. However, values of are (a) (b)
similar because the BTBT is concentrated around a volume
closer to the junctions, and the values of considered for
analyses are larger than the length over which the BTBT
region exists. Both = 20 nm and = 30 nm have
comparable <-= ; however, = 30 nm has been taken as
the optimized value due to its higher ? , as evident from
>>
Table II.
(c) (d)
Fig. 5. Transfer characteristics for different (a) and (b) . BTBT profile
for (c) = 10 nm and (d) = 25 nm

Figure 5 (b) shows the transfer characteristics of the device for

Fig. 3. Transfer characteristics for different gate-on-drain lengths
different source elevations ( D ) taking EFGH/ , , Φ- , and
from earlier steps. As is increased, the drain current reduces due
to increased area for negative values of BTBT rate alongside the
vertical direction beneath the gate dielectric as evident from Fig. 5
(c), and Fig. 5 (d) for = 10 nm, and = 25 nm, respectively.
For the two cases, the positive BTBT generation rates are almost
similar, thus, implying that the negative values are responsible for

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 2021 Devices for Integrated Circuit (DevIC), 19-20 May, 2021, Kalyani, India
net contribution to the drain current because drain current per unit
width is theoretically expressed as = I J=B=B KLKM [16] where
J=B=B is the BTBT rate. A = 10 nm is selected as the optimized
length.
Figure 6 shows the transfer characteristics for different
lengths of the p-type source region ( ) taking optimized
values of , , Φ- , , and from earlier steps. With
the reduction in , reduces. With the shrinkage of the
region to as lower as 30 nm, it is highly probable that the
number of carriers for tunneling from the source reduces.
However, for = 50 nm, 70 nm, 120 nm, the lengths are
not too low to cause a higher variation in among them.
This suggests that there is possibility of a critical length
beyond which the reduction in may severely degrade the
characteristics.
Fig. 6. Transfer characteristics for different source lengths
IV. CONCLUSIONS
This article reported systematic optimization of an n-p-n
body TFET with dual gates over the two p-n junctions through
calibrated TCAD simulations. The following important and
interesting conclusions are observed.
• Asymmetric source/ drain doping concentration
influences the ambipolar current as well as the on-
state current of the device in a manner similar to the
conventional p-i-n architecture.
• Similar to gate-drain underlap in conventional p-i-n
TFETs decreasing the ambipolar current, in n-p-n
TFETs, similar effect is observed for reduction of the
gate-on-drain length.
• With the reduction in the length of the sandwiched p-
type source region, the drain current reduces due to
the increase in the percentage of depletion region
with reference to the available volume for carriers to
tunnel from the p-type region.
• Subthreshold swing in the range of 30 – 40 mV/dec,
on-state current in the order of 10-5 A/μm, and
? in the order of 1011 are obtained.
>>
ACKNOWLEDGMENT
This work is supported by Science & Engineering
Research Board (SERB), Govt. of India, (sanction order no.
SRG/2019/000660 dt. Nov. 26, 2019).
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