Annasaheb Dange College of Engineering and Technology, Ashta

(An Autonomous Institute)

Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

COURSE DETAILS
Structure of Course

Class S. Y. B. Tech. Semester-IV

Course Code and Course Title 1EEPC211, Digital Electronics &
Microprocessor
Prerequisite/s 1EEES108
Teaching Scheme: Lecture/Tutorial 04/00
Credits 03
Evaluation Scheme: ISE I/ MSE/ ISE II/
10/30/10/50
ESE

Course Objectives: This course aims to

1 Understand number representation and conversion between different
representation in digital electronic circuits
2 Transform Boolean equation for less number of logic gates
3 Analyze logic processes and formulate logic operations using combinational
logic circuits
4 Understand the architecture of microprocessor and the concept of memory
organization, assembly language programming
5 Study interfacing of microprocessor with peripheral devices

Course Outcomes (COs):

Upon successful completion of this course, the student will be able to:
1EEPC211_1 Attempt conversions among various number systems (K2)
1EEPC211_2 Transform given Boolean equation for minimum number of logic gates(K2)
1EEPC211_3 Formulate combinational logic circuits(K2)
1EEPC211_4 Explain architecture and working of 8085 microprocessor and
peripherals(K2)
1EEPC211_5 Interface 8085 microprocessor with various peripheral devices(K3)

1EEPC211_6 Design a microprocessor based system for given applications (K4)

Mapping of Course Outcomes to Program Outcomes:

 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Course Program Outcomes

Outcomes 1 2 3 4 5 6 7 8 9 10 11 12 PSO1 PSO2
1EEPC211_ 3 2
1
1EEPC211_ 3 2
2
1EEPC211_ 3 2
3
1EEPC211_ 3
4
1EEPC211_ 3 2 1
5
1EEPC211_ 3 3 1
6
Total 18 11 2
Avg. 3 2.2 1
1EEPC211 3 2 1

Course skill Acquisition Matrix:

Program Outcome
Course
1 2 3 4 5 6 7 8 9 10 11 12 PSO1 PSO2
1EEPC211 3 2 1
Targets for Course Outcomes:

Course Course Outcomes

1EEPC211 1EEPC211_1 1EEPC211_2 1EEPC211_3 1EEPC211_4 1EEPC211_5 1EEPC211_6
Target 3 3 3 3 3 3

Target Students scoring above passing marks (K) Average of Grade (A)
Level >=1
1 >=60%
2 >=70% >=2
3 >=80% >=3

Course Contents:
Unit Number System, Logic Gates and Boolean Algebra 10 Hrs
1 Decimal, Binary, octal, Hexadecimal, conversions, BCD code, Gray
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

code, weighted codes, signed magnitude representation

Logic gates, universal gates, logic families, performance parameters,
Boolean theorem, Boolean algebra
Unit Combinational Logic Circuit Design- 07 Hrs
2 K- map, SOP and POS form, Half adder, Full adder, subtractor,
magnitude comparator, code converter, Multiplexer, De-multiplexer,
Encoder, Decoder
Unit Sequential Logic Circuit Design-I 05 Hrs
3 Latches- S-R Latch, Gated Latch-Gated S-R Latch, Gated D Latch, Flip
flops-Edge triggered- S-R & Edge triggered- J-K
Unit Sequential Logic Circuit Design-II 05 Hrs
4 Counters-nod n asynchronous counter, Shift Registers-Serial-In Serial-
Out, Serial-In Parallel-Out, Parallel-In Serial-Out, Parallel-In Parallel-
Out
Unit Analog to Digital Conversion & Digital to Analog Conversion- 05 Hrs
5 Working principle and operation of different types of ADC & DAC,
Detailed study of ADC and DAC 0808,0809
Unit Microprocessor 8085: Architecture, Interfacing, Applications 10 Hrs
6 Architecture, Instruction set, Addressing modes, Memory, Assembly
language programming, Interrupt, Interrupt service routine, Address
decoding, Memory interfacing, Recent Trends in Microprocessor based
system design

Text Books:
Sr. Year of
Title Author Publisher Edition
No Edition
01 A Textbook of Digital
R. S. Sedha S.Chand Second 2005
Electronics
02 Advanced Microprocessor K. M. Tata Mc-Graw Third 2006
& Peripherals Bhurchandi Hill
A. K. Ray
03 Microprocessor 8085 Anil Genius Second 2009
Architecture, Sawarnkar
Programming Interfacing
04 Fundamentals of Digital A. Anand PHI Fourth 2016
Electronics Kumar

Reference Books:
Sr. Title Author Publisher Edition Year of
No Edition
01 Digital Electronics Anil Maini Wiley Second 2007
Principles &
Applications
02 Modern Digital R.P.Jain Mcgraw Higher Fourth 2009
Electronics Ed
03 Microprocessor and its B.Ram Tata Mc-Graw Sixth 2008
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Reference Books:
Sr. Title Author Publisher Edition Year of
No Edition
applications Hill
04 Digital Design Morris Mano Pearson Fifth 2012
05 Microprocessor Ramesh Penram Third 1997
Architecture, Gaonkar International
Programming &
Application with 8085

Lesson Plan
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Lesson Plan Planned Conducted

Lecture
Uni Date Date
No.
t Content Delivery
Number System, Logic Gates and Boolean 28.02.2022
1. Algebra - Binary number system
2. Octal, Decimal number system & Conversions 02.03.2022
3. Hexadecimal number system 03.03.2022
4. 8421 BCD Code, Gray Code, Weighted code 07.03.2022
1 5. Signed magnitude representation 09.03.2022
6. Logic Gates, Universal Gates 10.03.2022
7. Logic families 14.03.2022
8. Performance parameters 16.03.2022
9. Boolean theorem 17.03.2022
10. Boolean Algebra, Reducing Boolean Expressions 21.03.2022
Combinational Logic Circuit Design- K-map, 23.03.2022
11. Two variable, Three variable
SOP and POS form, Minimization of SOP and 24.03.2022
12. POS Expressions, Reading the K-map
13. Adders- Half Adder & Full Adder 04.04.2022
14. Subtractor- Half Subtractor & Full Subtractor 06.04.2022
2
Magnitude Comparator - 1-bit, 2-bit, 4-bit 07.04.2022
15. Magnitude Comparator
Code Converters, Multiplexer- 2, 4,16 Input 11.04.2022
16. Multiplexer, De multiplexer
Encoders- Octal to binary, Decimal to BCD, 13.04.2022
17. Decoders- 3 Line to 8 Line, BCD to Seven
Segment Decoder
Sequential Logic Circuit Design-I 14.04.2022
18. Latches- S-R Latch, ,
19. Gated Latch-Gated S-R Latch 25.04.2022
3 Gated D Latch 27.04.2022
20.
21. Flip flops-Edge triggered- S-R 28.04.2022
22. Edge triggered- J-K 02.05.2022
Sequential Logic Circuit Design-II 04.05.2022
23. Counters-nod n asynchronous counter
24. Shift Registers-Serial-In Serial-Out, 05.05.2022
4 Serial-In Parallel-Out 09.05.2022
25.
26. Parallel-In Serial-Out 11.05.2022
27. Parallel-In Parallel-Out 12.05.2022
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Lesson Plan Planned Conducted

Lecture
Uni Date Date
No.
t Content Delivery
Analog to Digital Conversion & Digital to 16.05.2022
Analog Conversion-
28.
5 Types of ADC converter- Counter type, Flash
type
Dual slop type, Successive approximation 18.05.2022
29.
type
Types of DAC converter- R-2R Ladder type, 19.05.2022
30.
Weighted resistor type
Pin configuration & Connection Diagram of ADC 30.05.2022
31. 0808/0809
Pin configuration & Connection Diagram of DAC 01.06.2022
32. 0808/0809
Microprocessor 8085: Architecture, 02.06.2022
33. Interfacing, Applications
Architecture of 8085-Register section,
Special purpose register, Arithmetic and Logical 06.06.2022
34. Section
6 35. Instruction Set & Classification of Instruction Set 08.06.2022
36. Addressing modes 09.06.2022
37. Memory & Types of memory 13.06.2022
38. Assembly language programming 15.06.2022
39. Interrupt, Interrupt service routine 16.06.2022
40. Address decoding 20.06.2022
Memory Interfacing- IO Mapped IO, Memory 22.06.2022
41. Mapped IO, Comparison of IO Mapped IO &
Memory Mapped IO
8255 PPI Interfacing, ADC 0808 Interfacing, 23.06.2022
42. DAC 0809 Interfacing, Recent Trends in
Microprocessor based system design
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Content Delivery and assessment tools

Lect. Teaching Plan Teaching Teaching Assessment Mapping with
Unit
No. Content Delivery Method Aids Tools CO PO
Number System, Logic Gates and
1 Boolean Algebra - Binary number LT CB ISE-I
system
2 Octal, Decimal number system & ISE-I
LT CB
Conversions ESE
3 Hexadecimal number system CB ISE-I
LT
MSE
4 8421 BCD Code, Gray Code, Weighted
LT CB MSE EE211.1
1 code 1,2
5 Signed magnitude representation LT CB QA EE211.2
6 Logic Gates, Universal Gates LT CB ISE-I
7 Logic families LT, DM CB QA
8 Performance parameters LT, DM CB QA
9 Boolean theorem LT, DM CB MSE
10 Boolean Algebra, Reducing Boolean ISE-I, MSE,
LT CB
Expressions ESE
11 Combinational Logic Circuit Design- ISE-I, MSE,
LT CB
K-map, Two variable, Three variable ESE
SOP and POS form, Minimization of
2 12 1, 2
SOP and POS Expressions, Reading the LT CB MSE
K-map
13 Adders- Half Adder & Full Adder LT CB ISE-I
14 Subtractor- Half Subtractor & Full
LT CB MSE EE211.3
Subtractor
15 Magnitude Comparator - 1-bit, 2-bit, 4- ISE-I, MSE,
LT CB
bit Magnitude Comparator ESE
16 Code Converters, Multiplexer- 2, 4,16 QA, ISE-I,
LT CB
Input Multiplexer, De multiplexer ESE
Encoders- Octal to binary, Decimal to
17 BCD, Decoders- 3 Line to 8 Line, BCD CB ISE-I, MSE,
LT
ESE
to Seven Segment Decoder
3 18 Sequential Logic Circuit Design-I
LT CB QA, MSE
Latches- S-R Latch, ,
19 Gated Latch-Gated S-R Latch LT CB ESE EE211.3
20 Gated D Latch LT CB MSE
21 Flip flops-Edge triggered- S-R LT CB MSE, ESE 1, 2
22 Edge triggered- J-K LT CB QA, MSE,
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Lect. Teaching Plan Teaching Teaching Assessment Mapping with

Unit
No. Content Delivery Method Aids Tools CO PO
ESE

4 Sequential Logic Circuit Design-II

23 Counters-nod n asynchronous LT CB, PPT QA, ISE-II
counter
24 Shift Registers-Serial-In Serial-Out, CB QA, ISE-II,
LT EE211.3 1,2
ESE
25 Serial-In Parallel-Out LT CB ISE-II, ESE
26 Parallel-In Serial-Out LT CB ISE-II, ESE
27 Parallel-In Parallel-Out LT CB ISE-II, ESE
Analog to Digital Conversion & QA, ISE-II,
28 Digital to Analog Conversion- CB ESE
LT
Types of ADC converter- Counter
type, Flash type
5 29 Dual slop type, Successive
LT CB ISE-II, ESE
approximation type EE211.3

30 Types of DAC converter- R-2R

LT CB ESE
Ladder type, Weighted resistor type
1,2
31 Pin configuration & Connection
LT CB ISE-II, ESE
Diagram of ADC 0808/0809
32 Pin configuration & Connection
LT CB ISE-II, ESE
Diagram of DAC 0808/0809
Microprocessor 8085: Architecture, EE211.4
33 Interfacing, Applications LT CB QA, ESE EE211.5
Architecture of 8085-Register section,
Special purpose register, Arithmetic and EE211.6 1,2,3
34 LT CB ESE
Logical Section
35 Instruction Set & Classification of
LT CB ESE
Instruction Set
36 Addressing modes LT CB ESE
37 Memory & Types of memory LT CB QA
6
38 Assembly language programming LT CB QA, ESE
39 Interrupt, Interrupt service routine LT CB ESE
40 Address decoding LT CB QA, ESE
Memory Interfacing- IO Mapped IO,
41 Memory Mapped IO, Comparison of IO LT CB ESE
Mapped IO & Memory Mapped IO
42 8255 PPI Interfacing, ADC 0808 LT ESE
Interfacing, DAC 0809 Interfacing,
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Lect. Teaching Plan Teaching Teaching Assessment Mapping with

Unit
No. Content Delivery Method Aids Tools CO PO
Recent Trends in Microprocessor CB
based system design
Note: TM-Teaching Method- Lecture (LT), Demo (DM), Group Discussion (GD), Seminar (SM),
Industrial Visits (IV), Case Studies (CS) etc.
TA-Teaching Aids–Chalk Board (CB), Power Point Presentation (PPT),Video Film (VF), E-Learning
(EL) etc
AT- Assessment Tool –In Semester Evaluation -I (ISE-I), Mid Semester Evaluation (MSE), In Semester
Evaluation -II (ISE-II), End Semester Evaluation (ESE), Rubrics (Course End Survey) (RB), etc.
Keep only those Teaching Methods, Teaching Aids and Assessment Tools which are applicable for
content delivery of course.

Questions Bank
Unit Q.No Questions Marks CO
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Convert the following binary numbers to decimal (06) 1EEPC211_1

1 a) 1011 b)1101101 c) 1101.11 d)1101110.011
Add the following binary numbers (06) 1EEPC211_1
2 a) 11011+1101 b)1011+1101+1001+1111
c) 101111.101 d) 1010.11+1101.10+1001.11+1111.11
Attempt the conversion of following decimal numbers to hexadecimal (08) 1EEPC211_1
3
a) 452 b) 4796 c) 1248.56 d) 8957.75
Draw the logic diagram and construct the truth table for each of the (08) 1EEPC211_1
4 following expressions:
a) X=A+B+CD b) Y=(AB)(A+B)+EF c) Z=AB+CD+ABC
Draw the logic symbols, construct the truth tables and with the help of (08) 1EEPC211_1
5 circuit diagram explain the working of the following gates:
1
a) AND b)OR c)NOT d)NAND e)NOR
6 Show an arrangement to X-OR and X-NOR the inputs A, B, C and D. (08) 1EEPC211_1

7 Reduce the expression f= AB+A+AB (08) 1EEPC211_1

Using the consensus theorem show that (08) 1EEPC211_1
8 F(A,B,C)= AB+BC+CA=AB+BC+CA
Write the Boolean expression for logic diagram given below and (08) 1EEPC211_1
transform it for minimum no of logic gates which implements
9
simplified expression.

Transform the Boolean equations for minimum no of literals (08) 1EEPC211_1

10 a) xy+xy+xy b) xy+yz+xz c) (x+y) (x+y)

1 Map the expression f= AB+AB (08) 1EEPC211_1

Reduce the expression (08) 1EEPC211_1

2
f= AB+AB+AB using mapping and obtain K-map in SOP form
Reduce the expressions (08) 1EEPC211_1
2
f= (A+B) (A+B) (A+B) using mapping and obtain K-map in POS form
Simplify the Boolean function using K-map in SOP and POS form: (06) 1EEPC211_1
3
F= ϵm (0 ,1 , 2 , 4 , 7 , 8 , 12, 14 ,15 , 16 , 17 ,18 , 20 , 24 , 28 , 30 ,31)
2 (08) 1EEPC211_1
4 Distinguish between a half subtractor and full subtractor
Realize 4-bit comparator 1EEPC211_1
5 (08)

Explain the working of BCD adder 1EEPC211_1

6 (08)
Design an 8421 to 2421 BCD code converter and draw its logic 1EEPC211_1
7 diagram (08)

Implement following logic function using an 8:1 MUX 1EEPC211_1

8 (08)
F(A,B,C,D)=AB+CD+AC
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Implement full adder using a 3 line to 8 line decoder 1EEPC211_1

9 (08)

Design an excess 3 adder using 4-bit parallel adder and logic gates 1EEPC211_1
10 (08)

Distinguish between combinational and sequential switching circuits. 1EEPC211_1

1 (08)

Draw the circuit diagram of master slave J-K flip-flop and explain its 1EEPC211_1
operation with the help of truth table. How it is different from edge
2 (08)
triggering?

Convert a D flip flop into: 1EEPC211_1

3 (08)
a) SR flip-flop b) JK flip-flop c) T flip-flop

With neat diagram explain the working of following types of shift 1EEPC211_1
register
4 (08)
a) Serial-In, Serial-Out b) Serial-In, Parallel-Out

Design a 4-bit universal shift register and draw the circuit with the 1EEPC211_1
given mode of operation table

S1 S0 Operation
3
0 0 Parallel
5 (08)
0 1 Shift Right

1 0 Shift Left

1 1 Inhibit Check

Explain the types of counters 1EEPC211_1

6 (08)

Design a mod-7 asynchronous counter using J-K FFs 1EEPC211_1

7 (08)

Design BCD up/down counter using S-R FFs 1EEPC211_1

8 (08)

Write the design steps for synchronous counter 1EEPC211_1

9 (08)
Explain the synchronous counter 1EEPC211_1
10 (08)
Explain the interfacing of ADC 0808 1EEPC211_1
1 (08)
4
Explain the interfacing of DAC 0808 1EEPC211_1
2 (08)
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

Explain the R-2R ladder type of DAC 1EEPC211_1

3 (08)

Explain the Dual Slope type of ADC (08) 1EEPC211_1

4

Explain the connection diagram of ADC 0808 (08) 1EEPC211_1

5

Explain the connection diagram of DAC 0808 (08) 1EEPC211_1

6

Explain the successive approximation type of ADC (08) 1EEPC211_1

7

Explain the functional block diagram of DAC (08) 1EEPC211_1

8

Explain the pin configuration of ADC (08) 1EEPC211_1

9

Explain the pin configuration of DAC (08) 1EEPC211_1

10

Draw the architecture of 8085 Microprocessor and explain function of 1EEPC211_1

1 (08)
each block
2 Explain various flags with format of status flag register (08) 1EEPC211_1
1EEPC211_1
3 Explain requirement of Stack Pointer in the architecture of 8085 (08)
1EEPC211_1
4 Explain the pin diagram of 8085 Microprocessor (08)

Explain with neat diagram de-multiplexing of address and data bus of 1EEPC211_1
5 (08)
8085
1EEPC211_1
6 Obtain 32*4 memory using 16*4 memory chips (08)
1EEPC211_1
7 Draw and explain in 4 K ROM interfacing with 8085 from 0000H (08)
5 1EEPC211_1
8 Interface 8K of EPROM and 8KB of RAM using 4KB devices (08)
1EEPC211_1
9 Explain with example various addressing modes of 8085 (08)
1EEPC211_1
10 Draw and explain the timing diagram for LDA 2000 instruction (08)
1EEPC211_1
11 Explain ADD B & ADD M & ADC R instructions (06)

Explain INR R, DCR R, INR M, DCR M instructions along with 1EEPC211_1

12 (06)
examples
1EEPC211_1
13 Add two 8 bit numbers (04)

Write a program to exchange the contents of memory location D000H 1EEPC211_1

14 (06)
and D001H. Assume the contents of memory location D000h be 10H
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

& contents of memory location D001H be 20H

1 Draw a interfacing of 8 bit ADC with 8085 with programming (08) 1EEPC211_1

Explain the procedure of interfacing 8bit ADC with 8085. Draw the 1EEPC211_1
2 (08)
suitable diagram
1EEPC211_1
3 Explain the interfacing of DAC with 8085along with programming (08)
1EEPC211_1
4 Explain the interfacing of 8255 PPI with 8085 (08)
1EEPC211_1
5 Distinguish between memory mapped I/O and I/O mapped I/O (08)
6
Interface an 8 bit DIP switch with 8085 such that the address assigned 1EEPC211_1
6 (08)
to its FFH.
Interface 8085 with 2K*8 ROM chip and two 1K*8 RAM chip such 1EEPC211_1
7 (08)
that following address map is realized
8 Explain memory mapped I/O (08) 1EEPC211_1

9 Explain I/O mapped I/O (08) 1EEPC211_1

1EEPC211_1
10 Explain the address decoding along with examples (08)

Mode of Assessment

Sr. Assessment
Mode of conduct Curriculum Remarks
No Type
It is for 25 marks to be
1 ISE I Written Exam Unit I and II
converted into 10
2 MSE Written exam Unit I, II and It is for 50 marks and 2
 Annasaheb Dange College of Engineering and Technology, Ashta
(An Autonomous Institute)
Tal - Walwa, Dist-Sangli; India 416 301

Department of Electrical Engineering

hours duration to be
III
converted into 30
AS/DWT/OE/PPT/ It is for 25 marks to be
3 ISE II Unit IV and V
SM/SWT/QZ converted into 10
The weight-age of shall be
On entire 30% for the syllabus
syllabus of covered for MSE & 70% for
4 ESE Written exam
Digital remaining syllabus after
Electronics MSE (Total marks: 100) to
be converted into 50

Assessment Tool-AS: Assignments, DWT: Declared Written Test, SWT: Surprised Written Test,
OE: Oral Examination, SM: Seminar, QZ: Quiz

Prepared by: Approved by: HOD