2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India

576

Investigating the Linearity Behavior of Dual

Gate Junction less MOSFET with high-K Gate
Stack at Cryogenic Temperatures
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) | 978-1-6654-7205-0/22/$31.00 ©2022 IEEE | DOI: 10.1109/EDKCON56221.2022.10032911

Rittik Ghosh
Ananya Karmakar Priyanka Saha
Department of Micro &
Department of Electronic Science Department of Electronics and
Nano Electronics
University of Calcutta Communication Engineering
Vellore Institute of Technology
Kolkata, India IIIT Kota
Vellore, India
ananya26m@gmail.com Kota, India
rittikghosh.kol@gmail.com
priyanka.ece@iiitkota.
ac.in

Abstract— This paper presents the linearity behavior of Dual al. [8] performed Non Equilibrium Green’s Function (NEGF)
Gate Junction less (JLDG) MOSFET with high-k gate stack simulations depicting current and subthreshold swing being
down to cryogenic temperature (50K). Based on ATLAS device insensitive to temperature reduction at a given channel length on
simulation data, the device characterization is demonstrated reaching below a certain critical temperature. Moreover, at
under cryogenic conditions in terms of surface potential, cryogenic temperature, MOSFET turns on over few millivolts
electron current density and output drain current. The impact which demands an accurate prediction of threshold voltage (Vt)
of temperature is further studied over linearity parameters of for proper analysis of drain current characteristics of the
the device e.g., transconductance (gm), higher order MOSFET device. Several threshold voltage models at low
transconductance (gm3), third-order current intercept point
temperatures have also been proposed in [6,9-11] so far
(IIP3), third-order intermodulation distortions (IMD3), and
higher-order voltage intercept point (VIP3). Such analysis will accounting dopant freeze out and field assisted ionization of the
confirm the ability of the device to operate under cryogenic dopants as well.
conditions for efficient quantum-computing applications. In this paper, a JLDG MOSFET with high-k gate stack has
been investigated for low noise applications at cryogenic
Keywords—Dual Gate, Junction less MOSFET, Cryogenic, temperature. Enhanced gate controllability of such geometry
Linearity, Quantum computing exhibits steep subthreshold slope and much reduced short channel
effects (SCEs) with enhanced device current [12]. The high-k
I. INTRODUCTION gate stack consisting of silicon dioxide as the interfacial layer
Incessant progress in silicon (Si) quantum computers with faster below high-k HfO2 provides reduced gate tunnelling leakage
speed of operation as compared to classical ones has attracted current with improved interface properties and enhanced carrier
significant research attention to the introduction of deep cryo- mobility [13]. The linearity behavior of the device is investigated
CMOS circuits operating at cryogenic temperature (<10K). The in terms of transconductance, third derivative of
quantum bit systems (qubits) integrated with CMOS circuits transconductance (gm3), third-order current intercept point (IIP3),
exhibits scalable quantum processors with reduced overhead third-order intermodulation distortions (IMD3) and third order
related to miniaturization, manipulation and read out of qubits. voltage intercept point (VIP3) down to cryogenic temperature.
Limited power consumption associated with CMOS based These linearity parameters are helpful in defining the existence of
quantum computing and subsequent demand to meet sharp noise in device output signal applicable for analog circuit designs.
timing constraints on control pulses applied to qubits leads to a Thus, better linearity, small distortions with enhanced driving
delicate trade-off between power consumption and performance current capability of the device under cryogenic conditions will
of MOSFET devices at cryogenic temperature [1-3]. As reported ensure its implementations for high performance and ultra- low
in [4], several device parameters like intrinsic carrier power quantum computing applications.
concentration, carrier mobility, effective masses of carriers,
density of states, band gap energy get modulated with
temperature variations thereby affecting the subthreshold II. DEVICE STRUCTURE & SIMULATION METHODOLOGY
domain of transfer characteristics of MOSFET devices. Thus,
accurate I-V models valid for cryogenic conditions and The proposed structure is shown in Fig. 1. It is a widely
simulation analysis based on such models have recently become
popular double gate structure with source and drain lengths of 30
the booming areas of research.
nm each while the channel is 50 nm. Thus, the total device length
It is well known fact that device performance is boosted as is 110 nm. Moreover, the doping is kept constant throughout the
temperature is lowered. An ideal infinitely steep, quasi step like silicon film with a concentration of 1 10 /cc. The channel
switching characteristics is exhibited by MOSFET at cryogenic thickness is fixed at 10 nm. We have considered a stacked gate
temperature as evident through temperature dependent oxide configuration which provides better gate-channel coupling.
subthreshold swing (S=ln (10) (KbT/q)) [5]. However, the For this, 2 nm HfO2 and 1 nm SiO2 are chosen to constitute the
validity of Boltzmann limit at low temperature is not gate oxide stack. The gate work function is 4.7 eV.
experimentally verified. Several studies are reported in [5-7]
exploring the temperature dependent limit for subthreshold The simulation framework is based on the SILVACO TCAD
swing of MOSFETs. Saturation limit of S=10mV/dec was tool [14]. For capturing the effect of temperature on the device
reported in [7] below critical temperature of 46K. Later Kao et performance, we have relied upon the GIGA which is a self-

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 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 577

Fig. 1. 3D schematic of Dual Gate Junction less MOSFET with High-K gate
stack

heating simulator within SILVACO package. Drift-diffusion

transport is considered within the lattice as the thickness is 10
nm. For this, we have considered Shockley-Read-Hall (SRH)
recombination model along with bandgap narrowing models to
account for the bandgap shrinkage due to high doping.

Moreover, the mobility of carriers is calculated using the

‘ANALYTIC’ model. FLDMOB model is also activated to
account for high electric field-based mobility fluctuation. The
lattice heating in the device is captured by the ‘LAT.TEMP’
command. In the SRH recombination model, the electron and
hole lifetimes are precisely calibrated to match the experimental
results. A thermocontact is also defined to modulate the external
temperature of the simulation setup.

III.RESULTS AND DISCUSSION

In this work, we have evaluated the performance of a JLDG

MOSFET at cryogenic temperatures by varying the temperature
from 400 K to 50 K. Note that, for a highly doped thin film (such
as Silicon), the charge carriers throughout the channel as well as
starts to freeze at ultra-low temperatures along with the carriers
present in the source/drain regions. Moreover, the sharp fall in
the temperature value from 400 K to 50 K also reduces the
mobility of the charge carriers (electrons), which affects the
transport mechanism to a large extent. Fig. 2(a) shows the energy Fig. 2 (a) Energy band diagram, (b) Surface potential and (c) Electron current
density of the proposed JLDG MOSFET against the variation of temperature.
band diagram of the proposed device at on-state, and it can be
observed that at low temperatures, there is downward bending of
the energy bands. In addition, it must be mentioned that at higher
temperatures, the surface potential has a larger value compared
to its lower counterpart as depicted in Fig. 2(b). Although, the
downward bending of the energy bands infers to a lowering of
the potential barrier, but due to the freezing of the carriers, we
can observe a steady decline in the electron current density
throughout the channel as shown in Fig. 2(c). Furthermore, the
transfer characteristics of the proposed device has been depicted
in Fig. 3(a) against the variation of different temperatures,
ranging from 400 K to 50 K. Note that, the drain current falls
drastically at 50 K from 800 µA/µm (at 400 K) to 10 µA/µm.
The output characteristics shown in Fig. 3(b) illustrates that the
maximum on-current reduces significantly as we reduce the computing. However, it must be mentioned that the above-
temperature to 50 K. We can also observe a significant change mentioned electrical parameters may change to a large extent in
in the threshold voltage of the device and at low temperatures, case of devices with an intrinsic channel material.
the threshold voltage increases. The minimum off-state current
in this case is close to 10-20 A/µm, which can be defined as noise
in any experimental set-up. At cryogenic temperatures, the
electrical behavior of the proposed device shows significant
variation and thus cryogenic analysis can be a pivotal parameter
while designing next-generation devices for quantum

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 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 578

Fig. 3 (a) Transfer and (b) Output characteristics of the proposed JLDG
MOSFET against the variation of temperature.

Fig. 5 (a) Third order voltage intercept point (VIP3), (b) Third order current
intercept point (IIP3) and (b) Third order intermodulation distortion (IMD3) of
the proposed JLDG MOSFET against the variation of temperature.

parameters. Intermodulation distortion should be as minimum as

possible. Fig. 5(a) shows the third order voltage intercept point
(VIP3) and it must be mentioned for both better linearity and less
Fig. 4 (a) Transconductance gain (gm) and (b) Third order transconductance distortion, VIP3 should be large. At cryogenic temperatures, the
gain (gm3) of the proposed JLDG MOSFET against the variation of temperature. VIP3 reduces as we reduce the temperature from 400 to 50 K. For
quantum computing applications, it is very important to study the
Transconductance gain or gm plays a key role in determining the linearity and distortion in a MOSFET to establish the influence
voltage to current conversion ratio in case of a transistor. Fig. of noise.
4(a) shows the gm against the variation of temperature, where at
cryogenic temperatures, the gain of the device reduces Similarly, the third order current intercept point (IIP3) has been
drastically. The maximum value of gm is 0.6 V, which signifies evaluated in Fig. 5(b) for different temperatures. It must be
that the device can be operated in subthreshold regime as well. mentioned that IIP3 should be as high as possible to achieve
On the other hand, higher order transconductance parameters better linearity in any transistor. Moreover, the third order
play a pivotal role in case of assessing the linearity performance intermodulation distortion (IMD3) has been shown in Fig. 5(c)
of the device and gm3 should be as minimum as possible to get and it should be minimum to achieve a distortion less device.
better linearity in our proposed device. Fig. 4(b) shows the
assessment of third order transconductance against the variation
IV.CONCLUSION
of temperature and it can be inferred that gm3 decreases as we go
down to 50 K. Note that, for circuits operating with weak signals, In this article, we have investigated the RF and analog
linearity and intermodulation distortions are one of the keys performance of a JLDG MOSFET at cryogenic temperatures. At

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 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 579
cryogenic temperatures, the mobility of the charge carriers
(electrons) reduces drastically, which contributes towards the
reduction of the On-state current in the device. Moreover, the
linearity behavior of the device is investigated in terms of
transconductance, third derivative of transconductance (gm3),
third-order current intercept point (IIP3), third-order
intermodulation distortions (IMD3) and third order voltage
intercept point (VIP3) down to cryogenic temperature. These
linearity parameters are helpful in defining the existence of noise
in device output signal applicable for analog circuit designs.
Thus, better linearity, small distortions with enhanced driving
current capability of the device under cryogenic conditions will
ensure its implementations for high performance and ultra- low
power quantum computing applications.

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