Microcomputer and Interfacing PDF

MICROCOMPUTER AND
INTERFACING [ECEG-4701]
Reading Material
COMPILED BY DEMISEW TEFERI
NOVEMBER 2, 2014
HAWASSA UNIVERSITY, INSTITUTE OF TECHNOLOGY, SCHOOL OF ELECTRICAL AND COMPUTER
ENGINEERING
Hawassa, Ethiopia
Hawassa University, Institute of Technology, School of Electrical and Computer Engineering
Academic Year: 2014/15
Table of Contents
CHAPTER ONE ......................................................................................................................................... 1
INTRODUCTION TO MICROPROCESSORS & COMPUTERS ........................................................................ 1
1.1
Introduction to Computers ...................................................................................................... 1
1.2
History of Microprocessors ...................................................................................................... 6
1.3
Evolution of the Intel processors ............................................................................................. 7
1.4
Review Questions .................................................................................................................. 10
CHAPTER TWO ...................................................................................................................................... 11
THE Intel 8086 MICROPROCESSOR ARCHITECTURE ............................................................................... 11
2.1
Intel 8086 CPU ARCHITECTURE .............................................................................................. 11
2.2
Bus Operation........................................................................................................................ 17
2.3
Memory Segmentation.......................................................................................................... 18
Compiled by Demisew Teferi
CHAPTER ONE
INTRODUCTION TO MICROPROCESSORS & COMPUTERS
1.1 Introduction to Computers
In this section we provide an introduction to the organization and internal working of computers.
The model used is generic, but the concepts discussed are applicable to all computers. Before
embarking on this subject, it will be helpful to review definitions of some of the most widely used
terminology in computer literature, such as K, mega, giga, byte, ROM, RAM, and so on.
1.1.1 Some important terminology
One of the most important features of a computer is how much memory it has. Next we review
terms used to describe amounts of memory in IBM PCs and compatibles. Recall that a bit is a
binary digit that can have the value 0 or 1. A byte is defined as 8 bits. A nibble is half a byte, or 4
bits. A word is two bytes, or 16 bits. The following display is intended to show the relative size of
these units. Of course, they could all be composed of any combination of zeros and ones.
0
Bit
Nibble
Byte
Word
0000
0000 0000
0000 0000 0000 0000
A kilobyte is 210 bytes, which is 1024 bytes. The abbreviation K is often used. For example, some
floppy disks hold 356K bytes of data. A megabyte, or meg as some call it, is 220 bytes. That is a
little over 1 million bytes; it is exactly 1,048,576. Moving rapidly up the scale in size, a gigabyte
is 230 bytes (over 1 billion), and a terabyte is 240 bytes (over 1 trillion). As an example of how some
of these terms are used, suppose that a given computer has 16 megabytes of memory. That would
be 16 x 220, or 24 x 220, which is 224. Therefore 16 megabytes is 224 bytes.
Two types of memory commonly used in microcomputers are RAM, which stands for random
access memory (sometimes called read/write memory), and ROM, which stands for read-only
memory. RAM is used by the computer for temporary storage of programs that it is running. That
data is lost when the computer is turned off. For this reason, RAM is sometimes called volatile
memory. ROM contains programs and information essential to operation of the computer. The
information in ROM is permanent, cannot be changed by the user, and is not lost when the power
is turned off. Therefore, it is called nonvolatile memory.
1.1.2 Internal organization of computers
The internal working of every computer can be broken down into three parts: CPU (central
processing unit), memory, and I/O (input/output) devices (see Figure 1-1). The function of the
CPU is to execute (process) information stored in memory. The function of I/O devices such as
the keyboard and video monitor is to provide a means of communicating with the CPU. The CPU
is connected to memory and I/0 through strips of wire called a bus. The bus inside a computer
carries information from place to place just as a street bus carries people from place to place.
1
In every computer there are three types of buses: address bus, data bus, and control bus. For a
device (memory or I/O) to be recognized by the CPU, it must be assigned an address. The address
assigned to a given device must be unique: no two devices are allowed to have the same address.
The CPU puts the address (of course, in binary) on the address bus, and the decoding circuitry
finds the device. Then the CPU uses the data bus either to get data from that device or to send data
to it. The control buses are used to provide read or write signals to the device to indicate if the
CPU is asking for information or sending it information. Of the three buses, the address bus and
data bus determine the capability of a given CPU.
1.1.3 More about the data bus
Since data buses are used to carry information in and out of a CPU, the more data buses available,
the better the CPU. If one thinks of data buses as highway lanes, it is clear that more lanes provide
a better pathway between the CPU and its external devices (such as printers, RAM, ROM, etc.;
see Figure 1-2). By the same token, that increase in the number of lanes increases the cost of
construction. More data buses mean a more expensive CPU and computer. The average size of
data buses in CPUs varies between 8 and 64. Early computers such as Apple 2 used an 8-bit data
bus, while supercomputers such as Cray use a 64-bit data bus. Data buses are bidirectional, since
the CPU must use them either to receive or to send data. The processing power of a computer is
related to the size of its buses, since an 8-bit bus can send out 1 byte a time, but a 16-bit bus can
send out 2 bytes at a time, which is twice as fast.
1.1.4 More about the address bus
Since the address bus is used to identify the devices and memory connected to the CPU, the more
address buses available, the larger the number of devices that can be addressed. In other words,
the number of address buses for a CPU determines the number of locations with which it can
communicate. The number of locations is always equal to 2x, where x is the number of address
lines, regardless of the size of the data bus. For example, a CPU with 16 address lines can provide
a total of 65,536 (216) or 64K bytes of addressable memory. Each location can have a maximum
of 1 byte of data. This is due to the fact that all general-purpose microprocessor CPUs are what is
called byte addressable. As another example, the IBM PC AT uses a CPU with 24 address lines
and 16 data lines. In this case the total accessible memory is 16 megabytes (224 = 16 megabytes).
In this example there would be 224 locations, and since each location is one byte, there would be
16 megabytes of memory. The address bus is a unidirectional bus, which means that the CPU uses
the address bus only to send out addresses.
To summarize: The total number of memory locations addressable by a given CPU is always equal
to 2x where x is the number of address bits, regardless of the size of the data bus.
1.1.5 CPU and its relation to RAM and ROM
For the CPU to process information, the data must be stored in RAM or ROM. The function of
ROM in computers is to provide information that is fixed and permanent. This is information such
as tables for character patterns to be displayed on the video monitor, or programs that are essential
to the working of the computer, such as programs for testing and finding the total amount of RAM
installed on the system, or programs to display information on the video monitor. In contrast, RAM
is used to store information that is not permanent and can change with time, such as various
versions of the operating system and application packages such as word processing or tax
calculation packages. These programs are loaded into RAM to be processed by the CPU. The CPU
cannot get the information from the disk directly since the disk is too slow. In other words, the
CPU gets the information to be processed, first from RAM (or ROM). Only if it is not there does
the CPU seek it from a mass storage device such as a disk, and then it transfers the information to
RAM. For this reason, RAM and ROM are sometimes referred to as primary memory and disks
are called secondary memory. Figure 1-2 shows a block diagram of the internal organization of
the PC.
1.1.6 Inside CPUs
A program stored in memory provides instructions to the CPU to perform an action. The action
can simply be adding data such as payroll data or controlling a machine such as a robot. It is the
function of the CPU to fetch these instructions from memory and execute them. To perform the
actions of fetch and execute, all CPUs are equipped with resources such as the following:
a) Foremost among the resources at the disposal of the CPU are a number of registers. The
CPU uses registers to store information temporarily. The information could be two values to
be processed, or the address of the value needed to be fetched from memory. Registers inside
the CPU can be 8-bit, 16-bit, 32-bit, or even 64-bit registers, depending on the CPU. In
general, the more and bigger the registers, the better the CPU. The disadvantage of more and
bigger registers is the increased cost of such a CPU.
b) The CPU also has what is called the ALU (arithmetic/logic unit). The ALU section of the
CPU is responsible for performing arithmetic functions such as add, subtract, multiply, and
divide, and logic functions such as AND, OR, and NOT.
c) Every CPU has what is called a program counter. The function of the program counter is
to point to the address of the next instruction to be executed. As each instruction is executed,
the program counter is incremented to point to the address of the next instruction to be
executed. It is the contents of the program counter that are placed on the address bus to find
and fetch the desired instruction. In the IBMPC, the program counter is a register called IP,
or the instruction pointer.
d) Every CPU has also Instruction decoder. The function of the instruction decoder is to
interpret the instruction fetched into the CPU. One can think of the instruction decoder as a
kind of dictionary, storing the meaning of each instruction and what steps the CPU should
take upon receiving a given instruction. Just as a dictionary requires more pages the more
words it defines, a CPU capable of understanding more instructions requires more transistors
to design.
1.1.7
Internal working of computers
To demonstrate some of the concepts discussed above, a step-by-step analysis of the process a
CPU would go through to add three numbers is given next. Assume that an imaginary CPU has
registers called A, B, C, and D. It has an 8-bit data bus and a 16-bit address bus. Therefore,
the CPU can access memory from addresses 0000 to FFFFH (for a total of 1000H locations).
The action to be performed by the CPU is to put hexadecimal value 21 into register A, and
then add to register A values 42H and 12H. Assume that the code for the CPU to move a
value to register A is 1011 0000 (B0H) and the code for adding a value to register A is 0000
0100 (04H). The necessary steps and code to perform them are as follows.
If the program to perform the actions listed above is stored in memory locations starting at
1400H, the following would represent the contents for each memory address location:
4
The actions performed by the CPU to run the program above would be as follows:
a) The CPU's program counter can have a value between 0000 and FFFFH. The program
counter must be set to the value l 400H, indicating the address of the first instruction
code to be executed. After the program counter has been loaded with the address of
the first instruction, the CPU is ready to execute.
b) The CPU puts 1400H on the address bus and sends it out. The memory circuitry finds
the location while the CPU activates the READ signal, indicating to memory that it
wants the byte at location 1 4 0 0 H . This causes the contents of memory location
1400H, which is BO, to be put on the data bus and brought into the CPU.
c) The CPU decodes the instruction BO with the help of its instruction decoder
dictionary. When it finds the definition for that instruction it knows it must bring into
register A of the CPU the byte in the next memory location. Therefore, it commands
its controller circuitry to do exactly that. When it brings in value 21H from memory
location 1401, it makes sure that the doors of all registers are closed except register A.
Therefore, when value 21H comes into the CPU it will go directly into register A. After
completing one instruction, the program counter points to the address of the next
instruction to be executed, which in this case is 1402H. Address 1402 is sent out on the
address bus to fetch the next instruction.
d) From memory location 1402H it fetches code 04H. After decoding, the CPU knows that
it must add to the contents of register A the byte sitting at the next address (1403). After
it brings the value (in this case 42H) into the CPU, it provides the contents of register
A along with this value to the ALU to perform the addition. It then takes the result of
the addition from the ALU's output and puts it in register A. Meanwhile the program
counter becomes 1404, the address of the next instruction.
e) Address 1404H is put on the address bus and the code is fetched into the CPU, decoded,
and executed. This code is again adding a value to register A. The program counter is
updated to 1406H.
f) Finally, the contents of address 1406 are fetched in and executed. This HALT instruction
tells the CPU to stop incrementing the program counter and asking for the next
instruction. In the absence of the HALT, the CPU would continue updating the program
counter and fetching instructions.
5
Now suppose that address 1403H contained value 04 instead of 42H. How would the CPU
distinguish between data 04 to be added and code 04? Remember that code 04 for this CPU means
move the next value into register A. Therefore, the CPU will not try to decode the next value. It
simply moves the contents of the following memory location into register A, regardless of its value.
1.2 History of Microprocessors

In the 1940s, CPUs were designed using vacuum tubes. The vacuum tube was bulky and consumed
a lot of electricity. For example, the first large-scale digital computer, ENIAC, consumed 130,000
watts of power and occupied 1500 square feet. The invention of transistors changed all of that. In
the 1950s, transistors replaced vacuum tubes in the design of computers. Then in 1959, the first IC
(integrated circuit) was invented. This set into motion what many people believe is the second
industrial revolution. In the 1960s the use of IC chips in the design of
CPU boards became common. It was not until the 1970s that the entire CPU was put on a single
IC chip. The first working CPU on a chip was invented by Intel in 1971. This CPU was called a
microprocessor. The first microprocessor, the 4004, had a 4-bit data bus and was made of 2300
transistors. It was designed primarily for the hand-held calculator but soon came to be used in
applications such as traffic-light controllers. The advances in IC fabrication made during the 1970s
made it possible to design microprocessors with an 8-bit data bus and a 16-bit address bus.
By the late 1970s, the Intel 8080/85 was one of the most widely used microprocessors, appearing
in everything from microwave ovens to homemade computers. Meanwhile, many other companies
joined in the race for faster and better microprocessors. Notable among them was Motorola with
its 6800 and 68000 microprocessors. Apple's Macintosh computers use the 68000 series
microprocessors.
1.2.1
CISC Vs RISC
Until the early 1980s, all CPUs, whether single-chip or whole-board, followed the CISC (complex
instruction set computer) design philosophy. CISC refers to CPUs with hundreds of instructions designed
for every possible situation.
To design CPUs with so many instructions consumed not only hundreds of thousands of transistors, but
also made the design very complicated, time-consuming, and expensive. In the early 1980s, a new CPU
design philosophy called RISC (reduced instruction set computer) was developed. The proponents of RISC
argued that no one was using all the instructions etched into the brain of CISC-type CPUs. Why not
streamline the instructions by simplifying and reducing them from hundreds to around 40 or so and use all
the transistors that are saved to enhance the power of the CPU? Although the RISC concept had been
explored by computer scientists at IBM as early as the 1970s, the first working single-chip RISC
microprocessor was implemented by a group of researchers at the University of California at Berkeley in
1980. Today the RISC design philosophy is no longer an experiment limited to research laboratories. Since
the late 1980s, many companies designing new CPUs (either single-chip or whole-board) have used the
RISC philosophy. It appears that eventually the only CISC microprocessors remaining in use will be
members of the 80x86 family (8086, 8088, 80286, 80386, 80486, 80586, etc.) and the 680x0 family (68000,
68010, 68020, 68030, 68040, 68050, etc.). The 80x86 will be kept alive by the huge base of IBM PC, PS,
and compatible computers, and the Apple Macintosh is prolonging the life of 680x0 microprocessors.
6
1.3 Evolution of the Intel processors

In this section we trace the evolution of Intel's family of microprocessors from the late 1970s, when the
personal computer had not yet found widespread acceptance, to the powerful microcomputers widely in
use today.
1.3.1
The Start of microprocessor (Intel 4004)
The worlds first microprocessor, the Intel 4004, was a 4-bit microprocessorprogrammable controller on
a chip. It addressed a mere 4096, 4-bit-wide memory locations. The 4004 instruction set contained only 45
instructions. It was fabricated with the then-current state-of the-art P-channel MOSFET technology that
only allowed it to execute instructions at the slow rate of 50 KIPs (kilo-instructions per second). This was
slow when compared to the 100,000 instructions executed per second by the 30-ton ENIAC computer in
1946. The main difference was that the 4004 weighed much less than an ounce.
The main problems with this early microprocessor were its speed, word width, and memory size. The
evolution of the 4-bit microprocessor ended when Intel released the 4040, an updated version of the earlier
4004. The 4040 operated at a higher speed, although it lacked improvements in word width and memory
size. The 4-bit microprocessor still survives in low-end applications such as microwave ovens and small
control systems and is still available from some microprocessor manufacturers. Most calculators are still
based on 4-bit microprocessors that process 4-bit BCD (binary-coded decimal) codes.
1.3.2
Intel 8008, 8080 Microprocessors
Later in 1971, realizing that the microprocessor was a commercially viable product, Intel Corporation
released the 8008an extended 8-bit version of the 4004 microprocessor. The 8008 addressed an expanded
memory size (16K bytes) and contained additional instructions (a total of 48) that provided an opportunity
for its application in more advanced systems.
As engineers developed more demanding uses for the 8008 microprocessor, they discovered that its
somewhat small memory size, slow speed, and instruction set limited its usefulness. Intel recognized these
limitations and introduced the 8080 microprocessor in 1973the first of the modern 8-bit microprocessors.
About six months after Intel released the 8080 microprocessor. What Was Special about the 8080? Not only
could the 8080 address more memory and execute additional instructions, but it executed them 10 times
faster than the 8008. An addition that took 20 s (50,000 instructions per second) on an 8008-based system
required only 2.0 s (500,000 instructions per second) on an 8080-based system. Also, the 8080 was
compatible with TTL (transistor-transistor logic), whereas the 8008 was not directly compatible. This made
interfacing much easier and less expensive. The 8080 also addressed four times more memory (64K bytes)
than the 8008 (l6K bytes). These improvements are responsible for ushering in the era of the 8080 and the
continuing saga of the microprocessor.
1.3.3
Intel 8085 Microprocessor
In 1977, Intel Corporation introduced an updated version of the 8080the 8085. The 8085 was to be the
last 8-bit, general-purpose microprocessor developed by Intel. Although only slightly more advanced than
an 8080 microprocessor, the 8085 executed software at an even higher speed. An addition that took 2.0 s
(500,000 instructions per second on the 8080) required only 1.3 s (769,230 instructions per second) on the
8085.
The main advantages of the 8085 were its internal clock generator, internal system controller, and higher
clock frequency. This higher level of component integration reduced the 8085s cost and increased its
usefulness.
1.3.4
Evolution from 8080/8085 to 8086
In 1978, Intel Corporation introduced a 16-bit microprocessor called the 8086. This processor was a major
improvement over the previous generation 8080/8085 series Intel microprocessors in several ways. First,
the 8086's capacity of 1 megabyte of memory exceeded the 8080/8085s capability of handling a maximum
of 64K bytes of memory. Second, the 8080/8085 was an 8-bit system, meaning that the microprocessor
could work on only 8 bits of data at a time. Data larger than 8 bits had to be broken into 8-bit pieces to be
processed by the CPU. In contrast, the 8086 is a 16-bit microprocessor. Third, the 8086 was a pipelined
processor, as opposed to the nonpipelined 8080/8085. In a system with pipelining, the data and address
buses are busy transferring data while the CPU is processing information, thereby increasing the effective
processing power of the microprocessor.
Although pipelining was a common feature of mini- and mainframe computers, Intel was a pioneer in
putting pipelining on a single-chip microprocessor.
1.3.5
Evolution from 8086 to 8088
The 8086 is a microprocessor with a 16-bit data bus internally and externally, meaning that all registers are
16 bits wide and there is a 16-bit data bus to transfer data in and out of the CPU. Although the introduction
of the 8086 marked a great advancement over the previous generation of microprocessors, there was still
some resistance in using the 16-bit external data bus since at that time all peripherals were designed around
an 8-bit microprocessor. In addition, a printed circuit board with a 16-bit data bus was much more
expensive. Therefore, Intel came out with the 8088 version. It is identical to the 8086 as far as programming
is concerned, but externally it has an 8-bit data bus instead of a 16-bit bus. It has the same memory capacity,
1 megabyte.
1.3.6
Success of the 8088
In 1981, Intel's fortunes changed forever when IBM picked up the 8088 as their microprocessor of choice
in designing the IBM PC. The 8088-basecl IBM PC was an enormous success, largely because IBM and
Microsoft (the developer of the MS-DOS operating system) made it an open system, meaning that all
documentation and specifications of the hardware and software of the PC were made public. This made it
possible for many other vendors to clone the hardware successfully and thus spawned a major growth in
both hardware and software designs based on the IBM PC. This is in contrast with the Apple computer,
which was a closed system, blocking any attempt at cloning by other manufacturers, both domestically and
overseas.
1.3.7
Other microprocessors: the 80286, 80386, and 80486
With a major victory behind Intel and a need from PC users for a more powerful microprocessor, Intel
introduced the 80286 in 1982. Its features included 16-bit internal and external data buses; 24 address lines,
which give 16 megabytes of memory (224 = 16 megabytes); and most significantly, virtual memory. The
80286 can operate in one of two modes: real mode or protected mode. Real mode is simply a faster
8088/8086 with the same maximum of 1 megabyte of memory. Protected mode allows for 16M of memory
but is also capable of protecting the operating system and programs from accidental or deliberate destruction
by a user, a feature that is absent in the single-user 8088/8086. Virtual memory is a way of fooling the
microprocessor into thinking that it has access to an almost unlimited amount of memory by swapping data
between disk storage and RAM. IBM picked up the 80286 for the design of the IBM PC AT, and the clone
makers followed IBM's lead.
With users demanding even more powerful systems, in 1985 Intel introduced the 80386 (sometimes called
80386DX), internally and externally a 32-bit microprocessor with a 32-bit address bus. It is capable of
handling physical memory of up to 4 gigabytes (232). Virtual memory was increased to 64 terabytes (246).
All microprocessors discussed so far were general-purpose microprocessors and could not handle
mathematical calculations rapidly. For this reason, Intel introduced numeric data processing chips, called
math coprocessors, such as the 8087, 80287, and 80387. Later Intel introduced the 386SX, which is
internally identical to the 80386 but has a 16-bit external data bus and a 24-bit address bus which gives a
capacity of 16 megabytes (224) of memory. This makes the 386SX system much cheaper. With the
introduction of the 80486 in 1989, Intel put a greatly enhanced version of the 80386 and the math
coprocessor on a single chip plus additional features such as cache memory. Cache memory is static RAM
with a very fast access time. Table 1-1 summarizes the evolution of Intels microprocessors. It must be
noted that all programs written for the 8086/88 will run on 286, 386, and 486 computers.
1.4 Review Questions

1.
2.
3.
4.
5.
6.
7.
How many bytes is 24 kilobytes?

What does "RAM" stand for? How is it used in computer systems?
What does "ROM" stand for? How is it used in computer systems?
Why RAM is called volatile memory?
List the three major components of a computer system.
What does "CPU" stand for? Explain its function in a computer.
List the three types of buses found in computer systems and state briefly the purpose of each
type of bus.
8. State which of the following is unidirectional and which is bidirectional.
a)
data bus b) address bus
9. If an address bus for a given computer has 16 lines, then what is the maximum amount of
memory it can access?
10. What does "ALU" stand for? What is its purpose?
11. How are registers used in computer systems?
12. What is the purpose of the program counter?
13. What is the purpose of the instruction decoder?
14. What is a microprocessor?
15. Describe briefly how advances in technology have affected the size, cost, and availability
of computer systems.
16. Explain the major difference between CISC and RISC computers.
17. Name three features of the 8086 that were improvements over the 8080/8085.
18. What is the major difference between 8088 and 8086 microprocessors?
19. Give the size of the address bus and physical memory capacity of the following: (a) 8086
(b) 80286 (c) 80386
20. The 80286 is a
-bit microprocessor, whereas the 80386 is a
-bit
microprocessor.
21. State the major difference between the 80386 and the 80386SX.
22. List additional features introduced with the 80286 that were not present in the 8086.
23. List additional features of the 80486 that were not present in the 80386.
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CHAPTER TWO
THE Intel 8086 MICROPROCESSOR ARCHITECTURE
As you may recall the 8086 microprocessor is a 16~bit machine with a 16-bit data bus and a 20bit address bus. This allows for 220, or 1MB of addressing space. The instruction set and addressing
modes presented in this course first became available with the 8086 and every processor in the
80x86 family to come after the 8086 supports the initial instruction set.
When the 8086 is reset (or first turned on), the processor fetches its first instruction from address
FFFFOH. On the PC, this address points to boot instructions in the motherboard's system ROM,
which begins the process of booting DOS. All of the 80x86 machines, even the Pentium, follow
this mechanism when reset.
A slightly reengineered version of the 8086 was the 8088 microprocessor, which is similar to the
8086 except for the use of an external data bus that is only 8 bits wide. This forces the 8088 to
access memory twice as often as the 8086, resulting in a significant performance penalty in terms
of execution speed. Both the 8086 and the 8088 were used in the first PCs to hit the market.
2.1 Intel 8086 CPU ARCHITECTURE

Figure 2-1 shows a block diagram of the 8086 internal architecture. It is internally divided into
two separate functional units. These are the Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional units can work simultaneously to increase system speed and hence the
throughput. Throughput is a measure of number of instructions executed per unit time.
2.1.1 Bus Interface Unit (BIU)

The bus interface unit is the 8086s interface to the outside world. It provides a full 16-bit bidirectional data bus and 20-bit address bus. The bus interface unit is responsible for performing all
external bus operations, as listed below.
Functions of BIU:
i.
ii.
iii.
iv.
v.
vi.
It sends address of the memory or I/O.

It fetches instruction from memory.
It reads data from port/memory.
It writes data into port/memory.
It supports instruction queuing.
It provides the address relocation facility
To implement these functions the BIU contains the instruction queue, segment registers,
instruction pointer, address summer and bus control logic.
2.1.2 Execution Unit (EU)

The EU of 8086 tells the BIU from where to fetch instructions or data. It decodes instructions and
executes them. To implement these functions EU contains control circuitry, instruction decoder,
arithmetic logic unit (ALU) and registers (flag register, general purpose registers, pointers and
index registers).
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2.1.3 Instruction Queue

There are two ways to make the CPU process information faster: increase the working frequency
or change the internal architecture of the CPU. The first option is technology dependent, meaning
that the designer must use whatever technology is available at the time, with consideration for cost.
The technology and materials used in making ICs (integrated circuits) determine the working
frequency, power consumption, and the number of transistors packed into a single-chip
microprocessor. A detailed discussion of IC technology is beyond the scope of this course. It is
sufficient for the purpose at hand to say that designers can make the CPU work faster by increasing
the frequency under which it runs if technology and cost allow.
The second option for improving the processing power of the CPU has to do with the internal
working of the CPU. In the 8085 and earlier microprocessor, the CPU could either fetch or execute
at a given time. In other words, the CPU had to fetch an instruction from memory, then execute it
and then fetch again, execute it, and so on. The idea of pipelining in its simplest form is to allow
the CPU to fetch and execute at the same time as shown in Figure 2-2. It is important to point out
that Figure 1-2 is not meant to imply that the amount of time for fetch and execute are equal.
Intel implemented the concept of pipelining in the 8086 by splitting the internal structure of the
microprocessor into two sections: the execution unit (EU) and the bus interface unit (BIU) as stated
above. These two sections work simultaneously. The BIU accesses memory and peripherals while
the EU executes instructions previously fetched. This works only if the BIU keeps ahead of the
12
EU; thus the BIU of the 8086 has a buffer, or queue (see Figure 1-1). The buffer is 6 bytes in the
8086. If any instruction takes too long to execute, the queue is filled to its maximum capacity and
the buses will sit idle. The BIU fetches a new instruction whenever the queue has room for 2 bytes
in the 6-byte 8086 queue.
In some circumstances, the microprocessor must flush out the queue. For example, when a jump
instruction is executed, the BIU starts to fetch information from the new location in memory and
information in the queue that was fetched previously is discarded. In this situation the EU must
wait until the BIU fetches the new instruction. This is referred to in computer science terminology
as a branch penalty. In a pipelined CPU, this means that too much jumping around reduces the
efficiency of a program.
2.1.4 Registers
In the CPU, registers are used to store information temporarily. That information could be one or
two bytes of data to be processed or the address of data. The bits of a register are numbered in
descending order, as shown below.
The registers of the 8086 fall into the six categories outlined in Figure 2-3.
a) General Purpose Registers
The BIU of 8086 has four 16-bit general purpose registers labeled AX, BX, CX and DX as shown
in Figure 2-1 and Figure 2-3 a). Each 16-bit general purpose register can be split into two 8-bit
registers. The letters L and H specify the lower and higher bytes of a particular register. For
example, BH means the higher byte (8-bits) of the BX register and BL means the lower byte (8bits) of the BX register. The letter X is used to specify the complete 16-bit register.
13
The general purpose registers are either used for holding data, variables and intermediate results
temporarily. They can also be used as a counters or used for storing offset address for some
particular addressing modes. The register AX is used as 16-bit accumulator whereas register AL
(lower byte of AX) is used as 8-bit accumulator. The register BX is also used as offset storage for
generating physical addresses in case of certain addressing modes. On the other hand, the register
CX is also used as a default counter in case of string and loop instructions.
b) Segment Registers
The physical address of the 8086 is 20-bit wide to access 1 Mbyte memory locations. However,
its registers which contain logical addresses are just 16-bits wide. Hence 8086 uses memory
segmentation. It treats the 1 Mbyte of memory as divided into segments, with a maximum size of
a segment as 64 Kbytes. Thus any location within the segment can be accessed using 16 bits. The
8086 allows only four active segments at a time, as shown in Figure 2-4. For the selection of the
four active segments the 16-bit segment registers are provided by the bus interface unit (BIU) of
the 8086. These four registers are: Code segment (CS) register, the data segment (DS) register, the
Stack segment (SS) register, and the extra segment (ES) register. These are used to hold the upper
16-bits of the starting addresses of the four memory segments, on which 8086 works at a particular
time. For example, the value in CS identifies the starting address of 64 K-byte segment known as
code segment. By ''starting address", we mean the lowest addressed byte in the active code
segment. The starting address is also known as base address or segment base.
14
The BIU always inserts zeros for the lower 4 bits (nibble) in the contents of segment register to
generate 20-bit base address. For example, if the code segment register contains 348AH, then code
segment will start at address 34S80H.
Functions of Segment Registers:

i.
ii.
iii.
The CS register holds the upper 16-bits of the starting address of the segment from
which the BIU is currently fetching the instruction code byte.
The SS register is used for the upper 16-bits of the starting address for the program
stack (all stack related instruction will operate on stack).
ES register and DS register are used to hold the upper 16-bits of the starting address of
the two memory segments which are used for data.
c) Pointers and Index Registers
All segment registers are 16-bit wide. But it is necessary to generate 20-bit address (physical
address) on the address bus. To get 20-bit physical address one or more pointer or index registers
are associated with each segment register. The pointer registers IP, BP and SP are associated with
code, data and stack segments, respectively. They hold the offset within the code, data and stack
15
segments, respectively. The index registers DI and SI are used as a general purpose registers as
well as for offset storage in case of indexed, based indexed and relative based indexed addressing
modes.
d) Flag Register
A flag is a flip-flop, which indicates some condition produced by the execution of an instruction,
or controls certain operations of the EU. A 16-bit flag register in the EU contains nine active flags.
Figure 2-5 shows the location of the nine flags in the flag register.
Six of the nine flags are used to indicate some condition produced by an instruction. For example,
a flip-flop called the carry flag will be set to a 1 if the addition of two 16- bit binary numbers
produces a carry out of the most significant bit position. If no carry out of the MSB is produced
by the addition, then the carry flag will be a 0. The EU thus effectively runs up a "flag" to tell you
that a carry was produced.
The six conditional flags in this group are the carry flag (CF), the parity flag (PF), the auxiliary
carry flag (AF), the zero flag (ZF), the sign flag (SF), and the overflow flag (OF). Certain 8086
instructions check these flags to determine which of two alternative actions should be done in
executing the instruction.
S-Sign Flag: This flag is set, when the result of any computation is negative. For signed
computations, the sign flag equals the MSB of the result.
Z-Zero Flag: This flag is set, if the result of the computation or comparison performed by the
previous instruction/instructions is zero.
P-Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1s.
C-Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a
borrow in case of subtraction.
16
AC-Auxiliary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e. bit three,
during addition or borrow for the lowest nibble, i.e. bit three, during subtraction.
O-Overflow Flag: This flag is set, if an overflow occurs, i.e. if the result of a signed operation
is large enough to be accommodated in a destination register. For example, in case of the
addition of two signed numbers, if the result overflows into the sign bit, i.e. the result is of
more than 7-bits in size in case of 8-bit signed operations and more than 15-bits in size in case
of 16-bit signed operations, and then the overflow flag will be set.
The three remaining flags in the flag register are used to control certain operations of the processor.
These flags are different from the six conditional flags described above in the way they are set or
reset. The six conditional flags are set or reset by the EU on the basis of the results of some
arithmetic or logic operation. The control flags are deliberately set or reset with special instructions
you put in your program. The three control flags are the trap flag (TF), which is used for single
stepping through a program; the interrupt flag (IF), which is used to allow or prohibit the
interruption of a program; and the direction flag (DF), which is used with string instructions.
T-Trap Flag: If this flag is set, the processor enters the single step execution mode. In other
words, a trap interrupt is generated after execution of each instruction. The processor executes
the current instruction and the control is transferred to the Trap interrupt service routine.
I-interrupt Flag: If this flag is set, the maskable interrupts are recognized by the CPU,
otherwise, they are ignored.
D-Direction Flag: This is used by string manipulation instructions. If this flag bit is '0 the
string is processed beginning from the lowest address to the highest address, i.e. autoincrementing mode. Otherwise, the string is processed from the highest address towards the
lowest address, i.e. auto-decrementing mode.
2.2 Bus Operation

The 8086 has a common address and data bus. The address and data are time multiplexed, i.e.
address and data appear on this bus at different time intervals. Thus bus is commonly known as
multiplexed address and data bus. The multiplexed address and data bus provides the most efficient
17
use of pins on the processor while permitting the use of a standard 40-lead package. This
multiplexed address and data bus has to be demultiplexed externally with the use of latches and
the ALE signal provided by 8086. This bus can be buffered directly and used throughout the system
with address latching provided on memory and I/O modules or it can be demultiplexed at the
processor with a single set of address latches if a standard non-multiplexed bus is desired for the
system.
The control operation of 8086 is different in two different modes: minimum mode and maximum
mode. The 8086 provides some signals which have different meanings in minimum mode and
maximum mode. The minimum mode is used for a small systems with a single processor and
maximum mode is for medium size to large systems, which often include two or more processors.
2.3
Memory Segmentation
Even though the 8086 is considered a 16-bit processor, (it has a 16-bit data bus width) its memory
is still thought of in bytes. At first this might seem a disadvantage: Why saddle a 16-bit
microprocessor with an 8-bit memory? Actually, there are a couple of good reasons. First, it allows
the processor to work on bytes as well as words. This is especially important with I/O devices such
as printers, terminals, and modems, all of which are designed to transfer ASCII-encoded (7- or 8bit) data. Second, many of the 8086's operation codes are single bytes. Other instructions may
require anywhere from two to seven bytes. By being able to access individual bytes, these oddlength instructions can be handled. We have already seen that the 8086 has a 20-bit address bus,
allowing it to output 210, or 1,048,576, different memory addresses. As you can see, 524,288 words
can also be visualized.
As mentioned, the 8086 reads 16 bits from memory by simultaneously reading an odd-addressed
byte and an even-addressed byte. For this reason the 8086 organizes its memory into an evenaddressed bank and an odd-addressed bank.
With regard to this, you might wonder if all words must begin at an even address. Well, the answer
is yes. However, there is a penalty to be paid. The CPU must perform two memory read cycles:
one to fetch the low-order byte and a second to fetch the high-order byte. This slows down the
processor but is transparent to the programmer.
Two types of memory organizations are commonly used. These are linear addressing and
segmented addressing. In linear addressing the entire memory space is available to the processor
in one linear array. In the segmented addressing, on the other hand, the available memory space is
divided into chunks called segments. Such a memory is known as segmented memory. In 8086
system 1 Mbytes is divided into number of logical segments. Each segment is 64 Kbytes in size
and addressed by one of the segment registers. The 16-bit contents of the segment register gives
the starting/base address of a particular segment, as shown in Figure 2-6. To address a specific
memory location within a segment we need an offset address. The offset address is also 16-bit
wide and it is provided by one of the associated pointer or index register.
Note that for memory segmentation:
(a) The four segments can overlap for small programs. In a minimum system all four
segments can start at the address 00000H.
(b) The segment can begin/start at any memory address which is divisible by 16.
18
Advantages of memory segmentation

i) It allows the memory addressing capacity to be 1 Mbyte even though the address
associated with individual instruction is only 16-bit.
ii) It allows instruction code, data, stack, and portion of program to be more than 64
Kbyte long by using more than one code, data, stack segment, and extra segment.
iii) It facilitates use of separate memory areas for program, data and stack.
iv) It permits a program or its data to be put in different areas of memory, each time the
program executed i.e. program can be relocated which is very useful in
multiprogramming.
2.3.1 Generation of 20-bit Address

To access a specific memory location from any segment we need 20-bit physical address. The
8086 generates this address using the contents of segment register and the offset register associated
with it. Let us see how 8086 access code byte within the code segment.
We know that the CS register holds the base address of the code segment. The 8086 provides an
instruction pointer (IP) which holds the 16-bit address of the next code byte within the code
segment. The value contained in the IP is referred to as an offset. This value must be offset from
(added to) the segment base address in CS to produce the required 20-bit physical address.
19
The contents of the CS register are multiplied by 16. i.e. shifted by 4 position to the left by inserting
4 zeros bits and then the offset i.e. the contents of IP register are added to the shifted contents of
CS to generate physical address. As shown in Figure 2-7, the contents of CS register are 348AH,
therefore the shifted contents of CS register are 348A0H. When the BIU adds the offset of 4214H
in the IP to this starting address, we get 38AB4H as a 20-bit physical address of memory. This is
illustrated in Figure 2-7 (b).
We have seen that how 20-bit physical address is generated within the code segment. In the similar
way the 20-bit physical address is generated in the other segments. However, it is important to
note that each segment requires particular segment register and offset register to generate 20 bit
physical address.
2.3.2 Pointers and Index Registers

All segment registers are 16-bit. But it is necessary to put 20-bit address (physical address) on the
address bus. To get 20-bit physical address one more register is associated with each segment
register the way IP is associated with CS.
These additional registers belong to the pointer and index group. The pointer and index group
consists of instruction pointer (IP), stack pointer (SP), base pointer (BP), source index (SI) and
destination index (DI) registers.
Stack pointer (SP): The stack pointer (SP) register contains the 16-bit offset from the start of the
segment to the top of stack. For stack operation, physical address is produced by adding the
contents of the stack pointer register to the segment base address in SS. To do this the contents of
the stack segment register are shifted four bits left and the contents of SP are added to the shifted
result. If the contents of SP are 9F20H and SS are 4000H then the physical address is calculated
as follows.
20
BP, SI and DI can be used as general purpose registers. However, their main use is to hold the
16-bit offset of the data word in one of the segments.
BP: is used in stack segment instead of SP for accessing the stack using the based addressing
mode. In this case, the 20-bit physical stack address is calculated from BP and SS.
SI: can be used to hold the offset of a data word in the Data segment.
DI: can be used to hold the offset of a data word in the Extra segment during string instructions.
2.3.3 Default and alternate register assignments

Table 2.1 shows that some memory references and their default and alternate segment definitions.
For example, instruction codes can only be stored in the code segment with IP used as an offset.
Similarly, for stack operations only SS and SP or BP registers can be used to give segment and
offset addresses respectively. On the other hand, for accessing general data, string source, data
pointed by BX and BP registers; it is possible to use alternate segments by using segment override
prefix. See examples given after Table 2.1.
For the following examples we have assumed

CS= 1000H, DS=2000H, SS=3000H, ES=4000H, BP=0010H, BX=0020H, SP=0030H,
SI=0040H, DI=0050H
21
However, to understand the examples more clearly we have to introduce one example of 8086
instruction, MOV instruction.
MOV instruction
Simply stated, the MOV instruction copies data from one location to another. It has the following
format:
MOV destination, source ; copy source operand to destination
This instruction tells the CPU to move (in reality, copy) the source operand to the destination
operand. For example, the instruction "MOV DX, CX" copies the contents of register CX to
register DX. After this instruction is executed, register DX will have the same value as register
CX. The MOV instruction does not affect the source operand.
22
2.3.4 Segment override prefix

The segment override prefix allows the programmer to deviate from the default segment. The
segment override prefix is an additional 8-bit code which is put in memory before the code for the
rest of the instruction. This additional code selects the alternate segment register. The code byte
for the segment override prefix as the format 001XX110. The XX represents a 2 bits which are as
follows: ES=00, CS=01, SS=10 and DS=11. It is important to note that the segment override prefix
may be added to almost any instruction in any memory addressing mode.
2.4 Review Questions

1. Explain the functions of the EU and the BIU.
2. What is pipelining, and how does it make the CPU execute faster?
3. Registers of the 8086 are either __ bits or __ bits in length.
4. List the 16-bit registers of the 8086.
5. Explain the architecture of 8086 processor with the help of neat block diagram.
6. What is the instruction queue? Explain its advantage.
7. What are segment registers? Explain the purpose of them.
8. Explain the purpose of pointers and index registers.
9. What is the function of flag register?
10. How physical address is generated in 8086?
11. Draw the bit pattern for flag register of 8086 and explain the significance of each bit.
12. What are the advantages of using memory segmentation?
13. What are the functions of SI and DI registers?
14. What does "8-bit" or "16-bit" microprocessor mean?
15. State another way to increase the processing power of the CPU other than increasing the
frequency.
16. Which of the following registers cannot be split into high and low bytes?
a) CS
d) SS
g) CX
b) AX
e) BX
h) SI
c) DS
f) DX
i) DI
17. If CS = 3499H and IP= 2500H, find:

a) The logical address
c) The lower and upper ranges of
b) The physical address
the code segment

23
18. If DS = 3499H and the offset= 3FB9H, find:

a)
The physical address
b)
The logical address of the data being fetched
c)
The lower and upper range addresses of the data segment
19. Assume that the physical address for a location is 0046CH. Suggest a possible logical
address.
20. If an instruction that needs to be fetched is in physical memory location 389F2H and CS
= 2700H, does the code segment range include it or not? If not, what value should be
assigned to CS if the IP must be= 1282H?
21. What is the main disadvantage of the stack as temporary storage compared to having a
large number of registers inside the CPU?
22. If SS= 2000 and SP= 4578, find:
a)
The physical address
b)
The logical address
c)
The lower range of the stack segment
d)
The upper range of the stack segment
23. The following registers are used as offsets. Assuming that the default segment is used to
get the logical address, give the segment register associated with each offset.
a) BP
c) IP
e) SP
b) DI
d) SI
f) BX
24. Show the override segment register and the default segment register used (if there were
no override) in each of the following cases.
a) MOV SS:[BX], AX
c) MOV DX, DS:[BP+6]
b) MOV SS:[DI], BX
25. Find the status of the CF, PF, AF, ZF, and SF for the following operations.
a) MOV BL,9FH
ADD AL, 97H
ADD BL, 61H
c) MOV DX, 10FFH
b) MOV AL, 23H
ADD DX, 1
24

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MICROCOMPUTER AND

COMPILED BY DEMISEW TEFERI

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Internal working of computers

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

1.2 History of Microprocessors

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

1.3 Evolution of the Intel processors

The Start of microprocessor (Intel 4004)

Intel 8008, 8080 Microprocessors

Intel 8085 Microprocessor

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Evolution from 8080/8085 to 8086

Evolution from 8086 to 8088

Success of the 8088

Other microprocessors: the 80286, 80386, and 80486

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

1.4 Review Questions

How many bytes is 24 kilobytes?

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

2.1 Intel 8086 CPU ARCHITECTURE

2.1.1 Bus Interface Unit (BIU)

It sends address of the memory or I/O.

2.1.2 Execution Unit (EU)

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

2.1.3 Instruction Queue

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering

Academic Year: 2014/15

Compiled by Demisew Teferi

Hawassa University, Institute of Technology, School of Electrical and Computer Engineering