EEE248/CNG232 Logic Design – Fall 2020 HW3

Homework #3

(100 pts.) Due on December 5th before the lecture.

1. (20 pts.) Mod-4 counter is a sequential circuit that has two flip-flops A and B and one
input x. It consists of a combinatorial logic connected to the D flip-flops, as shown in
Figure below. Analyze the circuit:
a. (8 pts.) Derive the next state and output equations.
b. (8 pts.) Derive the state table of the sequential circuit.
c. (4 pts.) Draw the corresponding state diagram.

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EEE248/CNG232 Logic Design – Fall 2020 HW3

2. (24 pts.) The state diagram of a sequence detector which allows overlap is shown
below. A sequence detector accepts as input a string of bits: either 0 or 1. Its output
goes to 1 when a target sequence has been detected. In a sequence detector that
allows overlap, the final bits of one sequence can be the start of another sequence.
Using the state diagram given below and an input sequence 10110:
a. (4 pts.) Assign binary values to the states and derive the state table.
b. (8 pts.) Derive the simplified state equations.
c. (10 pts.) Use JK flip-flops and design a synchronous sequence detector
circuit.
d. (2 pts.) Is this a Mealy or Moore model?
Treat unused states as don’t care conditions.

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EEE248/CNG232 Logic Design – Fall 2020 HW3

3. (20 pts.) Design the sequential circuit specified by the state diagram depicted below
using T flip-flops.

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EEE248/CNG232 Logic Design – Fall 2020 HW3

4. (12 pts.) Given the sequential logic circuit below, complete the timing waveforms for
the outputs, assuming the storage elements have zero propagation delays. Initial
values of OUTA and OUTB are both logic ‘0’ as shown.

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EEE248/CNG232 Logic Design – Fall 2020 HW3

5. (14 pts.) Use rising edge triggered D-type Flip-Flops and any number and type of
combinational gates and building blocks, in order to design a 4-bit universal shift
register, for which a specification is provided below. Show the schematic of your
design CLEARLY with inputs CLK, CLEAR_B, S1, S0, LEFT_IN, RIGHT_IN, D[3:0], and
outputs Q[3:0].
Control Example to demonstrate the Next State when
S[1:0] Operation the Present State of the universal shift Register
is 0110

00 Hold 0110

01 Shift Right 0011

10 Shift Left 1100

11 Load new value D[3:0] D[3:0] – 4 bit input

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EEE248/CNG232 Logic Design – Fall 2020 HW3

6. (10 pts.) A new type of flip-flop called “G-flip-flop” is given below:

a. (6 pts.) Find the simplified characteristic equation of this G-flip-flop.

b. (4 pts.) Fill in the following excitation table for G flip-flop.

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