Reliability of Segmented Edge Seal Ring for RF Devices

J.P. Gambino, R.S. Graf, J.C. Malinowski, A.R. Cote, W.H. Guthrie, K.M. Watson,
P.F. Chapman, K.K. Sims*, M.D. Levy, T. Aoki**, G.A. Mason***, M.D. Jaffe

IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452, USA
* Global Foundries, Malta, NY 12020, USA
** IBM Yamato Laboratory, Kanagawa 242-8502, Japan
*** IBM Microelectronics, Bromont, QC, Canada

ABSTRACT into the voltage-controlled oscillator (VCO), causing spectral

RF devices are sensitive to noise coupling between
devices. One source of coupling is the edge seal ring. We
propose using a segmented guard ring to reduce coupling
between devices. We demonstrate that the segmented guard
ring is reliable for a 0.18 µm RF technology.
INTRODUCTION
spreading of the RF signal [3] (Fig. 1b).
One source of noise in RF circuits is the edge seal ring
[4,5]. The edge seal ring provides a wall of metal that
surrounds the die, and protects the die from cracks, moisture,
and mobile ion contamination [4-6] (Fig. 2). However,
noise from a power or signal line can propagate through the
edge seal ring, and adversely effect noise-sensitive devices
(Fig. 3a).

Recently, CMOS SOI and SiGe BiCMOS technology Polyimide

have replaced GaAs for the switches and power amplifiers in
mobile devices [1]. Silicon technology can provide Si3 N4
M4
Al

comparable performance to GaAs with reduced system cost SiO2

and smaller form factor. One challenge with silicon RF M3 Cu

circuits is minimizing signal coupling between devices. An
example of where coupling can cause problems is in the crack
M2 Al

transmitter circuit of the front end module (Fig. 1) [2,3]. M1 Cu

Na+
BPSG
N+ N+ STI PWell STI
Antenna
Mixer
PA
Active devices Edge seal Scribe line
BPF LPF DAC DSP
RF RF RF IF IF Fig. 2. Schematic cross-section of edge seal ring.

(a) coupling Edge seal Scribe line Edge seal Scribe line
LO
(a) (b)
LO
(b) wirebond wirebond
DC IF RF

spur spur
FET FET
gap
fIF fRF fLO
Frequency

Fig. 1. (a) Schematic of RF transmitter circuit, showing digital signal
processor (DSP), digital-to-analog converter (DAC), low pass filter (LPF),
local oscillator (LO), power amplifier (PA), and band pass filter (BPF). (b)
The signal from the power amplifier can couple to the local oscillator,
resulting in sideband spurs in the spectrum of the local oscillator [2,3].
The transmitter circuit takes the intermediate frequency (IF)
baseband signal and superimposes it onto an RF carrier,
which can be more easily radiated into space [2]. However,
Fig. 3. Top-down schematic of edge seal ring. (a) Continuous edge seal
ring, Noise from power or signal pad can propagate through edge seal ring
and effect sensitive devices. (b) Segmented edge seal ring.
Recently, it has been proposed to put gaps in the edge seal
ring, thereby forming a “segmented” edge seal ring [4,5].
The discontinuous edge seal ring prevents noise propagation
(Fig. 3b). In this study, we report on the reliability of a 0.18
11

µm CMOS devices with a segmented edge seal ring, testing

the transmitted signal from the power amplifier can couple for ionic contamination and for crack propagation.

978-1-4799-5018-8/14/$31.00 ©2014 IEEE 367

 EXPERIMENT dicing damage. The modules were stressed using the same
conditions as for the ionics test (i.e., HTS, T/C, HAST).
The test structures for ionic contamination were bulk Leakage and continuity were measured at time zero and then
pFETs, with a 3.5 nm thick gate dielectric, built with a again after the stress.
0.18µm BiCMOS technology [7.8]. The pFETs were placed
gap
outside of the guard ring, directly adjacent to the dicing
channel, as a worst case layout for ionic contamination. (a) (b)
Some pFETs were also placed inside the edge seal ring as
controls. The BEOL consists of 6 levels of metal in an SiO2
dielectric; Cu (with an SiN capping layer) is used at M1, gap gap
M4, and M5; Al is used at M2 and M3, and M6. The die gap
were built into modules using a wirebond, quad flat no-lead
(QFN) package. The mold compound has typical impurity
concentrations of 1 ppm Na+ and 5 ppm Cl-.
M2 Via Edge Dicing
The QFN modules went through a preconditioning step, pair chain seal channel
that simulates solder reflow (260oC anneal, run three times). gap

The stresses consist of the following: High temperature

storage (HTS); 150oC, 1000 hr; Thermal cycle (T/C); -
55oC to +125oC, 1000 cycles; and a high accelerated stress
test (HAST); 110oC, 85% RH, 3.6V, 246 hr. The sample
size consisted of 48 devices for each stress.
After these stresses, the threshold voltage (Vt) of the
pFETs was measured at 30oC, at time zero, after negative
gate bias stress (to attract mobile ions to the gates) and again
after positive gate bias stress (to repel mobile ions from the
gates). The fail criteria was a Vt shift of over -5 mV after
the negative bias test (Na+ in the gate will shift the Vt to a
more negative value).
The test structures for crack propagation were built using
Fig. 5. Layout of test structures for evaluation of crack propagation. (a)
View of entire die showing gap in edge seal ring along each edge. (b) View
of the gap in the edge seal , via chain, and M2 perimeter lines. (only M2
and M4 levels are shown).
RESULTS AND DISCUSSION
Ionic contamination was monitored by measuring the shift
in Vt of the pFETs after each of the stresses (HTS, T/C,
HAST). An example of the data, after thermal cycle stress,
is shown in Fig. 6. The delta Vt (change in Vt compared to
time zero) is less than -2 mV all in all cases, indicating that
there is no significant mobile ion contamination.

+0.5V
+0.5V
-1.8V
a 0.18µm SOI technology [9]. The BEOL consists of 4

-1.8V
Vgs
levels of metal in an SiO2 dielectric; Cu (with an SiN 4
capping layer) is used at M1 and M3; Al is used at M2 and
M4 (Fig. 4). The test structures consist of stacked via chains
Delta Vt (mV)

0
M4 Al

W -2
M3 Cu SiN

W SiO2 -4
M2 Al

1 2 4 10 20
M1 Cu
5 µm Stress time (sec)
Si

Fig. 4. SEM cross-section of gap in edge-seal ring.
(to measure continuity) and pairs of metal lines (to measure
continuity and leakage) that are placed just inside the edge
seal ring. The edge seal ring has a gap on each edge of the
die, at the mid-point of the die edge (Fig. 5). The die size is
5 mm x 5 mm. The wafers were thinned to 150 µm, then
modules were built in a flip-chip, chip scale package, with
Pb-free solder bumps and a molded underfill. In some cases,
the dicing was modified from standard conditions, using a
process that enhanced edge chipping, to provide worst case
Fig. 6. Cumulative delta Vt for pFET devices, both inside and outside the
edge seal ring, after thermal cycle stress. The delta Vt is first measured
after a negative gate bias (to attract mobile ions to the gate), then measured
again after a positive gate bias (to repel mobile ions from the gate.
Historically, edge seal rings were required to prevent
mobile ions from entering the device region. So why is there
no mobile ion contamination detected in this study? One
reason is that the materials used in IC fabrication and
assembly have improved over time, with lower mobile ion
concentrations. For example, the Na+ concentration in
molding compounds is typically 2 ppm or lower [10]. In

368
addition, modern integrated circuits already have a number
of mobile ion barriers as part of the BEOL stack, including
SiN or SiCN capping layers on top of Cu interconnects, and
BPSG or PSG premetal dielectric. Therefore, the edge seal
is a “redundant” mobile ion barrier, and is not required if
there are sufficient barriers in the BEOL stack.
The electrical data for via chains and perimeter lines is
shown in Table I. Some continuity fails are observed with
the non-optimized dicing process after preconditioning, with
some additional fails after the thermal cycle stress. These
fails are observed for both the continuous and segmented
edge seal rings. No fails are observed for any of the test
structures when using optimized dicing conditions.
Table I. Cumulative percentage of fails for continuity tests after stress.
Edge seal ring dicing Precon DTC HAST HTS
fails (%) fails (%) fails (%) fails (%)
none Non-optimized 2 1.6 0 0
continuous Non-optimized 1.3 0.7 0 0
segmented Non-optimized 0.7 0 0
continuous optimized 0 0 0 0
segmented optimized 0 0 0 0
Optical microscope inspections reveal minimal top-edge
chipping with optimized dicing and a large amount of top-
edge chipping for non-optimized dicing (Fig. 7). With non-
optimized dicing, the cracks occasionally propagate through
(a) (b)
100 µ m
Fig. 7. Top-down optical micrograph of diced chip edge for (a) optimized
dicing and (b) non-optimized dicing with top edge chipping (arrows).
gap
Fig. 8. Top-down optical micrograph of top-edge chipping with non-
optimized dicing. Note that crack stops at edge seal ring..
the edge seal, and can cause a continuity fail. Inspection of
the gaps in the edge seal showed that edge chipping never
penetrated the gaps (Fig. 8 and 9). Dicing damage in silicon
and in SiO2 is in the form of radial cracks [11].
gap
edge seal
cracks
Dicing edge 20 µm
Fig. 9. Top-down SEM of top-edge chipping with non-optimized dicing.
Note that the cracks in BEOL dielectric stop at the edge seal.
Assuming the edge seal remains intact during dicing, a crack
can only propagate into the device region if the radius of the
crack is smaller than the gap in the edge seal ring (Fig. 10).
In this study, the radius of the cracks is on the order of 50
µm, and the gap in the edge seal ring is 5 µm. Hence,
cracks do not propagate through the gap.
0
(a) (b)
device region edge seal
5 µm
50 µm
radial crack dicing edge
Fig. 10. Top-down schematic of radial crack propagation; (a) radius of
crack > gap in edge seal, and (b) radius of crack < gap in edge seal.
CONCLUSION
In this study, the reliability of a segmented guard ring has
been evaluated, testing for mobile ion contamination and for
crack propagation from dicing damage. We demonstrate that
the segmented guard ring is reliable for a 0.18 µm RF
technology with Cu interconnects in SiO2 dielectric. . .
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