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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Design of Low-Power Sub-2.4 dB Mean NF 5G
LNAs Using Forward Body Bias
in 22 nm FDSOI
Omar El-Aassar , Graduate Student Member, IEEE, and Gabriel M. Rebeiz, Fellow, IEEE
Abstract— This article presents K/Ka-band low-noise-ampli-
fiers (LNAs) for 5G front ends. The use of forward body
bias (FBB) in fully depleted silicon-on-insulator (FDSOI) devices
is studied and utilized to improve the LNA performance under
reduced supply voltage and dc power ( Pdc ). Design procedures
targeting high linearity, low noise, and high gain are pro-
vided. The two-stage common-source LNA (CS-LNA) achieves
sub-2.1 dB mean NF, 20.1 dB peak gain, 9 GHz 3 dB band-
width (BW) from 19.5 to 28.5 GHz, and an in-band IIP 3 of 0 dBm
with 9.6 mW Pdc . The single-stage cascode LNA (CAS-LNA)
achieves over 10 dB gain, 11 GHz 3 dB BW, and an IIP3
of 7.5 dBm for a 2.2 dB mean NF. The two-stage CAS-LNA
has 28.5 dB peak gain, 4 GHz BW, and 2.25 dB mean NF for
20 mW Pdc . In the low-power mode, the CS-LNA operates at
0.4 V with Pdc of 3.2 mW, 16.9 dB gain, and less than 2.2 dB
mean NF, while the two-stage CAS-LNA achieves 2.4 dB NF
and 23 dB gain for 5.5 mW. Also, ultralow-power operation and
sub-3 dB NF are possible with the CS-LNA at 0.2 V/1 mW with
12 dB gain and for the CAS-LNA at 0.4 V/2.4 mW with 17.7 dB
gain. To the best of our knowledge, the single-stage CAS-LNA
shows the highest IIP3 at 28 GHz compared with the published
CMOS work. The two-stage FBB CS and CAS designs have the
lowest voltage supply, Pdc , and best Figure of Merit (FoM) for
mm-waves 5G LNAs in the low-power mode.
Index Terms— FDSOI CMOS, 5G, low-noise amplifier (LNA),
millimeter-waves integrated circuits, ultralow voltage/power.
I. I NTRODUCTION
T HE low-noise amplifier (LNA) is a critical block in the
5G front-end since it dominates the NF of the receive
channel. The NF values for silicon-based K/Ka-band LNAs
are 2–5 dB with dc power ranging from 13 to 80 mW [1]–[8].
The lowest reported NF values are 1.4–1.5 dB for 28 GHz
CMOS-SOI LNAs with 13 dB gain and 10–15 mW [9], [10].
This work presents a detailed guideline for LNA design in the
mm-wave range in a deeply scaled technology node. The focus
is to provide optimization procedures for the devices, passives,
and topologies that yield state-of-the-art designs while show-
ing the voltage-supply and technology-scaling, noise, power,
and linearity tradeoffs.
Manuscript received March 27, 2020; revised May 16, 2020; accepted
June 10, 2020. This work was supported in part by Analog Devices and
in part by Qualcomm. (Corresponding author: Omar El-Aassar.)
The authors are with the Electrical and Computer Engineering Department,
University of California at San Diego, La Jolla, CA 92093 USA (e-mail:
oelaassa@eng.ucsd.edu; rebeiz@ece.ucsd.edu).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2020.3012538
0018-9480 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1
In particular, the forward body bias (FBB) in FDSOI is
exploited to improve the LNA performance under low supply
conditions. The effect of FBB is investigated in detail for
the common-source (CS) and cascode (CAS) topologies, and
optimal bias is used for low-power designs. It is shown that
the FBB improves the linearity by reducing the device output
channel conductance variation under scaled power and supply.
Measurements across power levels and FBB bias are per-
formed to provide an insight on the NF, gain, bandwidth (BW)
trends, and Figure-of-Merit (FoM) scaling with reduced Pdc .
Also, we present three K/Ka-band LNAs targeting high lin-
earity, low noise, and high gain. A one-stage CAS-LNA with
+7.5 dBm in-band IIP3 at 28 GHz is designed using a stacked
topology with FBB. The scaling of the CAS gate capacitor
is studied and used to improve the linearity, matching, and
stability without degrading the NF. A 20 dB gain, two-stage CS
design achieves <2.1 dB mean NF with a +2.6 dBm in-band
IIP3 and an FoM >25 dB. This design can also operate at
<0.2 V supply and achieve >30 dB FoM when using the
FBB. The third design achieves 28.5 dB peak gain when
using a two-stage CAS topology while ensuring unconditional
stability.
II. T ECHNOLOGY AND D EVICE S ELECTION
The minimum noise figure (NFmin ) for a MOS device can
be expressed as [11], [12]

NFmin = 1 + K gm(RG + R S ) ×
f
(1)
fT
where gm is the device transconductance, RG and R S are the
gate and source resistances, respectively, f is the operating
frequency, and f T is the unity current gain frequency. CMOS
technology scaling allows for higher f T and lower threshold
voltage (VT ) resulting in lower noise and power consumption
for the LNAs. However, this can be problematic at sub-28 nm
nodes due to the short-channel effects that can lead to bulk and
surface punchthrough across the source and drain depletion
regions [13]. Also, intrinsic device gain deteriorates rapidly
due to the drain induced barrier lowering (DIBL) [14].
Partially and fully depleted SOI MOS devices and FinFETs
are currently used for further scaling. In fully depleted SOI,
the bulk can be biased to control VT and improve the device
RF performance or save power. The lack of parasitic diodes
in the 22 nm FDSOI technology allows a VT control range
of ≈150 mV when the body bias is swept from 0 to 2 V and
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2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 2. (a) Simulated NFmin versus frequency for a 60 μm nMOS with

different gate PP and multiplier cells (M). (b) Z in and Z opt trajectories on the
Smith chart for the chosen 60 μm nMOS at 28 GHz.

satisfy the noise matching at a lower Pdc at the expense of

Fig. 1. (a) Schematic of a CS inductive degenerated LNA. (b) Z in and Z opt
variations with the device size. Simulated device noise performance at 28 GHz
for several device widths. NFmin versus (c) current density J D and (d) power
consumption Pdc for VDD = 0.8 V.
results in a sensitivity for body bias control −75 mV/V, which
is ideal for robust trimming. The effect of the body bias on
the LNA performance is one of the main goals of this article.
III. L OW-P OWER /L OW-N OISE D ESIGN
A. CS Design
Simultaneous noise and power matching for an inductively
degenerated LNA is typically achieved by increasing the
device size and biasing the transistor at the optimum cur-
rent density for minimum noise (JD,NF ), in order to bring Z opt
to the 50  circle [see Fig. 1(a)] [15]–[17]. Z opt is defined
as the optimum source impedance yielding a minimum NF
for the device. A source inductor (L S ) is then used to reduce
the real part of the input impedance (Z in ) and bring it close
to 50 . A gate inductor (L G ) is finally added to resonate
the capacitance of Z in and match the input to 50 . This
technique, however, penalizes power consumption in deeply
scaled nodes as the real component of Z opt is [1]
 and results in NFmin ≈ 0.66 dB after parasitic extraction to
RG fT
Re[Z opt ] ≈ × . (2)
2gm f single multiplier/relaxed pitch design.
When biasing the device at JD,NF , Re[Z opt ] can be expressed
in terms of the power consumption (Pdc ) as
 are chosen to bring Z in to Z opt in the best noise circle [see
RG Vod VDD fT
Re[Z opt ] ≈ × (3)
4Pdc f
where Vod is the overdrive voltage (Vgs − VT ) to achieve
JD,NF irrespective of the device size. Therefore, a higher
Pdc is needed to bring Re[Z opt ] close to 50  for high
f T technologies. An increase in the channel length or the
addition of an extrinsic gate-to-source capacitance (CGS ) can
f T reduction and, thus, NF degradation (1). Fig. 1(b) shows
the plots of Z opt and Z in when scaling the device size for
different L S values. A Re[Z opt ] = 50  is achieved for
a 120 μm device at 28 GHz, and simultaneous noise and
power matching is satisfied at 20 mW from a 0.8 V VDD [see
Fig. 1(c) and (d)]. A power-conservative approach can also be
achieved by selecting a device size of 60 μm to reduce the
power by half while ensuring 50 < Re[Z opt ] < 100  for an
input matching <−10 dB.
The device layout optimization is also studied to mini-
mize RG . The finger width (Wfing ) should be designed small
enough to minimize the horizontal poly gate resistance but
large enough to minimize the vertical component. Simula-
tions show that a 0.5 μm Wfing achieves a minimum NFmin
of 0.52 dB, at 28 GHz, prior to upper metals routing. NFmin
varies by <0.02 dB when Wfing is increased to 1 μm. A 1 μm
finger is, thus, chosen to minimize routing parasitics.
The 22 nm FDSOI technology offers different values for
the gate poly-to-poly pitch (PP). The relaxed pitch (3xPP =
312 nm) reduces the fringing capacitance and the drain and
source routing resistances and is usually favored in power
amplifiers designs. The narrow pitch (1xPP = 104 nm) reduces
gate metal routing resistance and is selected for the LNA. The
simulated NFmin of the 60 μm nMOS is plotted versus the
frequency for relaxed and narrow poly-pitches and different
numbers of multiplier cells (M) [see Fig. 2(a)]. An optimum
number of multipliers M = 4 reduces metal routing resistance
the top metal layer compared with NFmin = 1.36 dB for the
Once the device size and layout are determined, the noise
circles are plotted for the extracted design, and L G and L S
∗
Fig. 2(b)].
B. CAS Design
The CAS-LNA benefits from the transimpedance gain of
the added common-gate (CG) amplifier to increase the output
impedance and overall power gain. A high output impedance
provides the flexibility of using several CAS stages with high

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EL-AASSAR AND REBEIZ: DESIGN OF LOW-POWER SUB-2.4 dB MEAN NF 5G LNAs USING FBB
Fig. 3. (a) Schematics of inductive degenerated LNAs using series-peaked
CAS and stacked configurations. The Smith chart impedance trajectories from
20 to 30 GHz for Z in , Z opt , and Z out . (b) CS versus CAS configurations.
(c) CAS versus series-peaked CAS configurations. (d) CAS versus stacked
configurations. (Note that only the stacked configuration is able to restore the
output matching BW and input noise matching of a CS topology).
impedance interstage matching for higher gain but at the
expense of BW [1], [18]. The CAS also improves the reverse
isolation by alleviating the Miller effect.
Several concerns are addressed for mm-wave 5G cascode
LNAs (CAS-LNAs), namely, the BW limitation for a single
stage, the LNA stability, and the noise contribution of the CAS
device. Fig. 3(b) presents the BW limitation by plotting the
output impedance (Z out ), Z in , and Z opt , from 20 to 30 GHz,
for equally sized CS and CAS-LNAs. The CAS topology
reduces the effective input capacitance while having little
impact on Z opt . More important is the Z out increase, requiring
a higher-Q matching network to bring it to 50 .
Two techniques are, therefore, considered to improve the
BW: series-peaked CAS and stacked configurations [see
Fig. 3(a)]. The inductance of a series-peaked CAS (L S P )
resonates the intra-stack capacitance and peaks gm for higher
gain and results in a reduced CAS noise contribution, while the
zero introduced by the series peaking allows for BW extension
[see Fig. 3(c)]. However, L S P also translates through the CS
C G D and creates a negative real component reducing Re[Z in ],
while Z opt remains the same. An increase in L S is therefore
mandatory to recover the noise matching condition. A larger
L S is usually accompanied by gain and NF degradation
considering its finite Q as in (1).
The stacked configuration allows for a voltage swing at the
gate of the CAS device by proper scaling of C G,CAS leading
to a reduced gm and Z out [see Fig. 3(d)]. A similar reduction
in gm and Z out can be achieved by choosing a smaller CAS
device. However, the stacking technique enables an equally
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3
Fig. 4. Simulated small-signal operation across the frequency for a stacked
LNA for different C G,CAS values. (a)–(d) S-parameters. (e) NF. (f) Stability
factor k-factor.
sized CAS, compared with the CS, also biased at JD,NF to
minimize its noise contribution.
Fig. 4 compares the stacked and traditional CAS topologies
in terms of gain, matching, noise, and stability. A stacked
topology with C G,CAS = 30 fF improves the matching, isola-
tion, and 3 dB BW and renders the LNA unconditionally stable
for the 60 μm device size [see Fig. 4(a), (b), (d), and (f)]. The
gain penalty is 4.5 dB compared with the CAS-LNA [see
Fig. 4(c)], while the NF is within 0.05 dB [see Fig. 4(e)].
Compared with a CS-LNA, the CAS design has 0.3 dB higher
NF at 28 GHz due to the noise contribution from the CG
transistor.
IV. FBB FOR L OW-P OWER LNAs D ESIGN
The FBB is previously used in sub-6 GHz bulk CMOS
designs with a ≈0.5 V tuning range limited by the forward bias
of the bulk–source junction. The FBB is used in nMOS [19],
CAS [20], CMOS [21], and folded topologies [22] to reduce
the power consumption and improve the gain and output
conductance for reduced supply of operation. The FBB is also
used at 60 GHz in bulk CMOS as a linearizer device in parallel
with the gm-cell to improve the IIP3 at the expense of NF [23].
Recently, the FBB is exploited in fully depleted SOI up to 2 V
for a 5G 22–32 GHz LNA to provide a less sensitive dc power
control knob in addition to the gate bias voltage [4], [24].
In this work, we aim to study the effect of FBB on the gain,
NF, and IIP3 for CS and CAS topologies across frequency and
power level in the 22 nm FDSOI technology.
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4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 5. Simulated small-signal operation of a body-biased CS nMOS for nominal (0.8 V) and reduced (0.3 V) VDD at 28 GHz. (a)–(c) gm, MAG, and NFmin
versus the current density. (d) and (e) gm 3 and gm 5 variation versus the gate bias. (f) Layout of the body-biased nMOS transistor.

Consider the 60 μm nMOS CS with FBB where the device
is split into four multipliers to reduce RG (see Fig. 5). The
FBB in 22 nm FDSOI reduces VT from 320 to <50 mV
when sweeping the FBB from 0 to 4 V with a sensitivity
of ∼−76 mV/V. The gm, maximum available gain (MAG),
and NFmin are plotted at 28 GHz versus JD for the nominal
(0.8 V) and reduced VDD (0.3 V) in Fig. 5. A minimum NFmin
is achieved at JD,N F ≈ 0.1–0.15 mA/μm for all voltages.
At this bias point, the simulated gm and MAG at 28 GHz
are nearly the same for both the nominal and reduced VDD
conditions with a slight NFmin degradation. This shows that
one can design low-power mm-wave LNAs without trading
gain and NF.
The FBB also improves the band flatness of gm and MAG at
high JD values, and this can be exploited in power amplifiers
to improve their linearity. Fig. 5(d) and (e) shows the second
and fourth derivatives of gm (gm 3 and gm 5 ) for the nominal
and reduced VDD conditions. The optimal biasing primarily
depends on JD and, thus, is nearly constant for different device
sizes and VDD values. The FBB can manipulate gm 3 and
gm 5 to bias around the sweet-spot for improved IIP3 [see
Fig. 5(d) and (e)]. This can also be achieved by changing
the gate-to-source voltage (VGS ), however, with much higher
sensitivity compared with FBB control that has approximately
ten times less gm compared with the gate node. The FBB can,
thus, be used to trim for better IIP3 in the output stages of
an LNA.
Fig. 6 presents results for an nMOS CAS with 60 μm width
for the CG and CS devices. The body of the lower CS is
grounded since it does not affect the performance at JD,NF ,
while the body of the CG device is left as a tuning knob.
The simulated gm, MAG, and NFmin at 28 GHz are plotted
versus JD for a reduced VDD of 0.5 V and compared with the
single CS in Fig. 5(f) for the same Pdc [see Fig. 6(a)–(c)]. At
JD,NF , the reduced CS headroom in the CAS design limits gm
and degrades NFmin (0.7 dB higher than the CS design), while
MAG is increased due to the high CAS impedance. Applying
FBB reduces VGS of the CG device leading to a higher
headroom and gm and less NF for the CS device. When the
FBB is increased to 4 V, the CG enters into the triode region
under limited supply, thus reducing its transimpedance gain
and lowering MAG, but gm of the CS keeps improving due to
the higher headroom and this improves NFmin . At the optimum
FBB, the CAS can provide ∼9 dB MAG improvement over
the CS in exchange with 0.3 dB NFmin degradation for the
same Pdc and nearly the same chip area. The FBB of the CG
device can also manipulate the effective gm 3 and gm 5 of the
structure at low VDD operation with little change in JD and
lower sensitivity than its gate bias [see Fig. 6(d) and (f)].
For high-gain designs, the LNA linearity can be limited
by the output channel conductance (gds ) rather than gm . This
output linearity limitation is usually dominant for low VDD
designs with reduced headroom for the RF swing. Fig. 7(a)
presents the derivative gds3 for the CAS across VDD for three
values of the FBB. A higher FBB value reduces gds3 for a
given supply. Notably, the FBB improves the CAS output
linearity for a fixed Pdc [see Fig. 7(b) and (c)]. This is because
the current, primarily controlled by the CS device, is weakly
dependent on VDD , while a lower VT for the CAS device
increases the output headroom of the CS for a fixed VDD .
Therefore, the FBB can be exploited to improve IIP3 for
output-limited LNAs without incurring a power penalty.

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EL-AASSAR AND REBEIZ: DESIGN OF LOW-POWER SUB-2.4 dB MEAN NF 5G LNAs USING FBB 5

Fig. 6. Simulated small-signal operation of a body-biased CAS compared with a CS with equal Pdc for VDD = 0.5 V at 28 GHz. (a)–(c) gm, MAG, and
NFmin versus the current density. (d) and (e) gm 3 and gm 5 variation versus the CS gate bias. (f) Layout of the CAS with a body-biased CG transistor.

Fig. 7. Simulated small-signal output channel performance for a body-biased CAS at 28 GHz. (a) Channel conductance second derivative gds3 versus VDD .
(b) and (c) gds3 and gds5 versus power consumption Pdc for different CAS body bias voltages revealing output linearity improvement for a given Pdc when
using the FBB.

V. I MPLEMENTATION
Three different mm-wave LNAs (one-stage CAS, two-
stage CS, and two-stage CAS) were fabricated in Glob-
alFoundries 22 nm FDSOI with a core area of 0.12 and
0.19 mm2 , respectively, for the single- and two-stage designs
(see Fig. 8). The one-stage CAS design targets high linearity
and broadband operation with >10 dB gain and >10 GHz
3 dB BW [see Fig. 8(a)]. Note that C1 is reduced to 30 fF,
and this allows some RF swing on the stacked device gate
and improves the output linearity at the expense of gain. The
two-stage CS is designed for minimum NF while achiev-
ing >20 dB gain and sub-10 mW operation [see Fig. 8(b)].
The size of M2C S is 25% lower than M1C S to increase its input
impedance for gain and save power. The two-stage CAS-LNA
aims for >25 dB gain with unconditional stability and low NF
[see Fig. 8(c)]. The two-stage design allows sufficiently high
reverse isolation such that C1 is increased to 95 fF for the first
stage and an ac grounded gate for the second stage CAS device
to improve the gain. For all designs, the ac coupling capacitor
COUT and the routing inductor L OUT are designed with L D to
provide a 50  match at the output pad. Thin-oxide nMOS
with a minimum channel length (L eff = 17 nm) is used for
minimum NF and maximum gain. The body of the input device
(M1C S ) is grounded since it does not affect the gain and NF
at JD = 0.1 mA/μm. The FBB is provided to the rest of the
devices using a low-pass filter.
The gate layout routing is used to form a small extra C gs
MOM capacitor while minimizing routing overlap with the
drain side (as mentioned in Section III, this improves the input
impedance match). M1C S is designed as four multiplier cells
with tight finger pitch (104 nm) for lower RG in exchange
for extra capacitance employed in the input matching. CAS
devices (MCG ) are designed with a relaxed finger pitch
(312 nm) for less drain and source routing resistance and

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6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 8. Schematics and die micrographs of the fabricated 5G LNAs with FBB in 22 nm FDSOI. (a) Single-stage CAS. (b) Two-stage CS. (c) Two-stage
CAS.

Fig. 9. (a) and (b) Post metal-fill EM-simulated inductances and the
corresponding quality factors (Q) for a single-stage CAS-LNA. (c) Back-end
metal stack cross section and 3-D layout view of the single-stage LNA
revealing the metal filling placement.
less overlap capacitance. In addition, a small negative coupling
between the gate and source of M1C S (k gs ≈ −0.07) increases
the effective Re[Z in ] while reducing the imaginary of Z opt ,
which is also lowered by increasing C gs and L S . The size of
L S can, thus, be reduced for higher gain and lower NF (for a
finite quality factor (Q L S ) case). This technique consumes the
same Pdc of the extrinsic capacitor method and yields better
gain and NF.
The passive structures are EM-simulated using integrand
EMX. Both L D and L S are implemented in the top two metal
layers (2.9 μm aluminum and 3 μm copper), while L G was
designed on the top layer alone to maximize its self-resonance.
A patterned ground plane is placed on the lower two metals
to shield the inductors from the low-resistivity substrate loss
(ρ ≈ 7  · cm). The EM-simulated Q values for L G , L D , and
L S are 9.1, 11.9, and 14, respectively, at 25 GHz (see Fig. 9).
Fig. 10. (a) EM-simulated Q for the gate inductance before and after metal
fill. (b) 3-D layout view.
The initial Q values before the mandatory metal fill are ∼ 30%
higher. Reducing the metal fill for the upper thick metals
directly below the winding is the most effective in lessening
the Q degradation [11]. In future designs, the inductor Q can
be enhanced by tying the top thick metals together for the
inductor winding at the expense of a reduced self-resonance
frequency. In this case, the peak Q for L G can be increased
from 9.1 to 14.5 at 20–30 GHz (see Fig. 10).
VI. M EASUREMENTS
The three LNAs are RF probed and tested using a vector
network analyzer (Keysight N5247A PNA-X) up to 40 GHz
(see Fig. 11). The measured peak gain for the one-stage
CAS design is 10.2 dB with a 3 dB BW of 21.6–32.8 GHz.
The power dissipated is 15 mW from a 1.6 V supply [see
Fig. 11(a)]. The input and output matchings are <−10 dB
from 26 to 34 and 26 to 31 GHz, respectively. The two-stage
CS achieves 20.1 dB peak gain with a 9 GHz BW from 19.5 to

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EL-AASSAR AND REBEIZ: DESIGN OF LOW-POWER SUB-2.4 dB MEAN NF 5G LNAs USING FBB 7

Fig. 11. Measured and simulated small-signal performance versus frequency for the three fabricated 5G LNAs. (a)–(c) S-parameters for the nominal operation:
VDD,C S = 0.8 V with 9.6 mW and VDD,CAS = 1.6 V with 15 mW for the single-stage design and 20 mW for the two-stage design. (d)–(f) k-factors. (g)–(i)
NF.

28.5 GHz with Pdc = 9.6 mW for the nominal 0.8 V supply.
The gain is >15 dB from 18.5 to 32 GHz, and the input
matching (S11 ) is <−10 dB in the range from 22.3 to 32.2 GHz
[see Fig. 11(b)]. The two-stage CAS achieves 28.5 dB peak
gain and 4 GHz BW from 23 to 27 GHz for the nominal
operating conditions (Pdc = 20 mW and VDD = 1.6 V)
[see Fig. 11(c)]. Compared with simulations, the matching
and peak gain frequencies are shifted down by ∼10% likely
due to underestimated inductors values and their parasitic
capacitances. It is important to note that an underestimated
parasitic capacitance only should yield a peak gain reduction
compared with simulations. A ground mesh distributed across
the chips reduces the ground inductance and yields a measured
stability factor >1 for the single-ended designs with gain up
to 28.5 dB [see Fig. 11(d) and (f)].
The measured and simulated NF for the three LNAs is
shown in Fig. 11(g)–(i) for the nominal operation. The mea-
sured mean NF of the one-stage CAS is 2.2 dB with a worst
NF < 2.5 dB up to 30 GHz. The two-stage CS demonstrates
a 2.1 dB mean NF within the 3 dB BW and with a minimum
of 2 dB, while the two-stage CAS design has a 2.25 dB mean
NF with a minimum of 2.2 dB (∼0.2 dB higher than the CS
LNA). The measured NF for the three LNAs is 0.3–0.5 dB
higher than the simulated values. The detrimental effect on
the inductors Q from the high-density metal fill is a possible
reason for this discrepancy.
The measured IP1 dB and in-band IIP3 are presented
in Fig. 12. The one-stage CAS achieves an IP1 dB /IIP3 >
−3.5/+7 dBm across the 3 dB BW. For the two-stage designs,
an IIP3 of +2.6 and −10.4 dBm is measured, respectively,
for the CS and CAS designs when FBB is applied. The
FBB enhances IIP3 of the one-stage CAS and two-stage CS
designs by ∼ 2.5 dB for the same power consumption due
to the linearity improvement of the output conductance. This
improvement is not visible for the two-stage CAS when the
gain of the input stage exceeds 10 dB. In that case, the IIP3
linearity is dominated by the swing at the input of the second
stage rather than its output [see Fig. 12(c)]. Therefore, the FBB
has little effect on the output stage linearity but can still be
used to control Pdc .
The operation at low power is studied by stepping down
VDD and remeasuring the gain, NF, and S11 (see Fig. 13).

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8 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 12. Measured linearity across frequency for the three fabricated LNAs: IP1 dB and IIP3 with and without FBB while fixing Pdc . (a) One-stage CAS with
9.6 mW. (b) Two-stage CS with 15 mW. (c) Two-stage CAS with 20 mW.

Fig. 13. Measured gain, NF, and S11 across frequency for different VDD values. (a), (d), and (g) One-stage CAS. (b), (e), and (h) Two-stage CS. (c), (f),
and (i) Two-stage CAS.

The FBB is used when VDD is ≤ 0.5 and ≤ 1 V for the CS and
CAS designs, respectively. All LNAs maintain the same gain
and matching shapes for a reduced VDD with the two-stage
CS-LNA, achieving 12 dB gain at 0.2 V, and the two-stage
CAS-LNA achieves 17.7 dB at 0.4 V when FBB is used [see
Fig. 13(b) and (c)]. For the two-stage designs, the measured
NF across the S21 3 dB BW is below 2.8 and 3 dB, respec-
tively, for the CS and CAS-LNAs using 0.2 and 0.4 V supplies
[see Fig. 13(e) and (f)]. This value increases to 3.6 dB for the
one-stage LNA due to the gain degradation to 4.8 dB [see
Fig. 13(a) and (d)]. The input matching for the CS-LNA was
measured using the S-parameters setup [see Fig. 13(h)]. It can
be seen that lowering VDD slightly affects the measured input
matching for supply as low as 0.3 V. The change is more
considerable for extremely low supply levels (0.2 and 0.15 V).
The input matchings of the one-stage CAS and two-stage
CAS-LNAs were measured using the noise measurement setup
[see Fig. 13(g) and (i)]. Therefore, the measured S11 curves
are noisier and slightly different than the ones reported with
the S-parameters setup. Nevertheless, S11 shape is maintained
across the supply domains.
In order to analyze the low-power operation, the measured
peak gain, NF, 3 dB BW, and the calculated FoM for the
two-stage 5G LNAs are presented versus dc power consump-
tion (see Fig. 14). The CS design achieves 12 dB gain and sub-
3 dB NF when Pdc is only 1 mW (VDD = 0.2 V). Sub-3 dB NF
operation is achieved for the CAS-LNA at 0.4 V/2.4 mW with
17.7 dB of gain. For the same 7.5 mW, the CAS-LNA achieves

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 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
EL-AASSAR AND REBEIZ: DESIGN OF LOW-POWER SUB-2.4 dB MEAN NF 5G LNAs USING FBB
TABLE I
C OMPARISON W ITH K/Ka-BAND mm-WAVES LNA S
Fig. 14. (a) Measured performance across Pdc for the two-stage LNAs.
(a) NF and gain. (b) FoM. (c) 3 dB BW and VDD . FBB (0–2 V) is used for
VDD < 0.5 and < 1 V for the CS and CAS-LNAs, respectively, to improve
NF and FoM.
25 dB gain, which is 6.2 dB higher than the CS-LNA, while the
NF is 2.32 dB (and is only 0.23 dB higher than the CS-LNA),
as predicted from Fig. 6(c). The CAS design, however, has
nearly half the BW of the CS one. It is, thus, useful to compare
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9
their FoMs across dc power levels, which considers the BW
in addition to the gain and NF [see Fig. 14(b)].
Both two-stage LNAs achieve excellent FoMs > 20 dB
across most of their operation range. The FoM increases as
Pdc is reduced since the gain and NF improvement saturate for
higher power levels. The two LNAs have comparable FoMs
of 24–28 dB at 5–10 mW with the CAS-LNA favoring the
gain while the CS-LNA favoring the ULV operation, BW, and
slight NF improvement.
Table I summarizes the performance of the three FBB-
LNAs and presents a comparison with published silicon-based
K/Ka-band LNAs. To the best of our knowledge,
the single-stage CAS-LNA demonstrates the highest in-band
IIP3 for a 10 dB gain 5G LNA. The two-stage CS-LNA
reports the highest FoM, the lowest VDD , and Pdc in the
K/Ka-band with more than 9 GHz of BW and state-of-the-art
sub-2.2 dB mean NF. The two-stage CAS-LNA has the
same 28.5 dB peak gain as in [1] but with 4× less Pdc and
1.15 dB less mean NF. In the low-power mode, the two-stage
CAS-LNA has the highest reported gain of 23.2 dB for a
5 mW design with an NF < 2.4 dB.
VII. C ONCLUSION
This work detailed the design and measurement of
mm-wave 5G K/Ka-band FBB LNAs in 22 nm FDSOI. The
FBB effect is studied and applied to improve the performance
under scaled VDD and Pdc for CS and CAS-LNAs. The
single-stage CAS-design reports the highest IIP3 for a CMOS
LNA operating at 28 GHz, while the two-stage LNAs deliver
state-of-the-art sub-2.4 dB mean NF in the low-power mode
(3.2 mW for CS-LNA and 5.5 mW for CAS-LNA) with an
FoM over 25 dB. Such performance can improve current 5G
K/Ka-band phased-array front ends.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10
ACKNOWLEDGMENT
The authors would like to thank Integrand Software, Inc.,
for EMX electromagnetic simulator and GlobalFoundries for
chip fabrication.
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May 2020.
Omar El-Aassar (Graduate Student Member, IEEE)
received the B.Sc. (Hons.) and M.Sc. degrees in
electrical engineering from Ain Shams University,
Cairo, Egypt, in 2011 and 2015, respectively, and
the Ph.D. degree from the University of California
at San Diego, La Jolla, CA, USA, in 2020.
In 2010, he joined Mentor Graphics, Cairo, as an
Intern, where he worked for the Device Model-
ing Team. He has been a Teaching Assistant with
the Electronics and Communications Engineering
Department, Ain Shams University, from 2011 to
2015. He was also a Senior Analog/RF IC Design Engineer at Si-Ware Sys-
tems, Cairo, where he worked with the Timing Division on High-Performance
Clocking Circuits and LC-Based Reference Oscillators. In 2019, he was
an RF Design Intern with the RFIC Team, Qualcomm, San Diego. He is
currently with Apple, San-Diego. His research interests include RF/mm-wave
and ultra-wideband circuits and systems, integrated timing solutions, and
low-power circuits and systems.
Dr. El-Aassar was a recipient of the Analog Devices Outstanding Student
Designer Award in 2019 and the Dr. William Chang Best Dissertation Award
in 2020 at the University of California, San Diego.
Gabriel M. Rebeiz (Fellow, IEEE) received the
Ph.D. degree from the California Institute of Tech-
nology, Pasadena, CA, USA, in 1988.
From 1988 to 2004, he was with the University
of Michigan, Ann Arbor, MI, USA. His group
has optimized the dielectric-lens antenna, which is
the most widely used antenna at millimeter-wave
and terahertz frequencies. His group also devel-
oped 6–18, 30–35, 40–50, 77–86, and 90–110 GHz
8- and 16-element phased arrays on a single silicon
chip. The first silicon phased-array chip with built-
in-self-test capabilities, the first wafer-scale phased arrays with on-chip
antennas, and the first SiGe millimeter-wave silicon passive imager chip at
85–105 GHz. His group also demonstrated high-performance RF MEMS
tunable filters at 0.7–6 GHz, RF MEMS phase shifters at 1–100 GHz,
and high-power high-reliability RF MEMS metal-contact switches. As a
consultant, he helped develop 24 and 77 GHz single-chip SiGe automo-
tive radars, phased arrays operating at X- to W-band for defense and
commercial applications (SATCOM, automotive, and point-to-point), digital
beamforming systems, and several industrial RF MEMS switches. He has
graduated 68 Ph.D. students and 24 post-doctoral fellows. He is currently a
Distinguished Professor and the Wireless Communications Industry Endowed
Chair Professor of Electrical and Computer Engineering with the University
of California at San Diego (UCSD), La Jolla, CA, USA. He also leads a group
of 20 Ph.D. students and post-doctoral fellows in the areas of millimeter-wave
radio frequency integrated circuits (RFICs), tunable microwaves circuits,
RF MEMS, planar antennas, and terahertz systems. He has authored or
coauthored over 700 IEEE publications and authored the book RF MEMS:
Theory, Design and Technology, (Wiley, 2003).
Dr. Rebeiz is a member of the National Academy of Engineering. He has
been a Distinguished Lecturer of the IEEE Microwave Theory and Technique
Society (MTT-S), the IEEE Antennas and Propagation Society (AP-S), and
the IEEE Solid-State Circuits Society. He was a National Science Foundation
Presidential Young Investigator, a URSI Koga Gold Medal recipient, and
the 2003 IEEE IEEE MTT-S Distinguished Young Engineer. He was a
recipient of the IEEE MTT-S 2000 and 2014 Microwave Prize, the IEEE
MTT-S 2010 Distinguished Educator Award, the IEEE AP-S 2011 John D.
Kraus Antenna Award, the 2012 Intel Semiconductor Technology Council
Outstanding Researcher in Microsystems, the R&D 100 2014 Award for his
work on phased-array automotive radars, the 2014 IEEE Daniel E. Noble
Field Medal for his work on RF MEMS, and the IEEE AP-S 2015 Harold
A. Wheeler Applications Prize Paper Award. He was a recipient of the 1997–
1998 Eta Kappa Nu Professor of the Year Award, the 1998 College of
Engineering Teaching Award, and the 1998 Amoco Teaching Award given
to the Best Undergraduate Teacher at the University of Michigan, and the
2008 Teacher of the Year Award of the Jacobs School of Engineering, UCSD.
His students have received a total of 22 best paper awards from the IEEE
MTT-S, RFIC, and AP-S conferences. He has been an Associate Editor of
the IEEE T RANSACTIONS ON M ICROWAVE T HEORY AND T ECHNIQUES .