IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO.
6, JUNE 2021
A 0.061-mm2 1–11-GHz Noise-Canceling
Low-Noise Amplifier Employing Active
Feedforward With Simultaneous Current
and Noise Reduction
Zhe Liu , Student Member, IEEE, Chirn Chye Boon , Senior Member, IEEE, Xiaopeng Yu , Member, IEEE,
Chenyang Li , Member, IEEE, Kaituo Yang , Member, IEEE, and Yuan Liang , Student Member, IEEE
Abstract— This article proposes a novel wideband common-
gate (CG) common-source (CS) low-noise amplifier (LNA) with
active feedforward for simultaneous current and noise reduction.
By employing an active feedforward stage in the main path,
the current dissipation and the thermal noise are effectively
suppressed, while the noise and distortion cancelation properties
of CG-CS topology are preserved. Moreover, no extra noise is
introduced since the additional gm -boost amplifier follows the
same noise-canceling (NC) principle as the CG amplifier, and its
noise can be fully canceled at the output theoretically. Thus, the
proposed LNA benefits from the gm -boosting and NC technique
simultaneously to obtain a good tradeoff between gain, noise fig-
ure (NF), and power consumption. Fabricated in standard 40-nm
CMOS technology, the measured results show the proposed LNA
exhibits a peak gain of 17 dB, NF of 3.5–5.5 dB from 1 to 11 GHz
and an IIP3 of −2.8 dBm at 6 GHz. It consumes 9 mW from a
1.2-V supply and occupies a very compact die area of 0.061 mm2 .
Index Terms— Active feedforward, CMOS low-noise amplifier
(LNA), common-gate (CG), common-source (CS), noise-canceling
(NC), ultrawideband (UWB).
I. I NTRODUCTION
A S A new generation of mobile communication system,
5G wireless communication indicates that the key fea-
ture and trend of future communication development would
be super high capacity, ultrahigh data rate, and very high
bandwidth [1]. In this scenario, the demands for RF front ends
supporting a multiplicity of bands and standards have driven
both research and industry toward the design of broadband
Manuscript received October 22, 2020; revised January 1, 2021; accepted
February 6, 2021. Date of publication March 12, 2021; date of current version
June 3, 2021. This work was supported by A*STAR under its RIE2020
Advanced Manufacturing and Engineering (AME) Industry Alignment Fund-
Pre Positioning (IAF-PP) under Award A19D6a0053. (Corresponding author:
Chirn Chye Boon.)
Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, and
Yuan Liang are with VIRTUS, School of Electrical and Electronic
Engineering, Nanyang Technological University, Singapore 639798
(e-mail: liu.zhe@ntu.edu.sg; eccboon@ntu.edu.sg; licy@ntu.edu.sg;
ktyang@ntu.edu.sg; yliang017@e.ntu.edu.sg).
Xiaopeng Yu is with the Institute of VLSI Design, Zhejiang University,
Hangzhou 310027, China (e-mail: yuxiaopeng@zju.edu.cn).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TMTT.2021.3061290.
Digital Object Identifier 10.1109/TMTT.2021.3061290
0018-9480 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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3093
low-noise amplifier (LNA), which is promising for software-
defined radios (SDRs) and broadband communications. In
recent decades, many broadband LNAs have been reported
to cover the 3.1–10.6-GHz ultrawideband (UWB) [2]–[6].
However, there exist some challenges for the implementation
of LNAs, such as high gain, low noise figure (NF), wideband
input matching, low power, and small silicon area. Usually,
the low NF and high gain can be simultaneously achieved
at the cost of power consumption, rendering the LNA a
power-hungry component in UWB front ends. Meanwhile,
the inductors used in UWB LNA for bandwidth extension
often consume a large area.
Conventional wideband LNA topologies, such as common-
gate (CG) and common-source (CS) with resistive shunt
feedback, often have difficulties in achieving a low NF while
maintaining a good input matching over a wide range of
frequencies, or suffer from a limited gain and large power
consumption [8]. To effectively improve the transconductance,
the gm -boosting technique is applied in CG LNA [9], [10].
However, the noise voltage of the gm -boost stage is directly
referred to as the input by a factor, which is almost unity [11].
Hence, an active gm -boost stage inevitably exacerbates the
noise. To effectively suppress the noise of the input transistor,
the noise-canceling (NC) technique is widely used in wideband
LNAs [2], [12]–[22]. By adding an auxiliary amplifier to
cancel the noise contribution of the main amplifier, low NF is
achieved at the cost of power consumption.
Many wideband LNAs operating beyond 10 GHz have
been reported [2]–[8]. By adding a CS stage between the
outputs of conventional CG-CS LNA, the differential output
is converted to a single-ended one while maintaining the NC
principle [2]. However, five on-chip inductors are used to
resonate with the parasitic capacitance of the LNA for UWB
applications. It achieves a relatively low peak gain of 9.7 dB
while consuming large power consumption of 20 mW. Gen-
erally, resistive feedback can be employed in the cascode
configuration [7] and the CG-CS topology [8] for wideband
input matching. Unfortunately, the feedback resistor generates
additional noise, and the resistance is constrained for wideband
application, which limits the gain. The capacitor cross-coupled
3094 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 6, JUNE 2021
technique and transformer feedback technique are employed
in [5]. However, the maximum gain is still limited to 13 dB.
Moreover, multiple inductors are utilized, leading to a large
chip area of 1.11 mm2 . For these reported works, the tradeoffs
among the noise, gain, bandwidth, silicon area, and power
consumption have been the major design bottlenecks.
To maintain a balance among all the above design considera-
tions, this article presents an NC LNA with active feedforward
to realize both current and noise reduction. For the UWB
application, only two on-chip inductors are utilized in the
proposed LNA, where one inductor is employed at the input to
resonate with the input parasitic capacitance, while the other
is inserted at the output for inductive peaking.
The rest of this article is organized as follows. Section II
reviews NC CG-CS LNA designs in the literature. Section III
introduces the proposed LNA with theoretical analysis and
major design considerations. Section IV provides the imple-
mentation details. The measurement results are summarized
and discussed in Section V. Finally, Section V concludes this
article.
II. OVERVIEW OF E XISTING CG-CS LNA
The NC principle of the LNA is shown in Fig. 1(a), where
R S denotes the source impedance. In general, the NC principle
is to identify two nodes X and Y in the main amplifier where
the signals and the noise have opposite polarities. Then, their
voltages are scaled by the auxiliary amplifier and combined
with that of the main amplifier at the output. Therefore, the key
point of the NC mechanism is to convert the noise of M1
into two fully correlated noise components. There are two
fundamental NC topologies: CS with resistive shunt feedback
and CG-CS. The constrained gain and the additional noise
contributed by the feedback resistor make the first topology
less attractive for UWB application. The typical CG-CS balun-
LNA proposed in [12] is shown in Fig. 1(b), where gmx is the
transconductance of Mx (x = 1–7). When gm1 R1 = gm2 R2 , the
noise contribution of M1 can be fully canceled theoretically.
In this case, the NF arises from the noise contributed by M2 ,
R1 , and R2 . To gain more design insights into the tradeoffs and
design limitations of the LNAs under the input matching and
NC conditions, the equivalent transconductance from node X
to the output of the LNA, G m , and the noise factor contributed
by R1 , FR1 , are provided in Fig. 1. Based on the CG-CS
topology, many variants of the NC LNA have been reported,
which can be categorized as follows.
First, some works do target reducing the noise contribution
of the auxiliary amplifier of the CG-CS balun-LNA, which is
realized by increasing gm2 at the cost of power consumption.
To simultaneously meet the NC requirement and reduce the
noise contribution of M2 , gm2 = Ngm1 and R1 = NR2 are
proposed in [13]. However, the unsymmetrical load resistors
introduce a gain and phase imbalance at the differential
output. To solve the output imbalance problem, the current-
bleeding (CBLD) technique can be employed by adding a
CBLD circuit and two cascode transistors, which introduces
the additional noise. To reduce the noise contribution of the
cascode transistor in the auxiliary path, Kim and Kwon [19]
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report a modified CBLD circuit. It is noted that load resistors
of 1 k and cascode transistors are used in this topology.
However, these two factors constrain the voltage headroom.
Thus, a high supply voltage of up to 2.2 V is used, making
it less suitable for the low-power application. To mitigate the
current dissipation and supply voltage requirements, the load
resistor is reduced to 500 , and the local feedback technique
is employed in [21]. However, for these reported works, their
G m under the input matching and NC condition is limited to
2/R S . In this case, a large voltage gain is obtained by large load
resistors, which limits the bandwidth. For large bandwidth,
small resistors are required, leading to an increased FR1 and
lower gain. To alleviate the tradeoff among gain, bandwidth,
and NF, the second variant is to convert the differential output
to single-ended output with enhanced G m . As shown in Fig.
1(c), a CS stage consisting of M7 is added to convert the
voltage signal to the current signal in the main path. This
topology has demonstrated its application in UWB receivers
[2]. However, this CS stage requires an extra dc current,
and M7 brings additional noise. In Fig. 1(d), R1 , R2 , and
M7 are replaced by M4 and M5 with the current mirroring
N to realize the current amplification [15], [16]. Meanwhile,
multiple distortions caused by the voltage-current conversion
can be avoided by employing the current mirror (CM) com-
bination network. It is noted that G m of this topology is N
times larger than that of the CG-CS balun-LNA, allowing a
large gain–bandwidth product (GBW). Third, in recent years,
some works focus on reducing the noise contribution of the
auxiliary amplifier without extra consumed power. The prior
work [18] utilizes transformers for mutual noise cancelation
and low-power consumption. However, it targets narrowband
applications, and the transformers also occupy a large silicon
area. The current reuse technique is exploited in [22] to
increase the transconductance of the auxiliary amplifier while
keeping the same current dissipation. The main drawback
of this technique is the reduced voltage headroom, leading
to some deterioration in linearity. Moreover, an inductor is
essential to provide the dc path and ac isolation in the current
reuse technique.
According to the above design considerations, the topology
in Fig. 1(d) shows great potential for UWB application, and
it has the following characteristics. First, the input impedance
is determined by gm1 . Second, the noise contribution of M1
can be fully canceled according to the NC principle. Thus, its
main noise source comes from M2 , M4 , and M5 . The noise
contributed by M2 and M5 can be effectively inhibited by
raising the current mirroring ratio N. Therefore, with large
ratio factor N, the noise contributed by M4 dominates the
overall NF, while the noise contribution of M4 is attributed to
the transconductance ratio gm4 /gm1 . Under perfect matching
conditions (gm1 = 1/Rs ), the noise factor contributed by M4 ,
FM4 , is determined by gm4 and cannot be reduced by raising
the power consumption. Based on these considerations, there
exist several drawbacks in the conventional CG-CS LNA with
CM. First, the input matching only relies on the CG amplifier,
leading to poor design flexibility. Second, when gm1 is fixed
to 20 mS for 50- impedance matching, the current required
for M1 cannot be very small, e.g., below 1 mA. This current
LIU et al.: 0.061-mm2 1–11-GHz NC LNA EMPLOYING ACTIVE FEEDFORWARD
Fig. 1. (a) NC LNA mechanism. (b) CG-CS balun-LNA [12]. (c) Single-ended CG-CS LNA [2]. (d) CG-CS LNA with CM combination network [15], [16].
is reused by M4 , which necessitates that gm4 cannot be much
smaller than 20 mS, since gm4 /gm1 is inversely proportional
to the overdrive voltage of M4 and M1 . In other words, small
gm4 severely limits the output swing at node Y and degrades
the linearity of the main path. In general, gm4 /gm1 can be set
from 0.5 to 1 for good linearity. This ratio is set to be 0.8 in
[16]. However, such gm4 worsens the NF of LNA.
Based on the above observations, we focus on reducing
the current in the main path of CG-CS LNA to obtain both
lower gm1 and gm4 without degrading the linearity. Meanwhile,
an additional degree of freedom on the impedance matching
is added, providing more flexibility in choosing gm1 and gm4 .
In this way, the overall noise performance is improved by a
lower gm4 , while wideband input matching is well maintained.
III. P ROPOSED LNA
A. Basic Idea
As shown in Fig. 2(a), the basic concept of the proposed
LNA is to employ an active feedforward stage in the main
path. A gm -boost amplifier is added in the main path to achieve
enhanced transconductance and low current dissipation. Sub-
1 mA is, therefore, achievable by exploiting the gm -boosting
technique in the main path. Also, the input matching here is
determined by the CG amplifier and the gm -boost amplifier.
Meanwhile, it is undesirable that additional thermal noise of
the gm -boost amplifier is introduced. The noise of the gm -boost
amplifier is analyzed in detail in Section III-B, which shows
that it follows the same NC procedure as the CG amplifier.
The proposed circuit is depicted in Fig. 2(b), consisting of
an input stage (M1 ) with an active feedforward stage (M3 and
R3 ), a CM combining network (M4 and M5 ) in the main path,
and an NC stage (M2 ) in the auxiliary path. In addition, M6
works as a CBLD circuit. R B1 is the biasing resistor, which can
be replaced by a current source or biasing inductor. The CM
works as the load to directly combine the output signals of the
main and auxiliary path in the current mode. In the auxiliary
path, the CS amplifier works for both noise and distortion
cancelation, further increasing the total transconductance of
the LNA as well. It exploits gm -boosting to relax the gm1
requirement for input matching, thereby reducing gm4 . There
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3095
are two main reasons for incorporating a CBLD circuit. First,
the NC condition can be written as N = gm2 R S in this
topology, and large gm2 is of necessity to reduce the noise
contribution of M2 . Second, it is noted that the dc current of
M5 is reused by M2 in the conventional topology. However,
due to the reduced gm4 and gm5 , gm2 is around ten times of gm5
in this topology. Consequently, a CBLD circuit is required to
provide the dc current for a large gm2 . Table I summarizes the
main properties of the CG-CS LNA configurations in Fig. 1
with our proposed work. Here, the noise contribution of M6
can be neglected since its output-referred noise voltage is
divided by the total voltage gain.
In conclusion, this proposed topology exhibits both lower
NF and current with higher design flexibility than the con-
ventional topology. Benefiting from the large GBW, high gain
with wide bandwidth can be obtained simultaneously. It is
noted that this proposed LNA can also be used for broadband
applications without any inductor. Typically, for the UWB
applications, two on-chip inductors L 1 and L 2 are added to
further extend the bandwidth to 11 GHz.
B. Impedance Matching and Gain
At low frequencies, the input impedance Rin can be simply
expressed as
1
Rin = . (1)
gm1 (1 + gm3 R3 )
The input impedance here is determined by three parameters.
Under the determined input matching condition, R3 can be
set larger to target smaller gm1 and gm3 for low current
dissipation. In a practical circuit, Rin can be set slightly
larger than 50  for wideband matching. Though a slight
impedance mismatch is introduced at low frequencies, a wide-
band input matching can be obtained as the real part of the
input impedance decreases inevitably due to the parallel input
parasitic capacitance at high frequencies. To further extend
the input matching bandwidth, an L-type matching network is
employed to maintain the in-band S11 below −10 dB across
the UWB band.
In this topology, the gain from node X to B can be summed
from two paths. Given an input signal at node X, an inversely
3096 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 6, JUNE 2021

Fig. 2. (a) NC mechanism of the proposed LNA. (b) Proposed CG-CS LNA employing active feedforward with CM combination network.

TABLE I
C OMPARISON OF CG-CS LNA S

amplified signal is generated at node A. Due to the large v gs current i n is the current in the main path caused by i n1 , which
swing of M1 , a corresponding signal current is generated at meets the following KCL relationships:
node Y and further copied by the CM by a ratio of N in the ⎧
⎪
⎪ v A = −gm3 v X R3
main path. In the auxiliary path, the input signal at node X is ⎪
⎪
directly converted to the signal current by the CS stage. The ⎪
⎨v X = i n R S
two signal currents are summed at the output. Thus, the output in (3)
⎪
⎪ vY = −
voltage is amplified by means of two mechanisms: M5 drains ⎪
⎪ gm4
⎪
⎩i = i + g (v − v ).
less current from VD D to B and M2 draws more current from n n1 m1 A X
B to ground. Consequently, the gain can be simply expressed
as Solving these equations yields
i n1
Av = −G m R L = −(Ngm1 (1 + gm3 R3 ) + gm2 )R L . (2) in = . (4)
1 + gm1 R S (1 + gm3 R3 )
The load resistor R L mainly consists of the paralleling output
This expression reduces to i n1 /2 if the input is perfectly
resistance ro of transistors M2 , M5 , and M6 , limiting the
matched, indicating that half of the noise current of M1 flows
maximum voltage gain, especially in short channel-length
in the main path. The other half is constrained due to the
modulation.
source degeneration and cannot generate noise voltage at nodes
X and Y. To fully cancel the noise contribution of M1 , we have
C. Noise Analysis
gm5 v Y + gm2 v X = 0. (5)
The NC mechanism of M1 and M3 is shown in Fig. 3(a),
and the equivalent noise model of the proposed LNA is shown Solving these equations yields the NC condition
in Fig. 3(b). The thermal channel noises of M1 and M3
are modeled as current sources i n1 and i n3 , respectively. The N = gm2 R S . (6)

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LIU et al.: 0.061-mm2 1–11-GHz NC LNA EMPLOYING ACTIVE FEEDFORWARD 3097

cancelation. For the noise voltage v A , M1 and R S work as a CS

stage with source degeneration. Indeed, the generated v X and
v Y always show an opposite polarity with each other with a
fixed ratio of gm4 R S . Using (5) to get the NC condition of M3
yields the same results shown in (6). Thus, the NC principle
of the gm -boost amplifier is the same as the main amplifier.
Only considering the thermal channel noise of MOSFETs
and assuming that the gain from the input source to node X
is 1/2, the noise factor of the proposed LNA can be given
F = 1 + FM1 + FM2 + FM3 + FR3 + FM4 + FM5 + FM6
4γ gm1 (N − gm2 R S )2 4γ gm2
= 1+ 2 + 2
G m R S (1 + gm1 R S (1 + gm3 R3 )) 2 G m RS
4γ gm3 R3 gm1 (N − gm2 R S )
2 2 2
+ 2
G m R S (1 + gm1 R S (1 + gm3 R3 ))2
2
4R3 gm1 (N − gm2 R S )2
+ 2
G m R S (1 + gm1 R S (1 + gm3 R3 ))2
4N 2 γ gm4 4Nγ gm4 4γ gm6
+ + + 2 (10)
G 2m R S G 2m R S G m RS
where γ is the coefficient of the channel noise. FR3 and FM1−6
are the noise factors contributed by R3 and M1−6 , respectively.
Under the NC condition, FR3 , FM1 , and FM3 reduce to zero.
In addition, if the input is perfectly matched, the overall noise
factor F can be simplified as
Fig. 3. (a) NC mechanism of the proposed LNA. (b) Equivalent small-signal γ gm4 R S gm6 R S
model for the NC analysis. F =1+ + γ gm4 R S + γ +γ . (11)
N N N2
The second term denotes the simplified FM2 , which can be
Considering the input matching condition in (1), the NC effectively inhibited by raising N. The third term denotes
condition in (6) can be expressed as FM4 , which is determined by γ , gm4 , and R S . As mentioned
in Section II, FM4 cannot be reduced by raising N. The
Ngm1 (1 + gm3 R3 ) = gm2 . (7) fourth term denotes FM5 , which has a fixed ratio of 1/N
with FM4 . In a practical circuit, this ratio varies with the
Next is the noise analysis for the gm -boost amplifier. It is device mismatch and the drain dc voltage due to the channel
noted that the noise of R3 can be modeled as a voltage source modulation, especially for short-channel devices. To decrease
at node A, following the same analysis procedure of M3 . both FM4 and FM5 , a small gm4 is of necessity. The last
Interestingly, the noise of M3 and R3 follows the same NC term denotes FM6 , which is much smaller than FM4 with
condition, as described in (6), which means that both M3 and N 2 as the denominator. To decrease FM6 , small gm6 and
R3 produce no noise in theory. Take M3 as an example, a noise large N are preferred. In conclusion, under the NC condition,
voltage v A is generated at node A. Then, it produces two noise the main noise source comes from M2 and M4 , while the noise
voltages v X and v Y at nodes X and Y with opposite polarities. contribution of M5 and M6 can be neglected with N increasing.
Then, these two noise voltages travel through two paths and To observe the relationship between parameters and per-
cancel each other at the output. Modeling i m as the current formances, calculations are performed. Fig. 4(a) provides the
produced by v A , we have the following KCL relationships: calculated NF according to (11) while assuming gm6 = 10 mS
⎧
⎪ v A = −(i n3 + gm3 v X )R3 and γ = 1. For example, when N = 4, the calculated NFs at
⎪
⎪
⎪
⎪ gm4 = 2, 5, 12, and 18 mS are 1.48, 2.02, 3.08, and 3.81 dB,
⎨v X = i m R S
im (8) respectively. By decreasing gm4 from 18 to 2 mS, the NF drops
⎪
⎪ vY = − significantly. Meanwhile, the NF decreases as N increases.
⎪
⎪ g
⎪ m4
⎩i = g (v − v ). However, the rate of decay slows down with N increasing.
m m1 A X
When N > 5, the decrease in NF is not obvious anymore
Solving these equations yields since the main noise contribution comes from M4 rather than
M2 . To intuitively show the main noise source of the LNA,
−i n3 R3 gm1
im = . (9) the calculated relationship between FM2 and FM4 in (11) with
1 + gm1 R S (1 + gm3 R3 ) the variations of N and gm4 is provided in Fig. 4(b). For
This expression reduces to −i n3 R3 gm1 /2 if the input is per- example, with N = 4, FM4 dominates the overall noise factor
fectly matched. The negative sign indicates the current direc- when gm4 > 5 mS. Fig. 4(c) shows the calculated NF contour
tion of i m is opposite to i n , which has no impact on the noise with the variations of N and gm4 . For a given NF, smaller N

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3098 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 6, JUNE 2021
Fig. 4. (a) Calculated NF with respect to the variations of N and gm4 with γ = 1 and gm6 = 10 mS. (b) Calculated relationship between FM2 and FM4
with respect to the variations of N and gm4 . (c) Calculated NF contour with respect to the variations of N and gm4 with γ = 1 and gm6 = 10 mS.
Fig. 5. Simulated noise contributions by individual components at 1 GHz
and the corresponding parameters of the LNA. (a) Proposed work. (b)
Conventional CG-CS LNA with CM.
and gm4 lead to lower power consumption. To achieve a good
balance among gain, NF, and power consumption, N can be
carefully selected as 3, 4, or 5.
To further gain design insights into the impact of gm4 on NF,
simulations with N = 4 are performed. Here, a design example
of the conventional CG-CS LNA with CM is also provided.
To compare the noise performance objectively, the simulated
noise contributions by individual components with the corre-
sponding parameters are given in Fig. 5. For a fair comparison,
the size of M2 and the current dissipation are the same, which
can be reflected from the equal gm2 . Moreover, gm4 /gm1 of
the proposed LNA in Fig. 5(a) is similar to that of the design
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example in Fig. 5(b). The detailed design values of the LNAs
are summarized in Section IV. In Fig. 5(a), the simulated
gm4 is 2 mS with an NF of 3 dB, while the simulated gm4
is 12 mS with an NF of 4.6 dB in Fig. 5(b). The decrease
in the NF is mainly due to two factors. The first is the
decreased FM4 , which dominates the NF, as shown in Fig. 5(b).
The second is the decreased FM5 . Due to the decreased gm4
in Fig. 5(a), gm5 is 7.93 mS, while gm5 is 47.4 mS in Fig. 5(b).
It is noted that, in both LNAs, gm2 is around 60 mS. In the
conventional LNA, it is feasible for M5 and M2 to reuse the dc
current, while, in the proposed work, there exists significant
difference between gm5 and gm2 . Thus, M6 is required to
balance the difference of the dc currents required for M5 and
M2 . Though M6 introduces additional noise, the sum of the
noise contribution of M5 and M6 in the proposed work is still
smaller than the noise contribution of M5 in the conventional
LNA, as gm5 + gm6 in Fig. 5(a) is smaller than gm5 in Fig. 5(b).
This is because a small biasing voltage Vb6 can be given
to decrease gm6 while providing enough current for M2 in
the proposed LNA, while the gate voltage of M5 is fixed by
the CM in the conventional LNA, resulting in a large gm5 .
Furthermore, considering the output resistance ro4 of M4 , the
noise-canceling condition in (6) should be revised to
 
1
gm2 R S = gm5 //ro4 . (12)
gm4
This expression means that the noise cancelation actually
occurs at gm2 < gm5 /(gm4 R S ). Therefore, a good NC effect can
be regarded as the condition where the noise contributions of
M1 and M3 are lower than 1.5% according to the simulation
results.
According to the analysis of both calculation and simu-
lation, a lower gm4 effectively improves the overall noise
performance. Meanwhile, the short-channel modulation effect
cannot be neglected in the 40-nm technology. However, long-
channel transistors can only be used under the allowed gain
bandwidth and supply voltage. Short-channel transistors have
some advantages. First, as the channel length decreases, the
threshold voltage shifts in the negative direction [23] so that
the CM is more headroom-efficient. Also, the small size of the
transistor facilitates higher bandwidth by decreasing parasitic
capacitance.
LIU et al.: 0.061-mm2 1–11-GHz NC LNA EMPLOYING ACTIVE FEEDFORWARD 3099

where
1 a2 2a 2 a3
b1 = , b2 = − 3 , b3 = 52 − 4 . (19)
a1 a1 a1 a1
The current of M1 , i i can be written as

(b1 − 1)v S + b2 v 2S + b3 v 3S
ii = . (20)
RS
The current of M2 , i 2 can be written as
  3
i 2 = gm2 v X + gm2 v 2X + gm2 vX . (21)
Fig. 6. Small-signal model for the distortion analysis.
Applying Kirchhoff’s current law at the output, we have

D. Distortion Cancelation i out = Ni i − i 2 . (22)

According to [13] and [14], the nonlinearity of MOSFETs Substituting (18), (20), and (21) into (22) yields
can be modeled as a current source controlled by v gs and    
v ds , tied between the source and drain terminals. Ignoring the N N
i out = (b1 − 1) − gm2 b1 v S + − gm2 b2 v 2S
nonlinearity of nonlinear output conductance gds , the current RS RS
 
source can be written as a function of v gs using the Taylor  N   

expansion − gm2 b12 v 2S + −gm2 b3 v 3S − 2gm2 b1 b2 +gm2 b13 v s3 .
RS
gm 2 g  3 (23)
i ds = gm v gs + v gs + m v gs + · · · = gm v gs + i N L (13)
2! 3!
Thus, like the thermal channel noise, distortion currents gen-
where erated by M1 and M3 can also be canceled. Under the NC
∂ 2 Ids ∂ 3 Ids condition, i out can be simplified as
gm = , gm = . (14)
∂ Vgs2 ∂ Vgs3 
  

i out = −gm2 v S − gm2 b12 v 2S − 2gm2 b1 b2 + gm2 b13 v 3S . (24)
As shown in Fig. 6, the Taylor expansions are derived for the
output current i out as a function of the source voltage v s . The The input third-order intercept point (IIP3) of the circuit can
distortions of CM are ignored for simplicity, and distortions be expressed as
of M1 , M2 , and M3 are only considered up to the third order.
 
Applying Kirchhoff’s current law at v A and v X , we have 4  gm2 
.
IIP3 = (25)
⎧ 
gm1 
gm1

3 2gm2 b1 b2 + gm2 b1 
  3
⎪
⎪ i = g (v − v ) + (v − v ) 2
+ (v A − v X )3
⎪
⎨ i m1 A X
2
A X
6 In conclusion, the distortion currents of M1 and M3 flow
v S = v X − ii RS (15)
⎪
⎪ −v   along the main path and the auxiliary path. Then, the nonlinear
⎪ g
⎩ A = gm3 v X + m3 v 2 + m3 v 3 g
components undergo the same cancelation as noise, which gets
R3 2 X 6 X canceled at the output. In this case, the distortion of the LNA
 
where i i denotes the current of M1 . gmi and gmi (i = 1–3) are mainly comes from M2 . However, due to the nonlinearity of
the first- and second-order derivatives of the transconductance M2 , the nonlinearity of M1 and M3 also degrades the IIP3.
of M1 , M2 , and M3 , respectively. By solving (15), v s can be
expressed as
E. Bandwidth
v S = a1 v X + a2 v 2X + a3 v 3X (16)
At low frequencies, the input impedance and gain are
where expressed in (1) and (2), respectively. However, input para-
⎧ sitic capacitance and load capacitance deteriorate the input
⎪
⎪ a1 = (gm1 (gm3 R3 + 1)R S + 1)
⎪
⎪ matching and gain at high frequencies. In this topology,
⎪
⎪ 1  the broadband input matching (S11 ) and the power gain (S21 )
⎪  
⎨a 2 = 
⎪
2
R S gm1 gm3 R3 − gm1 (gm3 R3 + 1)2
are challenging due to the parasitic effect mainly distributed
1  1   (17)
⎪
⎪ a 3 = gm1 gm3 R3 − gm1 gm3 (gm3 R3 + 1) at four nodes in Fig. 2(b). Ignoring the Miller effect of C gd ,
⎪
⎪ 6 2 
⎪
⎪ at the input node X, input capacitance Cin mainly includes
⎪
⎪ 1 
⎩ + g (g R
m3 3 + 1) 3
RS the gate–source capacitance of M1 , M2 , and M3 , giving a pole
6 m1 frequency
Then, the nonlinear v X can be written as a function of v s
1
ωX =  . (26)
v X = b1 v S + b2 v 2S + b3 v 3S (18) Cgs1 + Cgs2 + Cgs3 (R S //Rin )

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3100 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 6, JUNE 2021

Fig. 7. (a) L-match network. (b) Equivalent circuit.

Similarly, at nodes A, Y, and B, the bandwidth is limited at

1
ωA = (27)
Cgs1 (R3 //ro3 )
1
ωY =   (28)
Cgs4 + Cgs5 g1m4 //ro4
Fig. 8. Simulated Re{Z in } and Im{Z in } with respect to the variations of L 1 .
1
ωB = (29)
(C1 + C2 )(ro2 //ro5 //ro6 )
where C1 donates the sum of gate–drain capacitance of transis-
tors M2 , M5 , and M6 . C2 donates the load capacitance. Cgsx is
the gate–source capacitance of transistors Mx (x = 1–6). The
size of M5 and M6 is much larger than M1 and M4 , resulting in
a larger capacitance seen at node B. Therefore, ω B dominates
the frequency response of gain.
To cope with the input matching degradation, an on-chip
inductor L 1 is inserted to resonate with the input parasitic
capacitance. As shown in Fig. 7(a), the input impedance Z in
can be expressed as
Rin Cin L 1 s 2 + L 1 s + Rin
Z in =
1 + Rin Cin s
Rin + j ω Rin Cin L 1 ω2 + L 1 − Rin
2 2 2
Cin Fig. 9. Simulated S11 with respect to the variations of L 1 .
= . (30)
1 + Rin Cin ω
2 2 2

Re{Z in }, the real part of Z in , indicates that Rin is transformed

down by a factor of 1+ω2 Cin2 Rin 2
, while the imaginary part
Im{Z in } can be regarded as the series LC network in a narrow
frequency range. As shown in Fig. 7(b), the approximation
allows equivalence for qualitative analysis in a certain fre-
quency range, where Fig. 10. Equivalent small-signal model at the output.

 Rin
Rin = (31)
1 + Rin Cin ω
2 2 2
The series inductor L 2 is inserted to resonate with the
1 + R in Cin ω
2 2 2
Cin = Cin . (32) output capacitance, resulting in an extended bandwidth and
Rin Cin ω
2 2 2
a gain peaking in the frequency response. Series peaking is a
Fig. 8 shows the simulated Re{Z in } and Im{Z in } with respect typical bandwidth extension technique, which is widely used in
to the variations of L 1 . As calculated in (31), Rin is converted CMOS amplifiers [24]–[27]. Different from the shunt peaking,
to a lower series component, which is independent of L 1 . which introduces a zero to extend bandwidth, the bandwidth
Meanwhile, the characteristic of Im{Z in } shows a conversion extension of series peaking is entirely from the peaking pro-
from capacitive to inductive by increasing L 1 . According to vided by complex poles [28]. In deep-submicrometer CMOS
(30), S11 can be written as technology, the gate–drain capacitance is comparable in mag-
  nitude to the gate–source capacitance. The equivalent small-
 Rin Cin L 1 s 2 + (L 1 − Cin Rin R S )s + Rin − R S  signal model of the output at node B is shown in Fig. 10,
S11 = 20 log .
Rin Cin L 1 s 2 + (L 1 + Cin Rin R S )s + Rin + R S  which has a third-order transfer function
(33) Vout G m RL
= (34)
Fig. 9 shows the simulated S11 with respect to the variations of Vin R L C1 C2 L 2 s 3 + C2 L 2 s 2 + R L (C1 + C2 )s + 1
L 1 . By choosing appropriate L 1 , good input matching (S11 < where R L = ro2 //ro5 //ro6 . By inserting L 2 , three complex
−10 dB) can be easily achieved across the UWB band. poles in the left plane are created here. The poles close to

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LIU et al.: 0.061-mm2 1–11-GHz NC LNA EMPLOYING ACTIVE FEEDFORWARD
Fig. 11. Simulated voltage gain with the variations of L 2 .
Fig. 12. Schematic of the proposed LNA.
the imaginary axis dominate the frequency response. When
the frequency moves at the vertical axis, the magnitude of
the frequency response has a peak in the proximity of the
frequency where the length of the pole vector has a minimum.
The detailed bandwidth extension ratios for series-peaked
designs are summarized in [25]. Assuming the proposed LNA
without L 2 exhibits a wide bandwidth over 4 GHz, it is
completely feasible to insert one series inductor to extend the
bandwidth to cover the UWB band.
Fig. 11 shows the simulated voltage gain of the proposed
work and the conventional CG-CS LNA with CM, whose
design values are given in detail in Fig. 13. First, the band-
widths of two LNAs without using inductors are compared.
With the same current dissipation of 6.6 mA in the auxiliary
path, as mentioned above, M6 in the proposed work can
be biased with a small voltage to achieve a small gm6 and
transistor size. In this case, the size of M6 is 22 μm/40 nm
with an output conductance gds6 = 3.8 mS, and the size of M5
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3101
Fig. 13. Design example of the conventional CG-CS LNA with CM.
is 24 μm/40 nm with an output conductance gds5 = 1.4 mS.
In the conventional topology, only M5 works as a load of
the auxiliary amplifier with a size of 152 μm/40 nm and
an output conductance gds5 = 8.2 mS. Thus, the proposed
work exhibits larger output resistance and smaller parasitic
capacitance compared to the conventional one. The black
line shows the simulated result of the conventional CG-CS
LNA with a voltage gain of 19.5 dB and 3-dB bandwidth
of 4.3 GHz, while the red line gives the simulated result
of the proposed LNA with a voltage gain of 20.7 dB and
3-dB bandwidth of 4.8 GHz. Second, at high frequencies,
the bandwidth extension is determined by L 2 . The design
target is to cover the UWB band with gain variation within
3 dB. Here, the simulated bandwidth is larger than the targeted
band considering the design margin. For example, by choosing
L 2 to be 2.8 and 4 nH, the simulated gain shows a peak at
13.2 and 12.2 GHz, respectively. To obtain a larger bandwidth,
L 2 = 2.8 nH can be chosen.
In the proposed LNA, the output capacitance seen at node B
produces a dominant pole, allowing a one-pole approximation.
For a one-pole amplifier, the GBW is determined by G m
and load capacitance. By employing CM to realize current
amplification, the proposed LNA exhibits a large G m by
increasing N. When N = 4, high gain larger than 15 dB and
bandwidth over 4 GHz can be achieved. In this case, only one
series inductor is required to extend the bandwidth to cover
the UWB band.
IV. C IRCUIT I MPLEMENTATION
This section presents the circuit design of the proposed work
and a design example of the conventional CG-CS LNA with
CM. As mentioned above, for a fair comparison, the current
dissipation of the auxiliary amplifier in the proposed LNA and
the conventional one is the same. Moreover, the corresponding
transconductance has been given in Fig. 5. For both LNAs,
an output buffer consisting of M7 and M8 is used to drive the
50- load. The key performance comparison of three con-
figurations, including the proposed work, the proposed work
without inductors, and the conventional one, is summarized
in Table II, where I D1 , I D2 , and I D3 are the simulated dc
3102 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 6, JUNE 2021

TABLE II
K EY P ERFORMANCE C OMPARISON OF T HREE C ONFIGURATIONS

Fig. 15. Monte Carlo simulation results for NF.

Fig. 14. Simulation results versus frequency under different process corners
and temperatures of gain and NF.

currents of M1 , M2 , and M3 , respectively. The overall current

of the main path in the proposed work is 0.9 mA, saving 46% Fig. 16. Die photograph of the fabricated LNA.
current of that in the conventional topology. By employing
the active feedforward, I D1 drops from 1.67 to 0.29 mA,
decreasing gm4 from 12 to 2 mS. Due to the reduced gm4
and gm5 , the simulated NF decreases from 4.6 to 3 dB.
Fig. 12 shows the schematic of the proposed LNA. For
low-power consideration, both gm1 and gm3 are supposed to
be small. In this case, large R3 facilitates input matching,
resulting in a certain voltage drop across R3 . Therefore,
an extra dc bias voltage at the gate of M1 is necessary. R B2 is
used to provide stable dc output voltage, and its value is much
larger than 1/gm2 . Thus, it has little impact on the ac signal.
M1 is biased with a resistor R B1 . In general, the bias current
of the CG stage can be provided by a current source or a
resistor, which can be fully integrated. The current source
is normally realized by a transistor operating in saturation.
According to [11], with the same voltage drop, the noise
contribution of a current source is about twice that of biasing
resistor when γ = 1. In addition, the biasing transistor also Fig. 17. Simulated and measured gain and S11 of the proposed LNA.
introduces significant parasitic capacitance at the input node.
Here, a biasing resistor R B1 is, therefore, preferable. It is noted the voltage drop across such a large resistor is only 0.29 V,
that R B1 is set to be 20 times R S , which has an impact on while, in the conventional topology, it is not feasible to use
the input matching and NF. Benefiting from the small I D1 , such a large biasing resistor due to the large I D1 . Meanwhile,

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LIU et al.: 0.061-mm2 1–11-GHz NC LNA EMPLOYING ACTIVE FEEDFORWARD 3103

TABLE III
P ERFORMANCE S UMMARIES OF THE P ROPOSED LNA AND C OMPARISON W ITH P REVIOUSLY R EPORTED W IDEBAND LNA S

it is also not feasible to use a biasing transistor as the current

source. For a biasing transistor whose transconductance is
gmbias , the contributed noise factor is determined by γ gmbias R S .
In this case, a small gmbias is of necessity to reduce the noise
contribution. However, the bias current is reused by M1 to
realize a transconductance around 20 mS for input matching,
resulting in a large overdrive voltage for the biasing transistor.
Thus, a biasing inductor L B is used in Fig. 13. L B has the
advantage of no dc voltage drop, providing more voltage
headroom for M1 and M4 . Thus, the simulated IIP3 is better
than the proposed work. However, large inductance is required
to provide input matching at low frequencies. For example,
an L B of 200 nH is selected in [21]. Such large L B can only
be implemented in the printed circuit board, which cannot be
fully integrated in the chip. Fig. 18. Simulated and measured NF of the proposed LNA.
To evaluate the robustness of the proposed work, the gain
and NF under various process corners and temperatures are of the NF is 0.0099 dB due to device mismatch and 0.113 dB
examined based on the postlayout simulation. In general, NF due to process variation. Next, the measurement results are
deteriorates at high temperatures, and it is improved at low provided.
temperatures. Fig. 14 shows the plots of the simulated gain
and NF under typical and worst case scenarios. Under the V. M EASUREMENT R ESULTS AND D ISCUSSION
worst case SS corner and 125 ◦ C, the worst bandwidth is from Fabricated in TSMC 40-nm CMOS technology,
2.1 to 10.7 GHz with a gain from 13 to 16 dB. In the above the proposed LNA draws 7.5 mA from a 1.2-V supply,
bandwidth, the NF is from 4.7 to 5.7 dB. To further quantify consuming a total power of 9 mW. Fig. 16 shows the
the effect of process variation and device mismatch on the die photo of the LNA, occupying a compact active area
noise performance, Monte Carlo simulations are conducted. of 380 μm × 160 μm. Herein, the core area of the LNA is
As shown in Fig. 15, the standard deviation of the NF at only 85 μm × 40 μm. The S-parameter and NF measurement
1 GHz is 0.0057 dB due to device mismatch and 0.062 dB were conducted on the probe station using an Agilent PNA-X
due to process variation. At 11 GHz, the standard deviation Vector Network Analyzer (N5245A). The measurement

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3104
Fig. 19. (a) Measured IIP3 at 6 GHz. (b) Measured IIP3 and P1dB versus frequency.
setup and procedure are the same as [8]. The simulated and
measured voltage gain after deembedding the buffer effect are
shown in Fig. 17. Compared with the postlayout simulation,
the gain drops slightly. The measured gain shows a peak
of 17 dB at 11 GHz. The measured bandwidth meets well
with the postlayout simulation. The measured gain shows a
3-dB bandwidth of 10 GHz, from 1 to 11 GHz. Across the
above frequency range, the in-band gain variation is 3 dB. The
curve is flat from 4 to 8.5 GHz with the gain ranging from
14 to 14.5 dB. The simulated and measured S11 ’s are also
shown in Fig. 17. The measured S11 is below −10 dB up to
11.5 GHz and shows a dip at around 9 GHz. Fig. 18 shows the
simulated and measured NF. The measurement shows an NF
of 3.5–5.5 dB over 1–11 GHz, which is slightly worse than
the simulated one. The trend of the measured NF agrees well
with that of the simulated result over the entire working band.
Fig. 19(a) shows the measured IIP3 at 6 GHz by apply-
ing two tones with 10-MHz spacing. The measured IIP3 is
−2.8 dBm, while the 1-dB compression point (P1dB ) is found
to be −12 dBm. The measured IIP3 at different center fre-
quencies (1, 3, 5, 7, 9, and 11 GHz) is shown in Fig. 19(b),
ranging from −7.7 to −2.2 dBm. The measured P1dB is also
plotted with a range of −17 to −11 dBm.
Table III benchmarks the performance of the proposed
LNA with the prior works. The published wideband LNAs,
especially those with upper −3-dB frequency ( f −3 dB ) higher
than 10 GHz, as well as those adopting the CG-CS topology,
are included for comparisons. A Figure of Merit (FoM I) is
used for comparison purposes. The circuit area ( A [mm2 ]) is
added in FoM II [10] to evaluate the overall performance of
the wideband LNAs with inductors
 
BW[GHz] · Gain[lin] · IIP3[mW]
FoM I = 20 log10 (35)
PDC [mW] · (NFmin [lin] − 1)
 
BW[GHz] · Gain[lin] · IIP3[mW]
FoM II = 20 log10   .
PDC [mW] · (NFmin [lin] − 1) · A mm2
(36)
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 6, JUNE 2021
The LNA presented here achieves higher FoM I compared
with the conventional CG-CS LNA with CM in [15] and [16]
and offers comparable performance in terms of gain, NF, and
power consumption. To summarize Table III, the proposed
LNA is a very promising topology due to a good tradeoff
among gain, NF, bandwidth, and power consumption with a
very small die area.
VI. C ONCLUSION
This article proposed a novel wideband LNA topology,
which can be regarded as an improved one from the conven-
tional CG-CS NC LNA. In the conventional CG-CS topology
with CM combining network, the input matching is only
determined by the CG amplifier. Furthermore, the noise con-
tribution of the CM cannot be suppressed with a high current
in the main path. By employing the active feedforward in
the main path, the current and the noise of the CM can
both be reduced without violating the NC principle. Thus,
a better noise performance with lower power consumption
can be achieved. Adopting the L-type matching network and
inductive peaking technique, the proposed LNA achieves a
wide bandwidth covering the UWB band. Fabricated in the
TSMC 40-nm technology, the proposed LNA occupies a very
compact area of 0.061 mm2 and achieves good performance
with a bandwidth of 10 GHz, an NF of 3.5–5.5 dB, a peak
gain of 17 dB, an IIP3 of −2.8 dBm at 6 GHz, and power
consumption of 9 mW. The achieved FoMs compare favorably
to the reported works, which indicates that the proposed
topology is suitable for low-cost and high-performance UWB
LNAs.
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[28] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits,
2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2004.
Zhe Liu (Student Member, IEEE) received the B.S.
and M.S. degrees from the College of Information
Science & Electronic Engineering, Zhejiang Univer-
sity, Hangzhou, China, in 2014 and 2017, respec-
tively. She is currently pursuing the Ph.D. degree at
the School of Electrical and Electronic Engineering,
Nanyang Technological University, Singapore.
Her interests include the design of radio frequency
(RF) integrated circuits, such as low-power phase-
locked loops, delay-locked loops, and receivers for
high-speed wireless communications.
Chirn Chye Boon (Senior Member, IEEE) received
the B.E. (Hons.) and Ph.D. degrees in electrical
engineering from Nanyang Technological University
(NTU), Singapore, in 2000 and 2004, respectively.
He was with Advanced RFIC, Singapore, where
he worked as a Senior Engineer. Since 2005, he has
been with NTU, where he is currently an Associate
Professor. He has been the Programme Director for
RF and MM-wave research in the S$ 50 million
research centre of excellence, VIRTUS, and NTU,
since March 2010. He has conceptualized, designed
and silicon-verified many circuits/chips resulting in over 160 refereed pub-
lications and over 30 patents in the fields of RF and MM-wave. He is a
coauthor of the book Design of CMOS RF Integrated Circuits and Systems
and CMOS Millimeter-Wave Integrated Circuits for Next Generation Wireless
Communication Systems (World Scientific Publishing). He specializes in the
areas of radio frequency (RF) & MM-wave circuits design for communications
applications.
Dr. Boon is a key NTU-team member of MIT-NTU joint collaboration
project "Low Energy Electronic Systems," under Singapore-MIT Alliance for
Research and Technology (SMART) with a grant total of S$ 25 million. He
is also a key member of an Industry Alignment Fund (IAF-PP) on "Next-
Generation V2X" with a grant total of S$ 21million. He is also a winner of the
Year-2 Teaching Excellence Award and Commendation Award for Excellent
Teaching Performance, EEE, and NTU. He is also an Associate Editor of
the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI)
S YSTEMS and the IEEE E LECTRON D EVICES L ETTERS Golden Reviewer.
He is also the Principal Investigator for research grants of over S$ 13 million.
3106 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 6, JUNE 2021

Xiaopeng Yu (Member, IEEE) was born in Zhe-
jiang, China. He received the B.Eng. degree from
the Department of Optical Engineering, Zhejiang
University, Hangzhou, China, in 1998, and the Ph.D.
degree from the School of Electrical and Elec-
tronic Engineering, Nanyang Technological Univer-
sity (NTU), Singapore, in 2006.
He was an Engineer with the MOTOROLA Global
Telecom Solution Sector, Hangzhou, from 2000 to
2002, and a Research Staff with NTU from 2005 to
2006. Since 2006, he has been with the Institute of
VLSI Design, Zhejiang University, where he is currently a Full Professor. He
was with the Mixed Signal Microelectronics Group, Eindhoven University
of Technology, Eindhoven, The Netherlands, as a Visiting Scholar and a
Marie Curie Fellow (co-hosted with Philips Research, Eindhoven), from
2008 to 2010. His current research interests include CMOS radio frequency
integrated circuits for wireless communication, low-power phase-locked loops,
and clock data recovery circuits for high-speed data communications using
submicrometer CMOS technology.
Kaituo Yang (Member, IEEE) received the B.S.
and M.S. degrees from the School of Informa-
tion Science and Technology, University of Science
and Technology of China (USTC), Hefei, China,
in 2011 and 2014, respectively. He is currently
pursuing the Ph.D. degree at Nanyang Technological
University, Singapore.
He holds several patents in the field of RF-CMOS
design. His research interests include analog and RF
integrated circuits and systems for wireless commu-
nications, especially focusing on low NF and high
linearity receiver design.

Chenyang Li (Member, IEEE) received the B.Eng. Yuan Liang (Student Member, IEEE) is currently
degree and the M.Eng. degree in electronic science pursuing the Ph.D. degree at the School of Electrical
and technology from the University of Electronic and Electronic Engineering, Nanyang Technological
Science and Technology of China, Chengdu, China, University, Singapore, with a focus on mm-wave to
in 2009 and 2012, respectively. He is currently terahertz integrated circuits design.
pursuing the Ph.D. degree in electrical engineering
at Nanyang Technological University, Singapore.
His research interest includes high linear power
amplifier design for Wi-Fi systems.

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