Proceedings of the Fourth International Conference on Trends in Electronics and Informatics (ICOEI 2020)
IEEE Xplore Part Number: CFP20J32-ART; ISBN: 978-1-7281-5518-0
0.9 V Body-Biased LNA with Input Matching for
Enhanced Gain & Low Power Applications
Ankur Pal
Dept. of Electronics & Communication Engineering
Galgotias College of Engineering and Technology
Greater Noida, India-201310
ankurpalgcet16@gmail.com
Sarthak
Dept. of Electronics & Communication Engineering
Galgotias College of Engineering and Technology
Greater Noida, India-201310
varshneysarthak11@gmail.com
Abstract—In this paper, a 2.4 GHz Low Noise Amplifier
(LNA) at 180nm CMOS technology is presented. This LNA
design involves two stages, the common source cascade, and the
cascode stage. The proposed circuit improves the noise figure
(NF) and power gain (S 21) of LN A by utilizing the cumulative
effect of the input matching network and body bias technique.
The work is implemented using the tool “Advanced Design
S ystem” (ADS ). The simulation results show a power gain (S 21) of
26.925 dB and a noise figure of 1.505. The other scattering
parameters are also observed with input return loss (S 11) of -
11.989 dB, output return loss (S 22) of -10.397 dB, and reverse
isolation (S 12) of -53.030 dB. With the help of the body bias
technique, the power supply of the circuit is also reduced to 0.9V
which leads to the power consumption of as low as 2.507 mW.
Keywords—Body bias, input matching network, cascade and
cascode stage low noise amplifier (LNA), power gain, noise figure,
supply voltage.
I. INT RODUCT ION
Wireless Communication, nowadays, plays an important
role to cater to the needs of increasing data traffic. Various
wireless technologies such as mobile co mmunication, satellite
communication, wireless access, etc., are growing at a fast
pace. All these systems utilize radio frequency technology or
radio frequency integrated circuit (RFIC) [1]. Hence, the RF
receiver’s performance needs to be taken into consideration.
Due to the various advancements in communication
technologies, the RF receiver frontend requires an improved
performance. When the performance of the device is under
consideration, Low Noise Amplifier (LNA) plays an essential
role in the receiver frontend. In the RF circuit design, CMOS
technology has been widely used because of its low cost and
low power. The major performance parameters of the LNA are
power gain, noise figure (NF), power consumption, and power
dissipation. A good low noise amplifier should have a
minimu m noise figure and maximu m gain. The supply voltage
should also be less. Many circuit configurations of LNA have
been proposed as reported in the work [1], [2] where they focus
on the gain, noise figure, linearity and stability but still, the
trade-offs between the noise figure and gain have not been
overcome for lo w-voltage as well as low power applications.
This paper implements the input matching network and the
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Garvita Singh
Dept. of Electronics & Communication Engineering
Galgotias College of Engineering and Technology
Greater Noida, India-201310
gsingh10jun@gmail.com
Gaurav M ehra
Dept. of Electronics & Communication Engineering
Galgotias College of Engineering and Technology
Greater Noida, India-201310
gaurav.mehra@galgotiacollege.edu
body bias technique which helps in minimizing the noise figure
and increasing the power gain simu ltaneously without affecting
the other parameters. The paper is organized as follows.
Section II discusses the techniques used to optimize the
parameters of LNA. It also describes the analysis of noise
figure NF, power gain, and the supply voltage requirements.
Next, the proposed LNA is presented and explained. Section III
shows the simu lation results where each parameter is discussed
individually. And in the last, Section IV g ives a brief
conclusion.
II. DESIGN AND IMPLEMENTATION
The sensitivity of any communication system depends upon
the noise. The noise factor is defined as the ratio of the SNR at
the input and the SNR at the output port where SNR is signal to
noise ratio.
= = 1+ (1)
Where NI and NA represent the noise at the input source and the
total noise due to the circuit respectively. The Noise Factor for
the system consisting of many elements in the series can be
given by the equation
= + + + …………. (2)
Where G1, G2 represents the power gain, and F1 , F2 , F3
represents the noise factors at each design stage. From equation
(2), it can be observed that if power gain G1 (first stage) is large
then the total noise factor will depend only on the first stage of
the circuit design. Since LNA is the init ial stage of the receiver
front end, hence LNA should have a gain as high as possible
and noise figure as low as possible.
The proposed LNA circuit is shown in Fig 1. It consists of a
common source (CS) cascade LNA as its first stage and
cascode stage as its second stage. The two-stage LNA is used
to boost the gain of LNA [3]. The transistors M2 and M3 are
connected in the cascode with M2 as a co mmon source and M3
as a common gate. Cascode stage reduces the Miller effect and
improves the output impedance that results in an improved gain
and excellent reverse isolation as stated in [4] – [8]. The
cascade stage is added to provide a high-power gain. The
378
 Proceedings of the Fourth International Conference on Trends in Electronics and Informatics (ICOEI 2020)
IEEE Xplore Part Number: CFP20J32-ART; ISBN: 978-1-7281-5518-0
inductor Lg is responsible for input matching. Lg and C2
together provide the DC path for the MOSFET M2. Inductor
L5 and capacitor C1 are responsible for output matching and
maintaining a DC path to the output port. Source inductance
negative feedback is implemented in the circuit with capacitor
C3 (attached between source and gate terminals) to optimize
the parameters of LNA. The noise figure is reduced on the
application of this input matching network without affecting
the other parameters. This technique results in better
impedance matching and also provides linearity to the circuit
[9]. As several MOSFETs are used in the circuit, DC power
consumption is high. A body bias technique is used to lower
the DC power consumption which reduces the supply voltage
and also makes it suitable for low power applications [4]. This
technique is implemented by providing external bias voltages
(Vbias ) to the body terminals of the MOSFETs as shown in Fig
1. The threshold voltage (VTH ) of a MOSFET is given by
equation (3) [10].
= + ( 2 − − 2 )
Where VTH0 is the threshold voltage at Vbias = 0V, Vbias is the
body to source voltage, ϒ0 is the process dependent parameter
known as substrate bias effect constant and represents the
bulk fermi-potential.
Fig:1 Proposed LNA schematic
On increasing Vbias from 0V to 0.9V, the value of the threshold
voltage decreases which in turn decreases the gate to source
voltage (VGS) of the MOSFETs M2, M3, and M4. This
decrement in the threshold voltage (VTH ) of the MOSFETs
reduces the supply voltage (VDD ) required by the proposed
circuit and makes the circuit applicable for lo w power
applications [4], [11]. After applying the body bias technique, a
reduction in noise figure (NF) is also observed.
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The Noise Factor (FDrain-Current ) is given by equation (4) and
transconductance is given by equation (5) [11].
F = (4)
=μ ( − ) (5)
Where Gm represents transconductance of the MOSFETs, ϒ is
the noise coefficient of CMOS, W/L represents the ratio of
MOS dimensions, VTH represents the MOSFETs threshold
voltage, COX represents the oxide capacitance and μ
represents the device mobility.
When threshold voltage decreases, then from equation (5), it is
noticed that transconductance increases , which in turn
decreases the noise factor of the proposed circuit as Gm is
inversely proportional to FDrain-Current given by equation (4).
Thus, the noise figure of the proposed LNA is also reduced by
(3) applying a body bias technique. And, when the noise of the
LNA is reduced, the gain that LNA provides will be enhanced.
Also, the work reported in [12] tells about the adaptive
substrate bias scheme in low noise amp lifiers for process
variability and circuit reliability. Hence, it can be said that the
body bias techniques are specifically imp lemented in the
amp lifier circuits where the low noise figure and low
operating voltages are required for nanoscale transistors.
III. RESULTS AND DISCUSSIONS
The simulation of the proposed circuit is done using the
“Advanced Design System” software. DC analysis of the
proposed circuit has been done and the scattering parameters of
the proposed circuit have been observed along with the noise
figure and the stability of the proposed circuit. Fig 2 and Fig 3
show the power gain and noise figure of the CMOS CS cascade
LNA with a cascode stage at 2.4 GHz with a power supply of
1.5 V.
Fig 2: Power gain (S21 ) of the circuit without C3 and Vbias
379
 Proceedings of the Fourth International Conference on Trends in Electronics and Informatics (ICOEI 2020)
IEEE Xplore Part Number: CFP20J32-ART; ISBN: 978-1-7281-5518-0

proposed LNA circuit involving both the above techniques.

Besides to body bias technique, the power gain (S21 ) of the
circuit significantly increased from 21.803 dB to 26.925 dB
which can be seen fro m Fig 4 and Fig 6. S21 represents a
measure of how efficiently the signal is transmitted fro m the
input terminal to the output terminal. It is also observed that
there is a decrement in the noise figure of 4.26% in the noise
figure of the circuit as shown in Fig 5 and Fig 11. The power
supply of the circuit is also reduced from 1.5 V to 0.9 V.

Fig 3: Noise Figure (NF) of the circuit without C3 and Vbias

The proposed circuit consists of two techniques, the input

matching network and the body bias technique. First, the input
matching network is added to common source cascade-cascode
LNA (operating at 1.5 V). For this, C3 is added between gate
and source of M2 which resulted in a substantial decrease in
noise figure from 2.775 to 1.572 as shown in Fig 3 and Fig 5.
A minute change of +2.67 % in the power gain is also observed
as shown in Fig 2 and Fig 4. Fig 6: Power Gain (S21 ) of the proposed circuit

The input return loss or input reflection coefficient (S11 ) for

the proposed circuit at 2.4 GHz is -11.989 d B as shown in Fig
7. S11 tells how much the input impedance matches the
reference impedance. Since S11 is below -10 d B, it indicates
that the circuit is well matched at the input and output.

Fig 4: Power Gain (S21 ) of the circuit with C3 added (without body bias)

Fig 7: Input Return loss (S11 ) of the proposed circuit

The output return loss or output reflection coefficient (S22 ) for

the proposed circuit at 2.4 GHz is -10.397 d B as shown in Fig
8. S22 tells how much the output impedance matches the load
impedance. Since S22 is below -10 d B, it indicates that the
circuit is well matched at the input and output.

Fig 5: Noise Figure (NF) of the circuit with C3 added (without body bias)

To further optimize the parameters of LNA, the body bias

technique is implemented. In this technique, Vbias is added to
the substrate of MOSFETs M2, M3, and M4. Fig 1 depicts the

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 Proceedings of the Fourth International Conference on Trends in Electronics and Informatics (ICOEI 2020)
IEEE Xplore Part Number: CFP20J32-ART; ISBN: 978-1-7281-5518-0

Fig 11 shows the minimu m noise figure (NF min ) of the

proposed circuit which is observed to be 1.331.

Fig 8: Output Return Loss (S22 ) of the proposed circuit

The reverse isolation or reverse transmission coefficient (S12 )

for the proposed circuit at 2.4 GHz is -53.030 d B as shown in
Fig 9. S12 tells how much the signal applied at the input gets
reflected. Since S12 has a higher negative value, it indicates
good matching at the input and output ports.
Fig 11: Minimum Noise Figure (NFmin ) of the proposed circuit
The stability of the proposed LNA is determined by the
Rollet’s stability factor (K). It is defined by the set of scattering
parameters and is described by equation (6).
| | | | | |
= (6)

If K is greater than unity, a circuit is unconditionally stable.

Hence the proposed circuit is stable at 2.4 GHz as can be seen
clearly from Fig 12.

Fig 9: Reverse Isolation (S12 ) of the proposed circuit

Fig 10 shows the NF of the proposed circuit wh ich is observed

to be 1.505 at 2.4 GHz when a supply voltage of 0.9V is
applied to the circu it. To min imize the noise present in the
circuit, its low noise figure. This proposed LNA presents a
better noise figure than prev iously reported works as shown in
Table 3.
Fig 12: Stability factor (K) of the proposed circuit
The power consumed by the proposed circuit is calculated
by observing the drain current ( . ) and the gate voltage
(v g ) as given in Table 1. These values are observed with the
help of the current probe and voltage pin tool in ADS. The
simulation for the current ID and the voltage vg is given in Fig
13 and Fig 14 respectively.

T ABLE 1: Drain current and Gate voltage values

Frequency Drain Current Gate Voltage

(GHz) (mA) (mV)

0.000 4.117 608.962

Fig 10: Noise Figure (NF) of proposed circuit

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 Proceedings of the Fourth International Conference on Trends in Electronics and Informatics (ICOEI 2020)
IEEE Xplore Part Number: CFP20J32-ART; ISBN: 978-1-7281-5518-0

The power consumed by the circuit can be calculated using Noise Figure 2.775 1.572 1.505
equation (7). (NF)
= . × Power Supply 1.5 V 1.5 V 0.9 V
(7) (Vdc)
The power consumed by the circuit is calculated to be 2.507
mW. Hence the proposed LNA design is suitable for low
power applications. The above table shows S21 and NF of the LNA with and
without input matching network and body bias technique at
operating voltages as mentioned. The percentage change in
power gain and noise figure due to the cumulative effect of
input matching and body bias technique is +26.8% and -
45.76% respectively. It is observed that the substantial change
in power gain is due to the body bias technique while in the
noise figure, it is due to the input matching network. The power
supply is also reduced from 1.5 V to 0.9 V using a body bias
technique.

T ABLE 3: Performance Comparisons of proposed LNA with previously

reported work

This
Re fe re nce s [4] [13] [14] [15] [16]
Work
CMO S
Te chnology 180 180 180 180 180 180
(nm)
Supply 1.8 0.6 1.0 1.0 1.8 0.9
Fig 13: Drain current (I D. i) of the proposed circuit Voltage (V)

Fre que ncy 2-10 2.4 2.4 2.4 2.4 2.4

(GHz )

Noise Figure 3.7-

2.88 3.7 3.7 3.14 1.505
(NF) 6.2

Powe r 48 0.84 1.2 7.6 - 2.507

(mW)
S 21 12.1 10.1 22 12.9 12.68 26.925
(dB) 2
S 11 < -10 - < -10 -13.1 -13.5 -11.989
(dB)
S 22 < -10 - < -10 - -10 -10.397
(dB)
S 12 - - - - -33.8 -53.030
(dB)

NFmin - - - - 1.9 1.331

Fig 14: Gate voltage (v g ) of the proposed circuit

A comparison of parameters with and without input matching

network and body bias technique is shown in Table 2 where IV. CONCLUSION
power gain, noise figure, and supply voltage are observed for
different design techniques. A common source LNA along with a cascode and cascade
stage has been presented in this paper. To optimize the
T ABLE 2: Parameters comparison with and without input matching network parameters of LNA, the body bias technique and the input
and body bias technique
matching network is used in the circuit. The proposed LNA is
implemented on 180n m CMOS technology at a frequency of
Without With Input With input
Input matching
2.4 GHz. The simulation is done using the ‘Advanced Design
Parame te rs matching
matching ne twork ne twork and System (ADS)’ software. First, the input matching network has
ne twork body bias lowered the noise figure up to a great extent, and second, a
significant increase in the gain of LNA is achieved with the
Power Gain (S21 ) 21.234 dB 21.803 dB 26.925 dB help of a body bias technique. On applying the input matching
network, the noise figure (N.F.) is reduced from 2.775 to 1.572,
which further is reduced to 1.505 after the body bias technique

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 Proceedings of the Fourth International Conference on Trends in Electronics and Informatics (ICOEI 2020)
IEEE Xplore Part Number: CFP20J32-ART; ISBN: 978-1-7281-5518-0
is applied. In other words, the noise figure is reduced by
45.76% in the proposed LNA. Another parameter of the
minimu m noise figure (NFmin ) of the proposed circuit is
observed to be as low as 1.331. The power gain (S21 ) has been
slightly increased from 21.234 d B to 21.803 dB with the help
of a matching network, but the major improvement is observed
by applying the body bias technique where S 21 is significantly
increased to 26.925 dB. So, the power gain (S21 ) is increased
by 26.8% in the proposed LNA. Other parameters i.e., S11 and
S22 are also below -10 dB which indicates that the circuit is
well matched at the input and the output. Moreover, the supply
voltage required for the proposed circuit is also reduced from
1.5 V to 0.9 V on applying a body bias technique. And, the
power of the circuit is found to be 2.507 mW. Hence, in this
paper, a low voltage LNA is presented for low power
applications to achieve high gain while keeping the noise figure
as low as possible.
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