2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)
Wideband Common Gate LNA With Novel Input
Matching Technique
Sana Arshad1,*, Rashad Ramzan2,Qamar-ul-Wahab3
*E-mail: sana@neduet.edu.pk
1
Electronic Engineering Department
NED University of Engineering & Technology, 75270, Karachi, Pakistan
2
United Arab Emirates University
P.O. Box 15551, Al-Ain, UAE
3
Linköping University, SE-581 83, Linköping, Sweden
Abstract-----In this paper, a novel architecture for wideband
input impedance matching consisting of two common gate (CG)
transistors is presented. One CG transistor is placed on top of the
other in a current reuse fashion such that both transistors appear
in parallel at the input. As a consequence, the transconductance
requirement for input matching from each NMOS transistor is
reduced to half compared to a simple CG LNA without effecting
the total gain. The proposed input matching technique achieves a
large bandwidth and high gain with comparatively small power
consumption. The designed UWB LNA is simulated using IBM
130nm CMOS process with Spectre RF. Post Layout simulation
results depict S11 and S22 better than -6.5 dB and -15 dB
respectively. The gain and 3 dB bandwidth are 15 dB and 2.1
GHz, respectively. The LNA demonstrates minimum NF of 3.7
dB at 3.53 GHz in the passband, input referred 1dBCP of −15.32
dBm with IIP3 of -10.5 dBm. The proposed LNA consumes only
2.6 mW with Vdd of 1.4 V.
Keywords----- CMOS LNA; common gate (CG); current reuse;
input impedance; inverter; UWB LNA; Wideband LNA.
I. INTRODUCTION
The Ultra Wideband (UWB) technology, existing from 3.1-
10.6 GHz has emerged as one of the most popular, most
researched and most promising wideband technology after
being declared commercial by the Federal Communications
Commission (FCC) in 2002. The extremely high data rate
together with large bandwidth, high protection, low cost and
low power makes it a suitable choice for various wireless
communication applications including IrDA, Wireless USB,
Bluetooth, Z-Wave, ZigBee, Body Area Network etc.
Besides, it has also been widely used in Biomedical
applications and vehicular tracking systems.
UWB Low Noise Amplifier (LNA) design is a great
challenge because the stringent requirements of good input
and output matching, reverse isolation, flat and high gain, low
noise figure, and high linearity shall all be met over a very
large frequency spectrum. Literature is full of UWB LNAs
implemented using the ever shrinking CMOS technology [1-4]
which has achieved fT as high as 280 GHz (45nm CMOS) [5].
While CG topology is successfully used as an input
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matching stage for UWB LNAs, Common Source (CS)
topology is usually avoided as it generally exhibits a
narrowband response. Obtaining wideband response requires
additional reactive components placed before the CS transistor
which actually serve as bandpass filter [4],[6]. Additionally,
noise characteristics of a CS based LNA vary directly with
frequency, thereby increasing Noise Figure (NF) at higher
frequencies. Moreover, due to Miller's effect, addition of a
cascode stage is required which requires more voltage
headroom thereby increasing power. The CG LNA, on the
contrary, excellent reverse isolation properties inherently. It
has a slightly higher but relatively constant noise figure
independent of both the operating frequency and bandwidth
[1-3]. Its input capacitance is easily resonated out by
adding an inductor at its source while its transconductance
helps to fix the 50Ω input impedance match. These features
makes CG LNA superior in performance compared to CS
LNA for wideband operation. A wideband CG LNA work
without a band pass filter at the input thereby saving area and
makes LNA design simpler.
In a conventional CG LNA, width of input transistor and
power consumption are governed by transconductance
required for input matching. In such LNAs, g of 20 mS is
theoretically required from input transistor for input matching
whereas values of 22-23mS are usually set to cater for
reflection of load impedance at the input [1]. The high power
consumption associated with this transconductance value can
be restricted using current reuse techniques which have proved
to be very efficient for low power designs [7-8]. To design a
low power CG LNA, we here propose a new input matching
architecture with the goal to use lesser current and achieve a
comparable gain as in standard CMOS CG LNAs. In our
proposed design, one CG transistor is placed at the top of
other such that the sum of transconductances of both
transistors provide the desired 50Ω matching. Thus input
matching is possible at approximately half the
transconductance/ current consumption value compared to
conventional CG LNA. The proposed LNA achieves
comparable performance with low power compared to
previously reported LNAs.
 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

VDD

C6 L4 Vb4
C7 M6
Vb2 R4 Vb6
M2 (1 / gm 6 ) ro 5
R2 M4 R6
M5 ≅ (1/gm6)
C2 L3 M6
C5
C8 L5 RFOUT
C3 L 2 C4
RFIN M3 C9 Fig. 2. Simplified schematic showing the 50 Ω output impedance
Vb1 M1 R3 M5
R1
R5 Capacitor C5 also presents an ac ground over the entire
Vb3
C1 Vb5 bandwidth of interest. The RF signal after amplification
L1
through M1 and M2 is coupled through C4 and C7 to the gain
Input Matching Gain Stage Buffer
stage (M3 and M4) again in a current reuse fashion. This stage
Stage provides additional gain to the LNA. Besides current reuse, the
Fig. 1. Proposed current reuse common gate LNA with novel input placement of M3 and M4 in an inverter configuration helps to
impedance matching architecture improve the linearity which depends on latter stage of the
LNA. The output of this stage is coupled through C8 to the
The paper is divided as follows. In section II, main design
buffer stage which also isolates the dc bias between these
concept, mathematical equations and circuit parameters are
stages. Series resonance of this capacitor with L5 and another
presented. Layout design and post layout simulation results are
resonance of L5 with input capacitance of M6 assist in
presented along with comparison with recent LNAs in section
extending bandwidth towards higher frequency spectrum of
III and the paper is finally concluded in Section IV.
desired band. The gain (A) of the LNA can be expressed as in
II. CIRCUIT DESIGN (4).
A. Design theory = −( ‖ )( +
2 4) (4)
Fig. 1 shows schematic of the proposed LNA. In input
matching stage, C1 and C2 couple input signal to the sources of where r and r are the drain to source resistances of M1 and
CG transistors M1 and M2 respectively. M2 is stacked at top of M2 respectively. g , g are the transconductances of M3 and
M1 which allows them to share the same drain current. They M4 respectively. sL and sL are the impedances of L and L
both act as input impedance matching device and their input respectively. Noise Figure for the proposed LNA can be
impedance appear in parallel at the input node as in (1). The written as in (5).
input impedance of either M1 (Z ) or M2 (Z ) consists of
inverse of sum of respective transconductance (g for M1 and =1+ + (5)
g for M2) and the gate to source capacitance (sCgs for M1
and sCgs for M2) present at the source node (2) - (3). L1 and
L3 resonate out sCgs and sCgs respectively as in simple CG where noise of gain stage has been neglected in accordance
LNAs. Thus, real part of input impedance (Z ) looking into the with Frii's formula. In (5), γ is a noise parameter (coefficient of
LNA is equal to inverse of the sum of the transconductances of channel thermal noise) for deep submicron MOSFETS and its
M1 and M2 only i.e. = 1⁄( + ). value can be much greater than 1 for short channel devices.
This resistive component is used to match the LNA input ≌ / 0 and its value can be much less than 1 for short
impedance to the source resistance. channel devices [9].
M5 and M6 implement output buffer needed for
= ‖ (1) measurements with standard 50Ω lab equipment. This buffer
is not needed in integrated implementations where mixer is
placed on chip eliminating the requirement of 50Ω output
= (2)
matching. Here, inverse transconductance of M6 (1/g ) and
the output impedance of M5 (r ), appear in parallel at the
output node of the LNA. By adjusting g = 50 Ω and a high
= (3)
r , 1 g ‖r reduce to 1/g only, shown in Fig. 2. In this
way, output impedance matching is achieved through the
The gates of M1 and M2 are kept at ac ground with the help of buffer.
C3 and C6. L and L serve as load for M1 and M2 respectively The gate bias of all transistors is provided through current
and carry same bias current. The combination of inductors L , mirrors. Input matching stage is biased at 0.53 mA while gain
L and capacitor C5 make a third order LC-T network and stage carries 1.34 mA. Buffer is biased separately with a
provides adequate isolation between both M1 and M2. power supply of 1 V.

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 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

-5

-10

S11 (dB)
-15

-20
Post Layout Simulation
Pre-Layout Simulation
-25
Fig. 3. Layout of the proposed LNA with an area of 1.1 x 0.67 mm2 4 2 5 63 7
Frequency (GHz)
excluding bondpads Fig. 4. Pre and Post Layout Simulated Input Reflection
Coefficient (S11) of the LNA
0
B. Circuit Parameters
From (1), g = g = 10mS, ideally, and simulations are -10

S22 (dB)
started with this value. After rigorous simulations and keeping
in view low power requirement, transconductance values are -20
adjusted to g = 9.3mS and g = 8.3mS respectively by
-30
setting M1 and M2 for gate widths of 40µm and 30µm Post Layout Simulation
respectively. With these values, S11 values as low as -15dB are Pre-Layout Simulation
-40
obtained in passband. Increasing gm's above the 2 3 4 5 6 7
Frequency (GHz)
aforementioned values only increase power consumption Fig. 5. Pre and post layout simulated output reflection coefficient
without much difference in S11. Hence above values are (S22) of the LNA
retained. 20
Inductors L , L are selected to be 7.6 nH each. They
resonate with gate to source capacitances plus other parasitic 10
capacitances present at source nodes of M1 and M2
S21 (dB)

respectively to create resonances at lower end of frequency 0

spectrum near 3.8 GHz and 4.5 GHz (pre-layout simulation).
-10 Post Layout Simulation
L appears at the drain of M1 and at the gate of M3 while L is Pre-Layout Simulation
at the junction of drain and gate of M2 and M4 respectively.
Iterative simulations are done after which desired gain is -20
4 2 5 3 6 7
obtained for widths of M3 and M4 as M3 = 85µm and M4 = Frequency (GHz)
Fig. 6. Pre and post layout simulated power gain (S21) of the LNA
110µm while L = 8 nH, L = 6.6 nH and L = 7.6 nH. These
component values are chosen to obtain a wideband gain 10
response by creating multiple resonances in the desired
spectrum. Buffer transistors width are adjusted as M5 = 31µm
and M6 = 20.9µm to facilitate output matching discussed in
NF (dB)

Section II. The total power consumption of LNA core is 2.61 5

mW from a 1.4 V supply. The gate bias values of M1 through
M6 are shown in Table I. Post Layout Simulation
Pre-Layout Simulation
III. SIMULATION RESULTS AND LAYOUT 0
4 2 5 3 6 7
Frequency (GHz)
Layout of the proposed LNA, designed in 130 nm CMOS, Fig. 7. Pre and post layout simulated Noise Figure of the LNA
is presented in Fig. 3 which has an area of about 0.74 mm2 with minimum NF of 3.7dB @ 3.53 GHz
(1.1 x 0.67 mm2) excluding bondpads. The layout is designed 5
Output Power (dBm)

to facilitate on-chip probing hence 150 µm GSG pads are used 0

at input/ output of the LNA. DRC, LVS, QRC, floating gate,
Orthogonality tests and post layout simulations are -10

P1dB = -15.32 dBm

TABLE I. GATE VOLTAGES OF TRANSISTORS -20
Transistor Gate voltage Transistor Gate voltage
(volts) (volts) -30
-30 -40 -20 -10 0
Vb1 0.45 Vb4 0.83 Input Power (dBm)
Vb2 1.4 Vb5 0.44 Fig. 8. Simulated input referred 1 dB CP (−15.32 dBm)
Vb3 0.45 Vb6 1

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 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

Output Power (dBm)

0 the design and on-chip-probing for measurement, can give
very accurate results, similar to the ones, presented after post
layout simulations. This is because the chip, and probes used
for testing are in the same measurement plane. No de-
-50
IIP3 = -10.5 dBm
embedding of the measured data is required in this case. De-
embedding is required when chip is mounted on PCB for
measurement.
-100
-40
-30 -20 -10 0
Table-II compares performance of proposed LNA with
Input Power (dBm) other reported LNAs designed in comparable technology
Fig. 9. Simulated input referred third order intercept Point
(−10.5dBm )
nodes and having similar specifications. Our proposed LNA
offers much larger bandwidth and gain with reduced power
successfully performed on the LNA layout. consumption.
Fig. 4 and 5 present input and output reflection coefficient
for the LNA respectively. While post layout S11 remains below IV. CONCLUSION
-10 dB from 2.6-4 GHz, S22 remains below -15 dB throughout The paper presents the design of a new common gate LNA
the bandwidth of interest. In Fig. 6, Power gain of the LNA is in which each CG NMOS of matching stage is biased at
presented. Pre-layout simulation shows a maximum gain of 15 almost half the transconductance compared to a conventional
dB and 3 dB bandwidth of 4GHz (2.5-6.5 GHz) whereas the common gate LNA, thus reducing the overall power
bandwidth reduces to 2 GHz after post layout simulation. consumption without effecting the gain. Post Layout
Thus, effective bandwidth for the LNA exists from 2.3-4.4 simulation results shows S11<-6.5 dB, S22<-15 dB, maximum
GHz. A decrease in S21 bandwidth and improvement in S22 is gain 15 dB, average NF of 5.3 dB. Input referred P1dB and
visible when pre and post layout results are compared. This is IIP3 are -15.32 dBm and -10.32 dBm respectively. The
an outcome of tradeoff that arose during pre-layout proposed LNA achieves high gain, wider bandwidth together
simulations due to tuning of L5 with capacitances appearing with smaller power consumption which makes it a good
around it. Capacitance values were then adjusted for extended choice for wideband receivers in portable battery powered
S21 bandwidth while compromising S22. In the layout, communication nodes.
excessive parasitics are introduced in form of capacitances due
to insertion of tie down diodes at various nodes. This REFERENCES
deteriorated gain and S22 got improved. Not shown is the [1] M. Khurram et al, “A 3–5 GHz Current-Reuse gm-Boosted CG LNA
reverse isolation of the LNA which remained below -50 dB in for Ultrawideband in 130 nm CMOS,” IEEE TVLSI,Vol. 20, No.3, 2012.
both pre and post layout simulation. Noise Figure of the LNA [2] S. Arshad et al, “A sub-10mW, noise cancelling, wideband LNA for
UWB applications,” AEU vol. 69, pp.109–118, 2015.
is shown in Fig. 7. The minimum NF achievable in the
[3] H. Zhang, X. Fan and E. S. Sinencio, "A Low-Power, Linearized, Ultra-
passband is 3.7 dB while average NF is 5.3 dB from the post Wideband LNA Design Technique", IEEE JSSC.,vol.44,no.2, Feb. 2009.
layout results. Linearity tests gives 1 dB compression point to [4] C. W. Kim et al, “An Ultra-Wideband CMOS Low Noise Amplifier for
be -15.32 dBm as shown in Fig. 8. Two tone test is performed 3–5-GHz UWB System,” IEEE JSSC., vol. 40, no. 2, 2005.
using tones of 3 GHz and 3.01 GHz which gives input referred [5] R. Ramzan et al, “Figure of merit for narrowband, wideband and
multiband LNAs,” Intl. J. of Elect., pp.1603-1610, vol. 99, No. 11, 2012.
third order intercept point to be -10.5 dBm as shown in Fig. 9.
[6] A. Bevilacqua et al, “An Ultrawideband CMOS Low-Noise Amplifier
It can be summarized that due to the addition of parasitics in for 3.1–10.6-GHz Wireless Receivers,”IEEE JSSC,vol.39,no.12, 2004.
the Layout the post layout simulation results deviate [7] N.Ahsan et al, “A 1.1V 6.2mW, Wideband RF Front-end for 0dBm
somewhat from the pre-layout results. However, fabrication of Blocker Tolerant Receivers in 90nm CMOS,”JAICSP,vol. 70, no. 1, pp.
79- 90, 2011.
[8] W. H. Chen et al “A Highly Linear Broadband CMOS LNA Employing
TABLE II. PERFORMANCE COMPARISON OF THE PROPOSED LNA Noise and Distortion Cancellation,” IEEE Proc. RFIC, pp. 61-64., 2007.
Ref no. [1] [8] [10] [11] [12] [13] This [9] D. K. Shaeffer et al, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,”
work IEEE J. of Solid-St. Cir., vol. 32, no. 5, pp. 745-759, 1997.
Tech 130 130 180 180 65 180 130 [10] S.-S. Song et al, “A Highly Linear Wideband CMOS Low-Noise
(nm) Amplifier Based on Current Amplification for Digital TV Tuner
Freq 3.1- 0.8 0.02 0.3 0.2 3 2.3-4.4 Applications,” IEEE MMCL, vol. 18, no. 2, pp. 118–120, Feb. 2008.
(GHz) 4.8 - - - - - [11] S. Woo et al, “A 3.6mW Differential Common-Gate CMOS LNA with
2.1 1.18 0.92 5.2 4.8 Positive-Negative Feedback,” IEEE Proc. ISSCC, pp. 218-219, 2009.
S11 (dB) <-8 ≤-6 ≤-10 ≤-10 <-14** <-10 -6.5 [12] S. C. Blaakmeer et al ,“ Wideband Balun-LNA With Simultaneous
Gain (dB) 13 14.5 20.5 21* 15.6* 15 15 Output Balancing, Noise-Canceling and Distortion-Canceling,”IEEE
NFmin 3.5 2.6 3.3 2 2.9** 3.5 3.7 JSSC, vol. 43, no. 6, June 2008.
(dB) [13] C. P. Liang et al, “Analysis and design of two low-power ultra-wideband
IIP3 -6.1 +16 2.7 -3.2 3.9** N/A -10.5 CMOS low-noise amplifiers with out-band rejection,” IEEE MTTS vol.
(dBm) 58, no. 2, pp. 277–286, Feb. 2010.
Power 3.4 17.4 32.4 3.6 14 5 2.6
( mW)
*voltage gain **estimated from graph

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