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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS 1

A V-Band Current-Reused LNA With a

Double-Transformer-Coupling Technique
Sunwoo Kong, Member, IEEE, Hui Dong Lee, Moon-Sik Lee, and Bonghyuk Park

Abstract— This letter presents a current-reused V-band

low-noise amplifier (LNA) with a double-transformer-coupling
technique in 65nm CMOS technology. A couple of common-
source (CS) stages are stacked to share current, and the double
transformers are used as an RF signal path between the CS
stages for both gain and stability considerations. The LNA has
three CS-CS stages, and achieves a peak gain of 31.4 dB, a
minimum noise figure (NF) of 4.7 dB, and a P1dB of −2 dBm over
62.9-67 GHz with a power consumption of 6 mW. The chip size
is 0.66 × 0.90 mm2 including pads.
Index Terms— CMOS, current-reuse, low noise ampli-
Fig. 1. Circuit schematic of the proposed LNA with the double-transformer-
fier (LNA).
coupling technique.

I. I NTRODUCTION
Another approach is to use a current-reused CS-CS topology in
T HE requirement for high-data-rate wireless communica-
tion has been growing as users increasingly consume
content on their mobile devices. The unlicensed millimeter-
which the parasitic capacitance at the drain of the bottom CS
stage is rather used as an LC-resonator with the inductor at the
drain [2]. In addition, the high-Q factor of a series LC-network
wave (mm-wave) range is receiving greater attention because
at the gate of the CS stage boosts the gain compared to that of
of the available wide-bandwidth. Generally, III-V compound
the CG stage [3]. This high-Q factor provides a wide enough
semiconductor technology is used for mm-wave applications.
bandwidth in the case of the mm-wave operation. However,
It has higher ft and f max than CMOS technology because
the CS-CS structure has a stability issue. The feedback capac-
CMOS technology suffers from device parasitics and substrate
itance of the CS stage potentially causes instability with
losses. Still, there have been many attempts to adopt CMOS
an LC-load. Furthermore, it needs an additional RF path
technology to the mm-wave range because it has the advan-
between the bottom CS stage and the upper one, as opposed to
tages of low cost and a high-level of integration, and modern
the cascode structure. The additional size from the matching
CMOS technology has tried to overcome the frequency limit
circuit also should be considered.
of operation.
In this letter, we propose a current-reused CS-CS LNA
CMOS amplifiers use multiple stages to compensate the
with a double-transformer-coupling technique. The double
relatively low performance at high frequency. The more stages
transformers improve the gain and the stability with a compact
are used, the more power is consumed. Stacking MOSFETs is
size of the matching circuit, and the CS-CS structure improves
a promising solutions to satisfy the requirements for low power
power consumption and noise performance.
consumption and high performance. In general, an LC-tank is
used as a high-frequency load, and it mitigates the voltage II. C IRCUIT D ESIGN
headroom problem. A cascode amplifier is a typical current-
Fig. 1 shows the proposed LNA. Let the first stage be the
reused structure in which a common-gate (CG) stage is stacked
representative example. The MOSFETs M1 and M2 have a
on a CS stage. The source-drain isolation of the CG stage
CS configuration that adopts the capacitor Cc1 because the Cc1
mitigates the stability problem of the gate-drain capacitance
acts as an AC ground. The RF signal from M1 is transferred to
of high-frequency amplifiers. However, the cascode amplifier
M2 by the transformer T F1 which consists of two transformers
has high-frequency noise and gain degradation because of
T F1 A and T F1B using the inductors L g , L d , and L s .
the parasitic capacitance at the drain of the CS stage [1].
Manuscript received April 26, 2016; revised June 28, 2016; accepted A. Double-Transformer-Coupling Technique
August 4, 2016. This work was supported by the Institute for Information
and Communications Technology Promotion (IITP) Grant funded the Korea Inductive coupling can be used to transfer a signal from the
Government (MSIP) (No. R0101-16-244, Development of 5G Mobile Com- bottom CS stage to the upper one. We propose an LNA which
munication Technologies for Hyper-connected smart services)
The authors are with Electronics and Telecommunications Research Insti- uses double transformers for the inductive coupling in Fig. 1.
tute, Daejeon 34129, Korea (e-mail: swkong@etri.re.kr; leehd@etri.re.kr; The transformers can boost the voltage gain by controlling the
moonsiklee@etri.re.kr; bhpark@etri.re.kr). turns ratio of the primary winding to the secondary one. The
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org. directions of the double transformers can also be used to boost
Digital Object Identifier 10.1109/LMWC.2016.2615017 the gain. The secondary windings at the gate and the source
1531-1309 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS
Fig. 2. Simulation results of current-reused LNAs which have T F1 A with
T F1B , T F1 A with L s , and T F1 A without L s , respectively, and a cascode
LNA: (a) maximum available gain, (b) minimum NF, and (c) μ-factor.
of the upper CS stage are in opposite directions, and this
enlarges the effective gate-source voltage swing. The double
transformers improve both the gain and stability. The L s
contributes to the stability [4]. The performance degradation
due to pursuing the stability of the amplifier is compensated
by using the double transformers from a different perspective.
Fig. 2 compares simulation results of the proposed LNA and
three other types of LNAs. All four LNAs use the same two
NMOSs for a fair comparison. The proposed current-reused
LNA uses the effect of the double transformers T F1 A and
T F1B . The other two current-reused LNAs use the effect of
the single transformer T F1 A with and without L s , respectively.
The cascode LNA has a CS-CG structure without the trans-
formers. The proposed LNA has the highest stability factor,
the lowest NFmin , and the highest maximum available gain
when μ > 1.
B. Implementation of the LNA
Fig. 3(a) shows the small signal model of the CS-CS
structure of the shaded area in Fig. 1. The voltage v i is seen
at the drain of M1 . The simple equivalent circuit model of
the transformer T F1 is composed of two ideal transform-
ers T Fdg and T Fds including equivalent lumped elements:
L zg and L zs . The lossy factors of the elements are neglected.
The equivalent impedance, which is seen at the primary side
of the transformer, is transformed to Z ig and Z is which are
seen at the secondary side of the gate and the source, and
Z igs = Z ig + Z is . The Z gs is the input impedance of M2
with L zg and L zs . The C gs is the input capacitor of M2
and gm is the transconductance of M2 . The Z gs is equal to
1/j ωC gs + j ω(L zg +L zs )+gm L zs /C gs . The mutual inductance
between L g and L s is not considered here to give a clear
description. The L d and L g form the transformer T Fdg of
turns ratio 1:n g , and L d and L s form the transformer T Fds
of turns ratio 1:n s . The voltages v g and v s are induced at
the secondary windings of T Fdg and T Fds , respectively. The
overall transconductance G m = i o /v i can be expressed as
gm (n g + n s )
Gm =
1+gm Z is −ω C gs (L zg + L zs )+ j ω(gm L zs + Z igs C gs )
2
(n g + n s )
= (1)
j ω0 (L zs + Z igs C gs /gm )

where ω0 ≈ 1/ C gs (L zg + L zs ) when gm Z is  1. The G m
is boosted by (n g + n s ) without additional power consumption
Fig. 3. (a) Small-signal model of the CS-CS topology with the double
transformers. (b) Design of the double transformers.
Fig. 4. Chip photo of the proposed LNA.
compared to the overall transconductance, which does not con-
tain the mutual inductance of the transformer. The L zs reduces
G m because G m = (n g +n s )/j ω0 2L zs , where Z igs ≈ Z gs (ω0 ).
The L zs makes a trade-off relation between the stability and
overall transconductance [4]. In conclusion, a large n g + n s
and an optimum L zs are needed. The layout of the transformer
is shown in Fig. 3 (b). The turns ratios n g and n s are 1.33 and
1.81, respectively. The capacitor Cc1 plays roles of providing
stable AC grounds and boosting the voltage across L d of the
LC-resonant circuit which results in a boosted n g + n s . The
large inductance is good to make large coupling coefficients
of transformers but L d should be designed for a resonant load
of M1 , and L g and L s should keep ω0 . The ratio of n g /n s is
decided after the trade-offs of L zs is considered. In Fig. 1, the
input and output impedances of the shaded area are expressed
as Z in = 20 − j 175 and Z out = 21.5 − j 145, respectively.
The input and output inductors are used as inductive dividers
to match 50 Ohms. All of the inductor and transformer models
were obtained using ADS Momentum. The chip was fabricated
using TSMC 1P9M 65nm process.
The channel current noise of M1 is the dominant noise
source of the LNA. In the design of the source-degeneration
LNA, small transconductance of M1 is a good solution for the
low NF [5]. However, the small transconductance results in
low gain of the LNA. The current-reused structure improves
the overall gain while keeping the transconductance small. The
additional noise source of M2 can be reduced using the double-
transformer-coupling technique. The NF of the network of M2 ,
in Fig. 3(a), is expressed as
(n 2g + n 2s )gm Z i γ (ω0 /ωT )2
N FM2 = 1 + (2)
(n g + n s )2
where γ is a bias-dependent factor. Here, (n 2g +n 2s )/(n g +n s )2
improves the NF, and it shows the lowest NFmin in Fig. 2(b).
III. M EASURED R ESULTS
Fig. 4 shows a photomicrograph of the fabricated chip,
which measures 660 μm × 900 μm. All measurement results
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KONG et al.: V-BAND CURRENT-REUSED LNA WITH A DOUBLE-TRANSFORMER-COUPLING TECHNIQUE
TABLE I
S TATE - OF - THE - ART V- BAND CMOS LNAs
Fig. 5. Measured and simulated results of the proposed LNA: (a) S-parameter
and NF, (b) 1dB compression point.
were obtained using on-wafer RF probing with a chip power
consumption of 6 mW from a 1.2V power supply. The mea-
sured and simulated S-parameters and NF results are shown in
Fig. 5 (a). The peak gain (S21) was 31.4 dB at 64.4 GHz. The
electromagnetic simulation overestimated the inductance and
Q-factor of the inductors so there are disparities between the
measured and simulated results. The measured S-parameter
was limited by the upper frequency of 67 GHz because of
the performance of the measurement equipment. An Anritsu
37397D vector network analyzer was used to measure the
S-parameter. The measured minimum NF was 4.7 dB at
64 GHz and the average value was 6.6 dB over the measured
data. The NF measurement was conducted using an Agilent
N8975A NF analyzer with a Quinstar QNS-FB15LV noise
source. A custom V-band down-mixer was used to extend
the frequency range. An Agilent 8267D signal generator with
an OML S15MS-AG mm-wave source module was used as a
local oscillator for the mixer. Fig. 5 (b) shows the measured
and simulated 1dB power compression point. The measured
output P1dB was −2 dBm. The compression point was
measured using an Agilent E4440A spectrum analyzer with
an Agilent 11974V mixer for a frequency range extension.
Table I describes recent state-of-the-art V-band CMOS LNAs.
It shows that this work has the best power-efficient gain. The
proposed LNA has the highest gain and the third lowest power
consumption in Table I with the comparable NF and OP1dB
performance. It has a relatively narrow bandwidth due to the
input network of the CS stages. The proposed LNA has the
3
best figure of merit (FOM) of 5.35. The bandwidth for the
FOM of this work was based on the simulation result, 6 GHz,
because of the limitation of the measurement equipment.
IV. C ONCLUSION
A current-reused V-band LNA with a double-transformer-
coupling technique was presented. The LNA achives a 31.4dB
peak gain, a 4.7dB minimum NF, and a −2dBm P1dB over
62.9-67 GHz with a 6mW power consumption. The chip
size is 0.66 × 0.90 mm2 including pads, and 1P9M 65nm
CMOS technology is used. The double-transformer-coupling
technique was analyzed using a small signal model, and it
demonstrated a stable power-efficient gain. The proposed LNA
showed the best FOM in comparison with recent low-power
high-performance CMOS V-band LNAs.
ACKNOWLEDGMENT
The authors would like to thank Dr. J. -S. Rieh and
Dr. D. Yoon, both with Korea University, Seoul, Korea, and
Dr. I.-Y. Oh, Wisejet, Daejeon, Korea, for their help on the
NF measurement.
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