Impact of impurities, interface traps and contacts on
MoS2 MOSFETs: modelling and experiments
Gioele Mirabelli, Farzan Gity, Scott Monaghan,
Paul K. Hurley, Ray Duffy
Tyndall National Institute, University College Cork
Lee Maltings Complex, Cork, Ireland
Abstract— Device modelling is a key enabling capability for
the semiconductor industry, especially for process optimisation,
and for insight into the physics of novel architectures and
materials that are difficult to access experimentally. Despite
much innovative experimental work, device modelling
capabilities for field effect devices based on Transition Metal
Dichalcogenide (TMD) channel materials are at an early stage of
development. Properly formulated physics-based models would
give a substantial improvement for time- and cost-effective
development of TMD devices. In this work, experimental device
data was used to develop models and parameter sets in the
continuum-based Synopsys Sentaurus Device software.
Specifically, few-layer MoS2 Field-Effect-Transistors (FETs)
were systematically electrically characterized, and the modelling
of the experimental data focused on the impact of impurities,
interface traps, and contact barriers. Furthermore, the
experimental MoS2 FETs device characteristics, combined with
the physics based transport models, suggests that the low
experimental electron mobility values are a result of a high
density of charge impurity defects in the MoS2 channel. To the
best of our knowledge continuum-based TCAD device models did
not previously exist for MoS2, or TMD-semiconductors in
general.
Keywords—MoS2; Device Modeling; Impurities; Electrical
characterization; Physics;
I. INTRODUCTION
In recent years the interest in 2D-semiconductors, and
Transition-Metal-Dichalcogenides (TMDs) in particular, has
increased noticeably. Due to their intrinsic 2D nature the
electrostatic control of the gate is higher with respect of 3D-
semiconductors, making them more immune to Short Channel
Effects [1]. One of the issues associated with 2D-materials is
the lack of a suitable large-area growth technique, which
limits the systematic study TMD materials grown over large
are substrates. Often, TMD films are characterized by defects
or grain boundaries, which can limit their electrical
performances. Therefore, most of the experimental results in
literature have been obtained from flakes mechanically
exfoliated from bulk crystals. To date these have shown the
best electrical results, with high on/off ratios, low inverse
subtreshold slopse and carrier mobilities in the range of tens of
cm2V-1s-1 [2].
Nevertheless, a large concentration of impurities was
reported in TMD crystals [3], and if in a charged state, these
impurities will degrade the carrier mobility and resistivity of
the material [4] especially in TMD films comprised of a small
(1-10) number of monolayers [5]. In the first part of this work,
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we report the electrical characterization of back-gated MoS2
FETs. Based on the experimental device characteristics a
model and parameter set for MoS2 was implemented in the
continuum-based Synopsys TCAD simulator Sentaurus
Device, which showed consistent behavior with the
experimental data. Charged impurity concentrations, interface
states and MoS2/metal contact barriers were varied to explore
the parameters which influence carrier transport in MoS2
FETs.
II. EXPERIMENT
The experimental procedure is reported in Fig. 1.
Mechanical exfoliation with scotch tape was used to obtain thin
flakes from a MoS2 bulk crystal. The flakes were transferred on
a substrate of 85 nm of dry thermally grown SiO2 and a highly-
boron doped Si handle wafer. The height of the flakes was
established by optical color-contrast to be 3-4 layers [6]. Ti/Au
metal contact pads and electrodes were defined by electron-
beam lithography, followed by metal evaporation and lift off
process. 15 kV beam exposures were performed with a Zeiss
SUPRA SEM with a Raith Elephy Plus blanker. An adhesion
layer of 5 nm of Ti and 45 nm of Au were deposited with e-
beam evaporation. For structural analysis, cross-section
samples were obtained by FEI’s Dual Beam Helios Nanolab
600i system using Ga ion beam. Cross-sectional Transmission
Electron Microscopy (XTEM) imaging was carried out using a
JEOL 2100 HRTEM operated at 200 kV in Bright Field mode
using a Gatan Double Tilt holder. Electrical characterization
was performed on a wafer at 25oC in a dry/dark environment
using the HP4156C parameter analyzer.
III. MATERIAL AND ELECTRICAL ANALYSIS
Fig. 1 shows the Scanning Electron Microscope (SEM) and
cross-sectional Transmission Electron Microscope (TEM)
Fig. 1: Top: summary of the experimental process flow and optical image
of the contacted MoS2 flake. Bottom: (a) SEM top-view of the MoS2 device
after contact deposition. (b) Representative high-resolution TEM image
showing the layered structure of the sample.
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Fig. 2: Transfer characteristics of the Trapezium for different drain-source
voltages. Inset: transfer characteristics of the Kite and the Triangle at Vds=1V.
images of the “Trapezium” device, so named because of its
shape. The device width is approximately 3.5 µm along the
length of the sample and the channel length is confirmed to be
1 µm as determined after the metal deposition. The TEM cross
section of the same device, confirms the 3-layers thickness
implied by optical contrast.
Fig. 2 shows the transfer characteristics of the device for
different Vds. The transfer characteristics at Vds=1V are
presented in the inset of Figure 2 for two other back gated
MoS2 FETs, termed the “Kite” and the “Triangle” based on
the MoS2 flake shapes on which the devices were made. These
devices are also 3L thick. The electrical results among the
three devices are highly consistent. The drain current at a back
gate voltage of 7.5 V and a drain-source voltage of 1V is ~50
nA/µm, limited probably by contact resistance and/or low
mobility. The off-current is limited by the sensitivity of the
measurement system, hence could potentially be lower. The
MoS2 flakes reported here were exfoliated from the same bulk
material onto the same SiO2/Si substrate and experienced the
same process steps and environment-related exposure. As a
consequence, the slight variability among these devices is
most probable related to intrinsic factors only, such as defects
[7], grain boundaries and/or impurities [8], as opposed to
process-related factors such as metal contacting [9] or air
exposure [10].
To compare the characteristics of the devices field-effect
mobility values were extracted from the derivative of the
transfer characteristics. Fig. 3a shows the field effect mobility
values plotted against carrier concentration, evaluated
considering a linear charge dependence on the gate voltage
overdrive. Due the low back-gate voltage (maximum value is
7.5 V) and the relatively thick back gate oxide (85 nm of SiO2)
the vertical field contribution to mobility degradation is not
expected to be a significant contribution. This is confirmed in
Fig. 3, where the field effect mobility increases with the
calculated carrier density.
Fig. 3: (a) Field effect mobility versus carrier density extracted from the
transfer characteristic at Vds=1V. (b) Impurity concentration extracted from
the mobilities in part (a) using eq. (1).
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Ma and Jena [11] reported a systematic study of carrier
transport in 2D crystals, which are found to be highly
dependent on the dielectric environment and ionized impurity
density. In particular, the mobility versus electron density for
low carrier concentration follows the relationship
(1)
where µCI is mobility, NCI is ionized impurity concentration
and ACI is a fitting parameter that depends on the dielectric
environment. Considering that ne can be obtained
experimentally, impurity concentration can be extracted by
fitting the equation with the field-effect mobility of the
devices. Fitted data in [11] shows an impurity concentration of
1013 cm-2, while in [12], where the same method is used,
different levels of impurity concentration (1011 and 1013 cm-2)
have been reported, probably due to the high variability of
TMDs and film/device preparation conditions. This is also
consistent with the relationship of Hall effect mobility to
doping concentration observations in natural and synthetic
TMD crystals [4].
Fig. 3b shows the impurity concentration level for each
device, extracted from fitting the mobility using eq. (1). The
average impurity concentration is 4×1013 cm-2. Similar levels
of impurity were found before by ICMPS analysis on MoS2
crystals [3]. The target in the ITRS roadmap [13] for
unintentional impurity concentration in semiconductors
intended for logic device application is for values less than
5×1010 cm-2.
IV. TCAD SIMULATIONS
To understand the implications on the electrical performance of
such a high impurity concentration the Synopsys TCAD
simulator Sentaurus Device [14] was used to develop a model
and parameter set for MoS2. To date a clear model for MoS2 is
still missing. Due to the lack of a proper growth process, the
low yield of the mechanical exfoliation and the high variability
of TMDs it is difficult to obtain consistent results and have
systematic experiments. The use of a TCAD simulator allows
an investigation of what the physical processes are currently
limiting device performance.
A schematic cross section of the structure used for
simulation studies is shown in Fig. 4. This replicates the actual
structure used in the experimental section. The main
parameters for MoS2 are obtained from literature. Some of the
parameters, such as band-gap [15] and in-plane dielectric
constant [16] are dependent on the actual thickness of the
MoS2. Then, to match the experimental results of the
Trapezium a mobility model dependent on impurities, defective
Fig. 4: Schematic of the device structure implemented in Sentaurus device
and the main parameters. The symbol * denotes thickness-dependent
parameters.
 contacts and interface traps were implemented. The Unified
Philips mobility model was used to take into account the
impurity dependency [17]
where µCI is the mobility dependent on coulomb impurities,
and
(3)
where ND and NA are the ionized donor and acceptor
concentrations, p is the hole concentration, G(Pe) and F(Pe) are
analytical functions describing minority impurity and electron
hole scattering. fe is a fitting parameter equal to 1. µe,N and µe,C
depend on the maximum and minimum mobility values, set as
1000 and 9 cm2V-1s-1 respectively [10]
The model proposed in [11] was used as reference and the
main parameters, i.e., Nref and α, are found to be 4×1018 cm-3
and 1.0 for monolayer MoS2. As reported in Fig. 5, these
values of Nref and α reproduce the magnitude and trend of the
relationship between mobility versus charged impurity density
reported for MoS2 in Ref. [11], especially for high impurity
concentration, which is the region of most interest for this
study. Impurities are introduced as mid-gap “fixed charges”,
which in Sentaurus are traps always completely occupied.
Furthermore, barriers were used at the contact to take into
account the high Schottky barriers usually found in TMD-
FETs. The value used to match the experimental results of the
Trapezium is 0.17 eV, which is close to the experimentally
reported value [18]. Fig. 6 illustrates the impact of the Schottky
barrier height at the metal/MoS2 interface on the transfer
characteristics.
The subthreshold behavior of the device is also dependent
on interface traps located at the SiO2/MoS2 interface of the
back gated device structure. To model the stretch out of the
experimental transfer characteristic, acceptor like interface
1000
100
Mobility (cm2/V.s)
Nref=6e18
α=1.2
α=1.0
10 Nref=4e18
α=1.2
α=1.0
Model from [11]
1
109 1010 1011 1012
Impurity Concentration (cm-2)
Fig. 5: Mobility versus impurity concentration considering different
parameters implemented using the Unified Philips mobility model. The
model is based on theoretical calculations for MoS2.
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(2)
(4)
Fig. 6: Simulated transfer characteristics varying the barrier at the source and
drain contacts. Inset: same curves in linear scale.
states are introduced close to the MoS2 conduction band edge
[19]. In order to match the subthreshold behavior of the
Trapezium 4 trap energies are introduced, with energy levels at
Et1=1.25kT, Et2=2.5kT, Et3=5kT and Et4=10kT from the
conduction band and with concentration of 8×1011, 3×1011,
(5) 2.5×1011 and 1×1011 cm-2, respectively.
Fig. 7 illustrates the difference in the subthreshold behavior
of the device without any interface traps, with Et1 and Et2 only
(the traps closest to the conduction band), and Et3 and Et4 only
(6) (the traps closest to the mid-gap). A schematic of the trap
energy levels is presented as inset in Fig. 7. As expected the
traps closest to the mid-gap affect more the subthreshold
behavior, while the ones close to the conduction band affect the
on-current. Fig. 8 compares the experimental and the simulated
data, with an impurity concentration of 4×1013 cm-2.
Since the model and the parameter set are in good
agreement with the experimental data, it can be used to gain a
deeper understanding of the main physical processes which are
limiting the drain to source current of the back gated MoS2
MOSFETs, focusing on the impact of the impurity
concentration. Fig. 9a shows the field-effect mobility of MoS2
FETs (Vds=0.1V) varying impurity concentration for a
different number of layers (no interface traps or contact
barriers are considered). As can be seen, the mobility is highly
dependent on charged impurity concentration and it is
probable that the experimental field effect mobility values
extracted to date have been significantly influenced (degraded)
due to the high impurity concentration.
Experimentally, mobility shows a peak between 5-10
layers [20], but are highly sensitivity to adsorbates on the
1013
Fig. 7: Simulated transfer characteristics using acceptor traps at different
energies. Inset: schematic of the trap energy levels with respect of the MoS2
bandgap. The transfer characteristics are shifted negatively along the back
gate voltage by changing the gate work function. This shift is to match the
shift in the experimental characeristics.
290

Fig. 8: Transfer characteristics of the experimental and the simulated devices in
semi-log and linear scales considering an impurity concentration of 4x1013 cm-2,
0.17eV of contact barriers and interface traps at energy levels at Et1=1.25kT,
Et2=2.5kT, Et3=5kT and Et4=10kT from the conduction band and with
concentration of 8×1011, 3×1011, 2.5×1011 and 1×1011 cm-2, respectively.
Fig. 9: (a) Field-effect mobility versus number of MoS2 layers considering
different impurity concentration. (b) Countour plot of the electron density near
the drain contact for 2 layers of MoS2. Both the plots are evaluated at Vds=0.1V
and Vbg=7.5V.
surface, especially for few layers [21]. Therefore, due to the
several imperfections of the material itself, it is possible that
these trends might differ when testing purer MoS2. Also, the
experimental values of mobility we reported are lower with
respect to what is given by the model.
To investigate the field effect mobility further the electron
density near the drain contact was considered. Fig. 9b shows
the electron contour plot around the drain contact for a 2
layers MoS2 back gated device. Since it is a back-gated FET a
change in carrier density from the SiO2/MoS2 interface to the
top metal contact exists, resulting in carrier transport
perpendicular to the MoS2 planes under the contact region.
Thus, the mobility versus thickness trend might be different
considering top-gated or back-gated FETs. Also achieving a
highly doped MoS2 under the drain and source metal contacts,
will significantly reduce contact resistance [22].
V. CONCLUSIONS
In conclusion, MoS2 FETs were electrically characterized
from which continuum-based models and parameter sets were
developed. It has been show that the experimentally extracted
field-effect mobility values are strongly dependent on the
impurity concentration present in the material. The trend was
confirmed by TCAD simulations, which also showed the
impact of interface trap density and contact barriers on the
electrical device behavior. Even if promising results are shown
to date the true TMD device performance is still masked by
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imperfections, which can be tackled by optimizing the growth
and device processing conditions.
ACKNOWLEDGMENTS
We acknowledge the support of SFI through the US-Ireland
Partnership Programme Grant No. SFI/13/US/I2862 (UNITE)
and of the IRC through the Postgraduate Scholarship
EPSPG/2015/69. The research was supported in part by the
HEA Programme for Research in Third Level Institutions in
Ireland under Grant Agreement No. HEA PRTLI5.
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