IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO.
12, DECEMBER 2019
Carbon Nanotube-Based CMOS SRAM:
1 kbit 6T SRAM Arrays and 10T SRAM Cells
Pritpal S. Kanhaiya , Christian Lau, Gage Hills, Mindy D. Bishop, and Max M. Shulaker
Abstract — We experimentally demonstrate the first
static random-access memory (SRAM) arrays based on
carbon nanotube (CNT) field-effect transistors (CNFETs).
We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays
fabricated with complementary metal-oxide-semiconductor
(CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), with
all 1024 cells functioning correctly without any per-unit
customization. Moreover, we show the first demonstration
of CNFET CMOS 10T SRAM cells, capable of operating at
highly scaled voltages down to 300 mV. We characterize
the CNFET CMOS SRAM and demonstrate robust opera-
tion by writing and reading multiple patterns (to both the
kbit arrays as well as the 10T SRAM cells), measuring
SRAM variations in read, write, and hold margins and
repeat cycling of cells. Moreover, due to the low-temperature
back-end-of-line (BEOL)-compatible CNT-specific process-
ing, CNFET SRAM enables new opportunities for digital
systems, since: 1) CNFET SRAM can be fabricated directly
on top of computing logic to realize three-dimensional
integrated circuits; and 2) CNFET circuits can utilize metal
routing both above and below the CNFET device layer (e.g.,
as in our demonstration which utilizes buried power rails,
whereby the power rails are fabricated underneath the FETs
while metal routing is fabricated above the FETs), providing
opportunities for further SRAM density scaling.
Index Terms — Carbon nanotubes (CNTs), carbon
nanotube field-effect transistors (CNFETs), digital logic,
static random-access memory (SRAM).
I. I NTRODUCTION
C ARBON nanotube (CNT) field-effect transistors
(CNFETs) are a promising emerging nanotechnology
for next-generation energy-efficient digital very-large-scale-
integration (VLSI) circuits. Owing to their simultaneously
ideal electrostatic control (due to the ultrathin ∼1-nm
diameter of a CNT) and high carrier transport [1], [2], it is
projected that the CNFETs can improve the energy-delay
product (EDP, a metric of energy efficiency) by an order
of magnitude versus silicon complementary metal-oxide-
semiconductor (CMOS) [3]–[5]. In addition to these EDP
benefits, CNFET digital logic has been fabricated at a record
scaled 30 nm contacted gate-pitch (CGP, a key metric defining
Manuscript received August 26, 2019; accepted September 26,
2019. Date of publication November 13, 2019; date of current ver-
sion November 27, 2019. This work was supported in part by Analog
Devices, Inc., DARPA 3DSoC and in part by the Air Force Research
Laboratory. The review of this article was arranged by Editor K. Uchida.
(Corresponding author: Pritpal S. Kanhaiya.)
The authors are with the Massachusetts Institute of Technology,
Cambridge, MA 02139 USA (e-mail: pkanhaiy@mit.edu).
Digital Object Identifier 10.1109/TED.2019.2945533
0018-9383 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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5375
the area of a FET), demonstrating the potential to realize
a sub-3-nm node technology [6]. Furthermore, the CNFETs
are a rapidly maturing nanotechnology, as complete digital
systems [7]–[13], and complex analog and mixed-signal
circuits [14], [15] have been experimentally demonstrated.
Despite these increasingly complex CNFET demonstra-
tions, a critical component of digital systems—static random
access memory (SRAM) memory arrays—had never been
demonstrated. Prior work either has realized only individ-
ual, isolated CNT-based SRAM cells [16] or has relied on
processing that is not compatible with silicon CMOS (e.g.,
relying on air-reactive, ionic, non-solid-state CNT doping
processes [17]–[24]). Here, we highlight the first demonstra-
tion of the kbit 6T CNFET CMOS SRAM arrays. We demon-
strate all SRAM cells within the array functioning correctly
without relying on any customization, calibration, or correc-
tion of any sort. This is the largest reported CNFET CMOS cir-
cuit demonstrated to-date, containing 6144 CMOS CNFETs.
To further demonstrate the maturity of CNFET CMOS, we
also demonstrate the first 10T CNFET CMOS SRAM cells,
which can operate at highly-scaled supply voltages down to
300 mV. Importantly, all design and processing is 1) wafer-
scale (performed on 150-mm substrates), 2) VLSI-compatible
(no per-unit customization), and 3) silicon-CMOS-compatible
(leveraging only solid-state and silicon-compatible materials
and conventional fabrication process steps).
This work is an extension of [25]. In addition to summa-
rizing those results, we include additional 6T SRAM charac-
terization, as well as the first experimental demonstrations of
CNFET CMOS 10T SRAM cells.
II. CNFET CMOS SRAM FABRICATION
The CNFET CMOS fabrication process flow is illustrated
in Fig. 1. The starting substrate is a 150-mm silicon wafer
with ∼1 µm thermal SiO2 . Prior to any CNFET fabrication,
we fabricate a bottom metal layer of metal as buried power
rails. An inter-layer dielectric (ILD) is deposited followed
by defining metal vias down to the buried power rails. The
next metal layer is defined, which acts as both metal routing
(for the wordlines) as well as the bottom metal gates for the
CNFETs. To fabricate the CNFETs, a high-k gate dielectric
(HfO2 ) is deposited through atomic layer deposition (ALD) at
200 ◦ C, followed by CNT deposition. We deposit the CNTs
uniformly across the 150 mm substrate through a solution-
based deposition, whereby the wafer is submerged in a solvent
 5376
Fig. 1. Process flow for the CNFET CMOS SRAM. (a) M1, the first metal
layer, which consists of the VDD and VSS lines, is defined (5 nm Ti/45 nm
Pt) via physical vapor deposition (PVD). (b) Oxide spacer deposition
followed by etch and metal fill for inter-layer via (ILV) definition. (c) M2,
the second metal layer, is defined (5 nm Ti/70 nm Pt) for the wordlines
and back gates of the CNFETs. (d) High-k gate dielectric deposition
(30 nm HfO2 ) via ALD, and additional ILV definition. (e) CNTs solution-
deposited at room temperature uniformly across the wafer followed
by oxygen plasma to etch away CNTs outside the active area (e.g.,
channel). (f) M3, the third metal layer, consists of bit, bit_b and PMOS
source/drain definition (2 nm Ti/98 nm Pt) as well as NMOS source/drain
definition (100 nm Ti). (g) Passivation over the PMOS (100 nm SiO2 ).
(h) Electrostatic doping over the NMOS (20 nm HfO2 ).
containing dispersed CNTs (the CNTs are pre-purified within
this solution to achieve >99.99% semiconducting CNTs,
see [26], [27] for details). Following CNT deposition, the
active area (e.g., channel area) of the CNFETs is defined
through traditional photolithography and all CNTs outside
of the active regions are etched away using oxygen plasma.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019
The next metal layer (Pt) is defined, which acts as both the
CNFET source and drain contacts for the p-type CNFETs
and additional metal routing (bit/bit_b lines). The finished p-
type CNFETs are protected and passivated with 100 nm SiO2 .
To fabricate the n-type CNFETs, we deposit the next metal
layer (Ti) as the n-type CNFET source and drain contacts,
followed by ALD deposition of HfO2 (which electrostatically
dopes the CNTs to achieve the correct threshold voltage,
see [28] for details). The HfO2 electrostatic doping film is
etched off of the p-type CNFETs (which are protected by
the SiO2 passivation), leaving our final CNFET CMOS. The
full process contains three metal layers and uses only silicon-
CMOS compatible materials. Key aspects of this fabrication
process are:
1) The buried metal layers beneath the CNFET device layer
can be fabricated using conventional back-end-of-line
(BEOL) metallization processes.
2) Such buried metal layers are very challenging to real-
ize with conventional silicon CMOS due to high-
temperature processing required for fabricating silicon
CMOS (>1000 ◦ C for steps such as dopant activation
annealing [29]).
3) In contrast, the low-temperature (<400 ◦ C) CNFET
processing naturally enables such buried metal layers
and new three-dimensional circuit architectures. Specif-
ically, the room-temperature solution CNT deposition
decouples the high-temperature CNT synthesis (typically
>800 ◦ C) from the wafer fabrication, and the CNFET
CMOS doping process (leveraging both metal source
and drain work function engineering as well as high-
k electrostatic doping) never exceeds 250 ◦ C.
4) While our experimental demonstration of the CNFET
CMOS SRAM only leverages a single buried metal
layer (utilized as buried power rails), the same BEOL
metallization process can be repeated to realize multiple
buried metal layers (in addition to multiple conventional
BEOL metal layers above the device layer).
5) The entire fabrication process is wafer-scale, solid-state,
and BEOL compatible (<400 ◦ C). Thus, while we fabri-
cate our CNFET CMOS SRAM over silicon substrates,
the substrate could be silicon CMOS circuitry, additional
layers of CNFET CMOS circuitry, etc.
Fig. 2 shows the circuit schematic as well as a three-
dimensional schematic of a single 6T CNFET CMOS SRAM
cell. Fig. 3 shows the scanning electron microscopy (SEM)
images of a fabricated 1 kbit CNFET CMOS 6T SRAM array
as well as a single 6T SRAM. Figs. 2 and 3 highlight the
buried metal process whereby the power lines (VDD and VSS )
are routed directly beneath the CNFET CMOS SRAM array,
with the CNFETs and signal routing fabricated directly verti-
cally overlapping (on the same substrate without any die- or
wafer-bonding). Such three-dimensional circuit architectures
can provide additional future opportunities for further SRAM
density scaling and reduced routing congestion. The SRAM
density in this demonstration is limited due to the fact that
the CNFETs are fabricated at a relaxed ∼1-µm technology;
this is only due to the limitations of academic fabrication
facilities, as this same CNFET fabrication process has been
 KANHAIYA et al.: CNT-BASED CMOS SRAM: 1-KBIT 6T SRAM ARRAYS AND 10T SRAM CELLS 5377

Fig. 2. CNFET-based CMOS SRAM. (a) Schematic of 6T SRAM cell. (b)

CNT. (c) SEM image of D1 CNFET (fabricated at a ∼1-μm technology
node due to lithographic limitations in an academic fabrication facility,
with a ∼2-μm physical channel length). (d) 3-D illustration of the CNFET-
based SRAM cell in an array, including the VDD and VSS lines in the first
metal (M1) layer, wordline (WL) in the second metal (M2) layer, bit and
bit_b lines, p-type and n-type CNFET source/drain contacts in the third
metal (M3) layer, and the SiO2 passivation and HfO2 electrostatic doping
Fig. 4. Packaged kbit CNFET CMOS 6T SRAM array. Conventional
films for the p-type and n-type CNFETs, respectively. (e) Cross section
wirebonding is used to access pads on the die.
showing all three metal layers and their vertical integration.

Fig. 3. SEM images of (a) fabricated 1 kbit CNFET CMOS 6T SRAM

array, (b) subsection of the SRAM array (2 × 4 SRAM cell segment),
and (d) false colored SRAM cell from the full array based on (c) metal
layer sequence. Labeling of the false colored image is according to (e) 6T
SRAM cell schematic. The peripheral control and read-out circuitry is off-
chip; future work will focus on integrating the peripheral control circuitry
and read-out circuity on-chip on either the same CNFET CMOS circuit
layer or on a layer of silicon CMOS or CNFET CMOS circuitry fabricated
beneath the CNFET CMOS SRAM array.
Fig. 5. Array-level testing of the fabricated kbit CNFET CMOS 6T SRAM
arrays (VDD = 1.8 V). Various patterns [e.g., (a)–(c) letters spelling
out MIT, (d) checkerboard, and (e) inverted checkerboard] were written
to and subsequently read out from the array to demonstrate complete
functionality. Bit values of 1 and 0 are shown as yellow and blue pixels,
respectively. Supply voltage (VDD ) = 1.8 V.

CMOS circuit demonstrated to-date, containing 6144 CMOS

experimentally demonstrated to potentially scale to aggressive
technology nodes (CGP = 30 nm).
III. E XPERIMENTAL R ESULTS :
CNFET CMOS 6T SRAM
6T Array-level Testing (Figs. 4 and 5): To illustrate the
robust CNFET CMOS process, we fabricate the 1 kbit CNFET
CMOS 6T SRAM arrays; this is the largest reported CNFET
CNFETs. A packaged die micrograph of a fabricated CNFET
CMOS 1 kbit SRAM array is shown in Fig. 4. To test the
functionality of the fabricated SRAM arrays, we first write
the entire array and then read the entire array. All the bits are
initially written, and then all the bits are read, highlighting
the ability to nondestructively read from the SRAM array.
The measured results of various patterns (e.g., checkerboard,
inverted checkerboard, and the letters M, I, and T) are shown

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 5378 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 12, DECEMBER 2019

Fig. 7. False colored SEM image of the (a) fabricated 10T CNFET CMOS
SRAM cell and (b) 10T SRAM cell schematic.

shows typical p-type and n-type CNFET ID –VGS curves

highlighting the well-matched CMOS CNFETs with ION /IOFF
ratios of >1000. The measured distributions of the write,
read, and hold margins for a set of 6T SRAM cells are
shown in Fig. 6(g)–(i). These metrics are defined as followed
[Fig. 6 (c)–(e)].
Fig. 6. 6T Cell-level characterization. (a) False colored SEM image of
the CNFET CMOS 6T SRAM cells fabricated for cell characterization. 1) Write Margin [Fig. 6(e)]: Let the tripping point (VTP )
A sizing ratio of 2.25:1.5:1 (D1/D2:A1/A2:P1/P2) was used. (b) ID versus be where bit = Q_b = VTP with WL = VDD
VGS characteristics, in semilog and linear scale, of a typical PMOS [Fig. 6(e)] [29]. The write margin (WM), write margin
(purple) and NMOS (black) CNFET (channel length = 2 μm, channel
width = 40 μm, CNT density ∼20 CNTs/μm), with VDS = 1.8 V for high (WMH), and write margin low (WML) are defined
NMOS and VDS = 1.8 V for PMOS. (c) Read margin, (d) hold margin, and in (1)–(3) as
(e) write margin measurement from a typical CNFET CMOS 6T SRAM
cell. (f) 1000 overlaid write measurements. Statistical distributions of (g)
write margin (h) read margin, and (i) hold margin from 40 CNFET CMOS WML = VTP − VSS (1)
6T SRAM cells, as well as their respective mean and standard deviations WMH = VDD − VTP (2)
(write margin mean and standard deviation—μWRITE and σWRITE , read
margin mean and standard deviation—μREAD and σREAD , hold margin WM = min(VTP − VSS , VDD − VTP ). (3)
mean and standard deviation—μHOLD and σHOLD ).

2) Read Margin and Hold Margin [Fig. 6(c) and (d)]:

in Fig. 5. These patterns test every possible SRAM cell in The read and hold margins’ extractions are from the
the array at both values (both with the cell programed at relationship between Q_b and Q referred to as the
logical value “1” and at logical value “0”), illustrating correct voltage transfer curve (VTC): Q_b versus Q, with
functionality of every cell in the array simultaneously (we also bit = VDD , bit_b = VDD, and with WL = VDD (for
read the array multiple times to ensure the ability to perform read margin VTCs) and WL = VSS (for hold margin
(dr) (dr) (dr) (dr)
nondestructive repeated reads). VTCs) [30]–[31]. Let (VIL , VOH ) and (VIH , VOL ) be
(dr)
the points on the VTC where the slope of Q_b versus
6T Cell-level Characterization (Fig. 6): In addition to array-
(ld) (ld) (ld) (ld)
level testing to show functionality, we fabricate individual Q is −1, and let (VIL , VOH ) and (VIH , VOL ) be the
CNFET CMOS 6T SRAM cells to both characterize the vari- (ld)
points on the VTC (i.e., the mirrored VTC: Vin versus
ability and demonstrate the robustness of the cells. Fig. 6(a) VOUT) where the slope of Q_b versus Q is −1. For
shows an SEM of a single isolated 6T SRAM cells (labels their respective VTCs, the read/hold margin (RM/HM),
correspond with labels in Figs. 2 and 3), while Fig. 6(b) the read/hold margin high (RMH/HMH), and read/hold

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 KANHAIYA et al.: CNT-BASED CMOS SRAM: 1-KBIT 6T SRAM ARRAYS AND 10T SRAM CELLS 5379

Fig. 6(f) shows 1000 repeated write measurements of

the same 6T SRAM cell. The cells exhibit minimal drift
and hysteresis over continuous biasing and time (>12 h),
as the absolute maximum and minimum write margins differ
by <10 mV (performed with VDD = 1.8 V) across all
1000 repeated write cycles.

IV. E XPERIMENTAL R ESULTS :

CNFET CMOS 10T SRAM
Beyond the first 6T SRAM arrays, we experimentally
demonstrate the first 10T CNFET CMOS SRAM cells to
highlight the potential for CNFET CMOS circuits to operate
at scaled supply voltages [32]. Owing to the 10T SRAM cell
circuit architecture, we demonstrate their ability to operate
at highly scaled supply voltages down to 300 mV. This
is the most scaled operating voltage demonstrated for any
CNFET-based SRAM or CNFET-based sequential logic.
10T Cell-level Characterization: The circuit schematic and
SEM of a fabricated 10T SRAM cell is shown in Fig. 7. The
measured characteristics of the 10T SRAM cell are shown
in Fig. 8. Fig. 8(a) and (b) shows the typical write and read
margins for a 10T SRAM cell (measured at VDD = 1 V).
In Fig. 8(c) and (d), we show time-dependent waveforms of a
typical 10T cell. To demonstrate cell functionality, we exercise
every potential write and read combination: we first write a
“1” to the cell and read it multiple times (to demonstrate
nondestructive reads), followed by writing a “0” to the cell
and reading it multiple times. Fig. 8(c) shows the measured
waveform with VDD = 1 V, while Fig. 8(d) shows the
measured waveform for the same 10T SRAM cell with VDD =
300 mV (for comparison, the CNFET CMOS 6T SRAM cells
can operate with a minimal VDD of ∼1 V).

V. C ONCLUSION
This work realizes the first CNFET CMOS SRAM arrays
(1 kbit 6T SRAM) comprising 6144 CMOS CNFETs, as well
as the first 10T CNFET CMOS SRAM cells operating at
highly scaled supply voltages down to 300 mV. We also
demonstrate buried power rails for further SRAM density
scaling opportunities. Taken together, this work is a major step
Fig. 8. 10T cell-level characterization. (a) Write margin (∼0.35 V) and toward demonstrating the feasibility of a future CNT-based
(b) read margin (∼0.23 V) from a typical CNFET CMOS 10T SRAM technology, realizing a critical component of future energy-
cell (VDD = 1 V). Time-dependent waveforms at (c) 1 V VDD and (d) efficient CNT digital systems.
300 mV VDD . There is still positive read and write margins at VDD = 300
mV, a requirement for digital logic (∼0.13 and ∼0.02 V, respectively).
Below 300 mV, noise margin violations result in incorrect operation. Clock ACKNOWLEDGEMENT
frequency is limited by the off-chip data acquisition setup that records
the output waveform. The measurements in (c) and (d) show first writing This article is an extension of the VLSI 2019 conference
a “1” followed by four nondestructive reads, followed by writing a “0”
followed by four nondestructive reads. The noise in the waveform is
article: P. S. Kanhaiya et al., “1 kbit 6T SRAM Arrays in
from measuring the cell while the bit lines are floating, illustrating that Carbon Nanotube FET CMOS,” IEEE VLSI 2019.
the access transistors [CNFET “A1” and “A2” in Fig. 7(b)] provide ideal
electrical isolation of the cell from the bitline.
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