SHREESHA R HEGDE 1BM13EC104

SUNAIN ASHOK PALEKAR 1BM13EC113

SHREEVATSA BHAT 1BM13EC105
YASHASWI D 1BM13EC128

UNDER THE GUIDANCE OF

K VIJAYA
ASSOCIATE PROFESSOR

PROJECT WORK-2
2016-17
ELECTRONICS AND COMMUICATIONS
Introduction:

Today the world needs very high speed information. It may be in

terms of processing or with sending the data.
Both need high speed processors as well as memory.
High speed memory means more will be the power dissipation.
So the technology that is coming up is with the introduction of
new materials for the production of chips.
One such is Carbon nano-tube field effect transistors.
The Moore's law which says that the number of transistors will
double every 18 months will soon get outdated.
 PROBLEM DEFINITION
SILICON IS THE PRESENT MATERIAL THAT WE ARE USING FOR THE PRODUCTION OF CHIPS.
THE DISADVANTAGE WITH THE SILICON IS WITH THE PURITY. IT REQUIRES ABOUT
99.9999999%(7TH DEGREE) PURE SILICON FOR THE PRODUCTION.
THE IMMUNITY AGAINST THE NOISE IS VERY POOR.
THE TEMPERATURE DEPENDENCY OF THE VARIOUS CHARACTERISTICS SUCH AS SUBTHRESHOLD
CONDUCTION, THRESHOLD VOLTAGES ETC. IS VERY HIGH.
THE SECONDARY EFFECTS TRY TO DOMINATE FOR THE LOWER CHANNEL LENGTHS.
THE RADIUS OF THE SILICON ATOM IS 700PM(CRYSTAL) WHICH PERMITS THE SCALING DOWN
OF THE TRANSISTORS ONLY TILL 3NM.
 THE BATTERY TECHNOLOGY HARDLY DOUBLES EVERY 10S OF YEARS. THIS PERMITS FOR LOW
POWER APPLICATIONS IN BATTERY OPERATED DEVICES
ANOTHER ISSUE IS WITH THE ENVIRONMENTAL CONCERN WHICH INTENDS US TO REDUCE
POWER FOR THE REDUCTION OF GLOBAL WARMING.
 PROPOSED SOLUTION

THE SOLUTION MAY BE REPLACING THE SILICON WITH CARBON NANO-TUBE.

THE GRAPHENE WHICH IS ROLLED UP TO FORM TUBE LIKE STRUCTURE IS USED AS A CHANNEL.
THE 7TH DEGREE PURE CARBON CAN BE AVAILED WITHOUT MUCH DIFFICULTY.
THE ATOMIC RADIUS OF THE CARBON ATOM IS AROUND 130PM WHICH PERMITS THE
SCALING DOWN LESS THAN 3NM.
 CARBON NANO TUBE FIELD EFFECT TRANSISTORS

CARBON NANO TUBE FIELD EFFECT TRANSISTORS ARE NEW TECHNOLOGY TRENDS IN THE VLSI
INDUSTRIES.
THE FIRST APPROACH WAS DONE BY THE STANFORD UNIVERSITY NANO-SCIENCES LAB IN THE
YEAR 2011.
CARBON NANOTUBE FIELD EFFECT TRANSISTORS ARE USUALLY MADE BY WRAPPING THE
GRAPHENE INTO TUBE-LIKE STRUCTURE.
THERE ARE 4 TYPES OF CNTFET
Suspended CNTFET Back-gated CNTFET
Top-gated CNTFET with fabrication

Gate all-around CNTFET

 THE GATE ALL-AROUND CNTFET CAN BE FABRICATED WITHOUT SILICON FOR LOW-VOLTAGE
APPLICATIONS SUCH AS SRAM CELLS AND DIGITAL LOGIC CIRCUITS.
THE OTHER THREE CAN BE FABRICATED WITH SILICON BEING USED SO THAT IT CAN BE USE FOR
HIGH VOLTAGE APPLICATIONS SUCH AS ESD PAD DESIGNS, HIGH SWING DIFFERENTIAL
AMPLIFIERS AND THE INTERFACING PINS FOR THE MICROPROCESSORS ETC.
 CHIRALITY

CHIRALITY IS THE FORCE VECTOR THAT OCCUR DUE TO MISMATCH IN THE CARBON ATOMS
THAT OCCUR DUE TO ROLLING OF THE GRAPHENE INTO TUBE LIKE STRUCTURE.
H=N1+M2 WHERE N AND M ARE INTEGERS AND 1
AND 2 ARE THE UNIT VECTORS OF THE HEXAGONAL
HONEYCOMB LATTICE.
 CHARACTERISTICS

3 2 ++2
= IS THE EQUATION OF THE DIAMETER OF THE TUBE IN TERMS OF THE

CHIRAL NUMBERS M, N.
3
= TAN 1 IS THE EQUATION FOR THE CHIRAL ANGLE
2+

THE STANDARD EQUATION FOR THE MOSFET IS APPLICABLE HERE WITH THE CHANGES THAT
THE CHANNEL WIDTH BEING REPLACED BY DIAMETER OF THE TUBE AND THE WIDTH IS
AVAILABLE ONLY IN THE FORM
I-V CHARACTERISTICS
 KEY ADVANTAGES OF CNTFET OVER CMOS

BETTER CONTROL OVER CHANNEL FORMATION

BETTER THRESHOLD VOLTAGES
BETTER SUB-THRESHOLD SLOP
HIGH ELECTRON MOBILITY
HIGH CURRENT DENSITY
HIGH TRANSCONDUCTANCE
 SIMULATION

THE PROCESS OF MEASURING THE VARIOUS OUTPUTS OF THE CIRCUITS VIRTUALLY BASED ON THE
PREDICTIVE TECHNOLOGY MODEL(LIBRARY) IS CALLED SIMULATION.
VARIOUS SIMULATORS ARE AVAILABLE FOR BOTH THE ANALOG AND DIGITAL CIRCUITS. VIRTUOSO
BY CADENCE INC. AND THE HSPICE BY SYNOPSYS INC. ARE THE WELL KNOWN SIMULATORS.
THE DEVICE IS MODELLED AS THE COMBINATION OF R,L AND C NETWORKS AND THE STIMULUS IS
APPLIED AS PER THE DESIGN.
THE SIMULATOR USED HERE IS HSPICE Z-2007. THE TECHNOLOGY RAW LIBRARY FILE IS PROVIDED
BY STANFORD UNIVERSITY NANO-SCIENCES LAB.
 SRAM CELL

BASIC OF ALL THE MEMORY CIRCUITS. MAINLY USED FOR HIGH SPEED CACHE MEMORY.
USED TO HOLD ONE BIT OF DATA VIZ., EITHER 0-STATE OR 1-STATE.
ARRAY CAN BE MADE SO AS TO HOLD HIGHER NUMBER OF BITS TO FORM A WORD.
THIS CAN BE ACHIEVED BY ARRAY DECODER.
THIS FORMS THE BASIC STRUCTURE OF RAM.
THE BIT STORED IN IT IS VANISHED AS SOON AS THE POWER SUPPLY IS TAKEN BACK.
BASIC STRUCTURE OF SRAM- THE 6T MODEL

Pass transistors
 PASS TRANSISTOR DESIGN LOGIC

FACTORS TO BE CONSIDERED IN DESIGNING OF THE PASS TRANSISTOR ARE THE KOX, CSUB,
AND THE NUMBER OF TUBES.
THIS IS DEPENDENT UPON THE INVERTER SIZING AND THE VOLTAGE SWING REQUIRED AT THE
OUTPUT OF THE INVERTER.
THE TRANSISTORS SHOULD BE OPERATING IN THE PROPER REGION SO AS TO ACCOMPLISH
THE REQUIRED OPERATION
KOX IS TAKEN TO BE 16. IT WAS TESTED FOR KOX FROM 10 TO 80. BUT IT WAS FOUND TO BE
IDEAL AT 16 AND IT IS THE PERMITTIVITY OF AMORPHOUS CARBON.
 POWER

POWER IS DEFINED AS THE PRODUCT OF THE VOLTAGE ACROSS THE TRANSISTOR AND THE
CURRENT FLOWING THROUGH IT.
AVERAGE POWER IS THE RATIO OF SUM OF ALL THE POWERS AT EACH INSTANT TO THE TIME
TILL WHICH SIMULATION IS RUN.
AVERAGE POWER REFLECTS THE ACTUAL POWER CHARACTERISTICS SINCE THERE WILL BE
SPIKES DURING THE TRANSITION PERIOD.
 SNM

SNM ACTUALLY GIVES THE ROBUSTNESS OF THE SRAM CELL.

IT IS DEFINED AS THE MINIMUM LENGTH OF THE RECTANGLE THAT CAN BE FORMED INSIDE THE
BUTTERFLY CURVE OF THE SRAM CELL.
SNM DIFFERS FOR ALL THE THREE OPERATIONS OF THE SRAM VIZ., READ, WRITE AND THE HOLD
STATE.
 VARIOUS SRAM CONFIGURATION

6T model 7T model
8T model 10T model
 10T MODEL SPECIALTIES

THE SIMPLE CIRCUIT IS EASY TO UNDERSTAND AND THE DESIGN IS SIMPLE.

THE USE OF TRANSMISSION GATE ACTS LIKE A SIMPLE LEVEL SHIFTER FOR THE PROPER LEVEL
DEFINITION VIZ., 1-STATE = 0.9V AND 0-STATE = 0V
IT PERMITS THE SIMULTANEOUS READ AND WRITE OPERATION.
 SNM FOR READ WRITE AND HOLD

Hold SNM Read SNM

Write SNM
PROJECT TIMELINE
 RESULTS
Nominal operating voltage= 0.9V CNTFET Nominal operating voltage =0.9V

model Read SNM Write SNM Power Dissipated Model Read SNM Write SNM Power
Dissipated

6T 0.15 0.21 7.239uW

6T 0.3 0.27 5.34nW
7T 0.18 0.22 5.542uW
8T 0.22 0.25 3.49uW 7T 0.32 0.29 4.8nW

10T 0.15 0.21 11.3649uW 8T 0.33 0.29 3.6nW

10T 0.3 .27 6.8nW

 CONCLUSIONS

IN THIS PROJECT WE ANALYSED AND COMPARED THE SNM AND POWER DISSIPATION OF
DIFFERENT SRAM CELL TOPOLOGIES FOR BOTH CNTFET AND MOSFET. SNM AND POWER
DISSIPATION OF DIFFERENT CHIRALITY OF SRAM CELLS ARE TESTED.
BRIEF COMPARISON OF MOSFET AND CNTFET IS DONE. WE CAN SEE THAT IN
NANO SCALE REGIME CNTFET DEVICES MORE ADVANTAGEOUS THAN CMOS.
 ACADEMIC ACHIEVEMENTS

A RESEARCH PAPER TITLED STATIC NOISE MARGIN ANALYSIS OF LOW POWER CNTFET BASED
SRAM CELLS HAS BEEN ACCEPTED FOR PUBLICATION IN THE NATIONAL LEVEL TECHNICAL
PAPER PRESENTATION - PRASTUTI
 REFERENCES

HTTP://IEEEXPLORE.IEEE.ORG/DOCUMENT/1052809/?RELOAD=TRUE
HTTP://WWW.IRJET.NET/ARCHIVES/V2/I4/IRJET-V2I403
HTTPS://EN.WIKIPEDIA.ORG/WIKI/SIGNAL TO NOISE MARGIN OF SRAM
HTTP://WWW.SEAS.UPENN.EDU/~EECAD/CADENCE/HSPICE.HTML
HTTPS://WWW.SYNOPSYS.COM/VERIFICATION/PROTOTYPING/SABER/COSMOS-
SCOPE.HTML
HTTP://TECHNAV.IEEE.ORG/TAG/3735/CARBON-NANOTUBES
THANK YOU