CMOS Fundamentals

CMOS Fundamentals
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Q1. Why low power has become an important issue in the present day VLSI circuit
realization?
Answer:
In deep submicron technology the power has bec : In deep submicron technology the
power has become as one of the most important issue because of: Increasing transistor
count; the number of transistors is getting doubled in every 18 months based on getting
doubled in every 18 months based on Moore,s Moore,s Law Higher speed of operation;
the power dissipation is proportional to the clock frequency Greater device leakage
currents; In nanometer technology the leakage component becomes a significant
percentage of the total power and the leakage current increases at a faster rate than
dynamic power in technology generations
Q2. How reliability of a VLSI circuit is related to its power dissipation dissipation?
Answer:
It has been observed that : It has been observed that every 10ºC rise in temperature ºC
rise in temperature roughly doubles the failure roughly doubles the failure rate because
various fa rate because various failure mechanism lure mechanism such as silicon
interconnect fatigue, such as silicon interconnect fatigue, electromigrat electromigration
diffusion, ion diffusion, junction diffusion and thermal runaway starts occurring as
temperature increases.
Q3. How environment is affected by the power dissipation of VLSI circuits circuits?
Answer:
According to an estimate of the U.S. Environmental Protection Agency (EPA), 80% of the
power consumption by office equipment are due to computing equipment and a large part
from unused part from unused equipment. Moreover, the power equipment. Moreover, the
power is dissipated is dissipated mostly in the form of heat. The cooling techniques, such
as AC transfers the heat to the environment.
Q4. Why leakage power dissipation has become an important issue in deep submicron
technology in deep submicron technology?
Answer:
In deep submicron technology deep submicron technology the leakage component the
leakage component becomes a significant percentage of the total power and the leakage
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current increases at a faster rate than dynamic power amic power in new technology
technology generations. That is why the leakage pow generations. That is why the
leakage power has become an important issue.
Q5. Distinguish between energy and power dissipation of VLSI circuits. Which one is
more important for portable systems systems?
Answer:
Power (P) is the power dissipation in Watts at : Power (P) is the power dissipation in
Watts at different fferent instances of time. On the other has energy (E) refers to the
energy consumed in Joule over a period of time (E = P*t).
Q6. What are the commonly used conducting layers used in IC fabrication?
Answer:
Fabrication involves fabrication of Fabrication involves fabrication of patterned laye
atterned layers of the rs of the three conducting materials: metal, poly-silicon silicon and
diffusion by using a series of photolithographic techniques and chemical processes
involving oxidation of silicon, diffusion of impurities into the silicon and deposition and
etching of aluminum or polysilicon polysilicon on the silicon to provide interconnectio on
the silicon to provide interconnection.
Q7. Show the basic structure of a MOS transistor.
Answer:
The basic structure of a MOS transistor is given below. On a lightly doped substrate of
silicon two islands of diffusion regions called as source and drain, of opposite polarity of
that of the substrate, are created. Between these two regions, a thin insulating layer of
silicon dioxide is formed and on top of this a conducting material made of poly-silicon or
metal called gate is deposited.
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Q8. What is the latch up problem that arises in bulk CMOS technology?
Answer:
The latch : The latch-up is an inherent problem in both n up is an inherent problem in both
n-well as well a well as well as pwell based CMOS circuits. The phenomenon is caused
by the parasitic bipolar transistors formed in the bulk of silicon as shown in the figure for
the n in the figure for the n-well process. well process. Latch-up can be defined as the
formation of a low-impedance path between the power supply and formation of a low-
impedance path between the power supply and ground rails through the parasitic ground
rails through the parasitic npn and pnp bipolar transistors. bipolar transistors. As shown
the BJTs are cross As shown the BJTs are cross-coupled to form the st coupled to form
the structure of a ructure of a silicon silicon-controlled controlled-rectifier (SCR) providing
a short rectifier (SCR) providing a short-circuit path circuit path between the power rail
and ground. Leakage current through the parasitic resistors can cause one transistor to
turn on, which in turn turns on the other transistor due to positive feedback and leading to
heavy current flow and consequent device failure.
Q9. How the latch up problem can be overcome?
Answer:
There are several approaches to reduce the ten : There are several approaches to
reduce the tendency of Latch of Latch-up. Some of the important techniques are up.
Some of the important techniques are mentioned below:
Use guard ring around p Use guard ring around p- and/or n and/or n-well with frequent
well with frequent contacts to the rings
To reduce the gain product B1XB2
Moving the n Moving the n-well and the n+ source/drain further well and the n+
source/drain further apart
Buried n+ layer in well to reduce gain of Q1
Higher substrate doping level to reduce R Higher substrate doping level to reduce R-
sub
Reduce R Reduce R-well by making low resistance contact to well by making low
resistance contact to GND
Q10. Distinguish between the bulk CMOS technology with the SoI technology
fabrications. technology fabrications.
Answer:
In bulk CMOS technology, a lightly doped p : In bulk CMOS technology, a lightly doped p-
type or n-type substrate is used to fabricate MOS transis type substrate is used to
fabricate MOS transistors. On the other hand, an insulator can be used as a substrate to
fabricate MOS transistors
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Q11. What are the benefits of SOI technology relative to conventional bulk CMOS
technology?
Answer:
Benefits of SOI technology relative to convent : Benefits of SOI technology relative to
conventional silicon al silicon (bulk CMOS):
Lowers parasitic capacitance due to isolation from the bulk silicon, which improves
power consumption and thus high speed performance.
Reduced short channel effects
Better sub Better sub-threshold slope. threshold slope.
No Latch up due to BOX (buried oxide).
Lower Threshold voltage.
Reduction in junction depth leads to low leakage current.
Higher Device density.
Q12. What are the basic assumptions of the fluid model?
Answer:
There are two basic assumptions as follows: : There are two basic assumptions as
follows: (a) Electrical charge is considered as fluid, which can move from one place to
another depending on the difference in their level, of one from the other, just like a fluid.
(b) Electrical potentials can be mapped into the geometry of a container, in which the fluid
can move around.
Q13. Explain the function of a MOS transistor in the Explain the function of a MOS
transistor in the nonsaturation saturation mode using the fluid model mode using the fluid
model.
Answer:
Gate voltage higher than the threshold voltage : Gate voltage higher than the threshold
voltage and the drain d the drain voltage is slightly higher than source voltage. In such a
situation, as the drain voltage is increased the slope of the fluid flowing out increases
indicating linear increase in the flow of current.
Q14. Explain the three modes of operation of a MOS transistors ransistors.
Answer:
The three modes are:
(a) Accumulation mode when Accumulation mode when Vgs is much less than is much
less than Vt.
(b) Depletion Depletion mode when mode when Vgs is equal to is equal to Vt.
(c) Inversion Inversion mode when mode when Vgs is greater than is greater than Vt.
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Q15. What are the three regions of operation of a MOS transistor?
Answer:
The three regions are:
Cut-off region: This is essentially the accumulation mode, where there is no effective
flow of current between the source and drain.
Non-saturated region: This is the active, active, linear or week inversion region,
where the drain current is dependent on both the gate and drain voltages.
Saturated region: This is the strong inversion region, where the drain current is
independent of the drain drain current is independent of the drain-to-source voltage but
urce voltage but depends on the gate voltage.
Q16. What is the threshold voltage of a MOS transistor? How it varies with the body bias?
Answer:
One of the parameters that characterizes the switching behavior of a MOS transistor is its
threshold voltage Vt. This can be defined as the gate voltage at which a MOS transistor
begins to conduct.
Q17. What is channel length modulation effect? How the voltage current characteristics
are affected because of this effect?
Answer:
It is assumed that channel length remains constant as the drain voltage is increased
appreciably beyond the on set of saturation. As a consequence, the drain current remains
constant in the saturation region. In practice, however the channel length shortens as the
drain voltage is inccreased. For long channel lengths, say more than 5µm, this variation
of length is relatively very small compared to the total length and is of little consequence.
However, as the device sizes are scaled down, the variation of length becomes more and
more predominant and should be taken into consideration. As a consequence, the drain
current increases with the increase in drain voltage even in the saturation region.
Q18. What is body effect? How does it influences the threshold voltage of a MOS
transistor?
Answer:
All MOS transistors are usually fabricated on a common substrate and substrate (body)
voltage of all devices is normally constant. However, as we shall see in subsequent
chapters, when circuits are realized using a number of MOS devices, several devices are
connected in series. This results in different source potentials for different devices. It may
be noted that the threshold voltage Vt is not constant with respect to the voltage
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difference between the substrate and the source of the MOS transistor. This is known as
the substrate-bias effect or body effect. Increasing the Vsb causes the channel to be
depleted of charge carries and this leads to increase in the threshold voltage.
Q19. What is transconductance of a MOS transistor? Explain its role in the operation of
the transistor.
Answer:
Trans-conductance is represented by the change in drain current for change in gate
voltage for constant value of drain voltage. This parameter is somewhat similar to β, the
current gain of bipolar junction transistors. The following equation shows the dependence
of on various parameters. As MOS transistors are voltage controlled devices, this
parameter plays an important role in identifying the efficiency of the MOS transistor.
Q20. How one nMOS and one pMOS transistor are combined to behave like an ideal
switch.
Answer:
To overcome the limitation of either of the transistors, one pMOS and one nMOS
transistor can be connected in parallel with complementary inputs at their gates. In this
case we can get both LOW and HIGH levels of good quality at the output. The low level
passes through the nMOS switch and HIGH level passes through the pMOS switch
without any degradation as shown in the figure
Q21. The input of a lightly loaded transmission gate is slowly changes from HIGH level to
LOW level. How the currents through the two transistors vary?
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Answer:
Another situation is the operation of the transmission gate when the output is lightly
loaded (smaller load capacitance). In this case, the output closely follows the input. In this
case the transistors operate in three regions depending on the input voltage as follows:
Region I: nMOS non-saturated, pMOS cut-OFF.

Region II: nMOS non-saturated, pMOS non-saturated.
Region III: nMOS cut off, pMOS non-saturated.
Q22. How its ON-resistance of a transmission gate changes as the input varies from 0 V
to Vdd, when the output has a light capacitive load.
Answer:
The variation of ON resistance is shown in the figure. The parallel resistance remains
more or less constant.
Q23. Draw the ideal characteristics of a CMOS inverter and compare it with the actual
characteristics.
Answer:
The ideal and actual characteristics are given below. In the ideal characteristics, the
output voltage is Vdd for input voltage from o to Vdd/ and 0 for input voltage from Vdd/ to
Vdd. This is not true in case of the actual characteristics as shown below.
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Q24. Compare the characteristics of the different types of MOS inverters in terms of noise
margin and power dissipation.
Answer:
Various characteristic parameters are compared in the following table:
Q25. What is the inversion voltage of an inverter? Find out the inversion voltage of a
CMOS inverter.
Answer:
The inversion voltage Vinv is defined as the voltage at which the output voltage Vo is
equal to the input voltage Vin. For a CMOS inverter it can be expressed in terms of the
threshold voltages of the MOS transistors and other parameters.
Q26. How the noise margin is affected by voltage scaling?
Answer:
As the supply voltage is reduced, the margin also decreases as shown in the figure.
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Q27. What is the lower limit of supply voltage of a CMOS inverter. What happens if the
supply voltage is further reduced?
Answer:
The lower limit of the supply voltage depends on the sum of the threshold voltages of the
nMOS and the pMOS transistors. Vdd = Vtn +|Vtp|. As the supply voltage is reduced
further, it leads to hysteresis in the transfer characteristic.
Q28. What is sheet resistance? Find out the expression of the resistance of rectangular
sheet in terms of sheet resistance.
Answer:
The sheet resistance is defined as the resistance per unit area of a sheet of material.
Consider a rectangular sheet of material with Resistivity = , Width = W, Thickness = t
and Length = L. Then, the resistance between the two ends is
Q.29 Find out the capacitance of a MOS capacitor.
Answer:
The capacitance of a parallel plate capacitor is given by
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Q30. Explain the basic concept of super buffer.
Answer:
There are situations when a large load capacitance such as, long buffers, off-chip
capacitive load, or I/O buffer are to be driven by a gate. In such cases, the delay can be
very high if driven by a standard gate. Limitations of driving by a simple nMOS inverter is
the asymmetric drive capability of pull-up and pull-down devices (ratioed logic). Moreover,
when the pull-down transistor is ON, the pull-up transistor also remains ON. So, the pull-
down transistor should also sink the current of the pull-up device. Although this limitation
is overcome in CMOS circuits, there is asymmetry in drive capability of pull-up and pull-
down devices having the same minimum size
Q.31 Draw the schematic diagram of an inverting and non-inverting super-buffers and
explain its operation.
Answer:
The schematic diagrams of the super buffers are given below.
The average of the saturation currents for Vds = 5V and linear current for Vds = .5V is
approximately 4.4 βpu for the standard inverter. On the other hand the, for the super-
buffer, the average current is 19.06 βpu, which is 4 times that of standard inverter. Thus,
the pull-up device is capable of sourcing about four times the current of the standard
nMOS inverter.
Q32. Give the schematic diagram of a Bi-CMOS inverter. Explain its operation. Compare
the switching characteristics of a BiCMOS inverter with respect to that for static CMOS for
different fan out conditions.
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Answer:
The schematic diagram of a BiCMOS inverter is given below. Higher current drive
capability of bipolar NPN transistors is used in realizing bi-CMOS inverters. The delays of
CMOS and BiCMOS inverters are compared for different fan-outs. It may be noted that for
fan-out of 1 or CMOS provides smaller delay compared to BiCMOS. However, as fan-out
increases further, BiCMOS performs better and better.
Q33. How the transfer characteristic of a CMOS NAND gate is affected with increase in
fan-in?
Answer:
Transfer characteristic does not remain symmetric with increase in fan-in of the NAND
gate. The inversion voltage moves towards right with the increase in fan-in.
Q34. How the transfer characteristic of a CMOS NOR gate is affected with increase in
fan-in?
Answer:
In case of NOR gate the transfer characteristic also does not remain symmetric and the
inversion voltage moves towards left with the increase in fan-in.
Q35 How switching characteristic of a CMOS NAND gate is affected with increase in fan-
in?
Answer:
When the load capacitance is relatively large, the fall time increases linearly with the
increase in fan-in and the rise time is not affected much.
Q36. How switching characteristic of a CMOS NOR gate is affected with increase in fan-
in?
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Answer:
When the load capacitance is relatively large, the rise time increases linearly with the
increase in fan-in and the fall time is not affected much. For the same area, NAND gates
are superior to NOR gates in switching characteristics because of higher mobility of
electrons compared holes. For the same delay, NAND gates require smaller area than
NOR gates
Q37. How noise margin of a CMOS NAND/NOR gate is affected with increase in fan-in?
Answer:
Because of the change in the inversion voltage, the noise margin is affected with the
increase in fan-in. For equal fan-in, noise margin is better for NAND gates compared to
NOR gates. We may conclude that for equal area design NAND gates are faster and
better alternative to NOR gates
Q38. For a complex/compound CMOS logic gate, how do you realize the pull-up and the
pull-down networks?
Answer:
A CMOS logic gate consists of a nMOS pull-down network and a pMOS pull-up network.
The nMOS network is connected between the output and the ground, whereas the pull-up
network is connected between the output and the power supply. The nMOS network
corresponds to the complement of the function either in sum-of-product or product-of-sum
forms and the pMOS network is dual of the nMOS network .
Q.39 Give the two possible topologies AND-OR-INVERT AND-OR- INVERT (AOI) and
OR-AND-INVERT (OAI) to realize CMOS logic gate. Explain with an example.
Answer:
The AND-OR-INVERT network corresponds to the realization of the nMOS network in
sum-of-product form. Where as the OR- AND-INVERT network corresponds to the
realization of the nMOS network in product-of-sum form. In both the cases, the pMOS
network is dual of the nMOS network .
Q40. Give the AOI and OAI realizations for the sum and carry functions of a full adder.
Answer:
AOI form of realization is shown in the figure.
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Q41. How do you realize pseudo nMOS logic circuits. Compare its advantage and
disadvantages with respect to standard static CMOS circuits.
Answer:
In the pseudo-nMOS realization, the pMOS network of the static CMOS realization is
replaced by a single pMOS transistor with its gate connected to GND. An n-input pseudo
nMOS requires n+1 transistors compared to n transistors of the corresponding static
CMOS gates. This leads to substantial reduction in area and delay in pseudo nMOS
realization. As the pMOS transistor is always ON, it leads to static power dissipation when
the output is LOW.
Q42. In what way relay logic circuits differ from pass transistor logic circuits? Why the
output of a pass transistor circuit is not used as a control signal for the next stage?
Answer:
Logic functions can be realized using pass transistors in a manner similar to relay contact
networks. However, there are some basic differences as mentioned below:
(a)In relay logic, output is considered to be ‘1’ when there is some voltage passing
through the relay logic. Absence of voltage is considered to be ‘0’. On the other hand, is
case of pass transistor logic it is essential to provide both charging and discharging path
for the output load capacitance.
(b)There is no voltage drop in the relay logic, but there is some voltage drop across the
pass transistor network.
(c)Pass transistor logic is faster than relay logic.
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Q43. What are the advantages and limitations of pass transistor logic circuits? How the
limitations are overcome?
Answer:
Pass transistor realization is ratioless, i.e. there is no need to have L:W ration in the
realization. All the transistors can be of minimum dimension. Lower area due to smaller
number of transistors in pass transistor realization compared to static CMOS realization.
Pass transistor realization also has lesser power dissipation because there is no static
power and short-circuit power dissipation in pass transistor circuits. The limitations are (a)
Higher delay in long chain of pass transistors (b) Multi-threshold Voltage drop (Vout = Vdd
– Vtn) (c) Complementary control signals and (d) Possibility of sneak path because of the
presence of path to Vdd and GND.
Q44. Why is it necessary to insert a buffer after not more than four pass transistors in
cascade?
Answer:
When a signal is steered through several stages of pass transistors, the delay can be
considerable. For n stages of pass transistors, the delay is given by the relationship.
To overcome the problem of long delay, buffers should be inserted after every three or
four pass transistor stages.
Q45. Why is it necessary to have swing restoration logic in pass transistor logic circuits?
Explain its operation.
Answer:
In order to avoid the voltage drop at the output (Vout = Vdd – Vtn) , it is necessary to use
additional hardware known swing restoration logic at the gate output. At the output of the
swing restoration logic there is rail to rail voltage swing. The swing restoration can be
done using a pMOS transistor with its gate connected to GND.
Q46. What is the ‘sneak path’ problem of pass transistor logic circuits? How sneak path is
avoided in Universal Logic Module (ULM) based realization of pass transistor network.
Illustrate with an example.
Answer:
As shown in the figure, the output is connected to both ‘1’ (Vdd) and ‘0’(GND). The output
attains some intermediate Value between Vdd and GND. The MUX based realization
allows connection of the output to only one input, which can be either 0 or 1.
Multiplexer realization of Is shown in the figure.
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Q47. Explain the basic operation of a 2-phase dynam phase dynamic circuit? ic circuit?
Answer:
The operation of the circuit can be explained : The operation of the circuit can be
explained using precharge precharge logic in which the output is logic in which the output
is precharged precharged to HIGH level during to HIGH level during φ2 clock and the
clock and the output is evaluated during output is evaluated during φ1 clock 1 clock.
Q48. How phase clocks can be generated using inverters?
Answer:
As shown below, two phase clock can generated using inverters. The timing diagram is
given in the next slide.
Timing diagram of the two-phase clock generated from a single-phase clock.
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Q49. What makes dynamic CMOS circuits faster than static CMOS circuits?
Answer:
As MOS dynamic circuits require lesser number of transistors and lesser capacitance is
to be driven by it. This makes MOS dynamic circuits faster.
Q50. Compare the sources of power dissipation between static CMOS and dynamic
CMOS circuits?
Answer:
In both the cases there is switching power and leakage power dissipations. However, the
short circuit and glitching power dissipations, which are present in static CMOS circuits,
are not present in dynamic CMOS circuits.
Q51. What is charge leakage problem of dynamic CMOS circuits? How is it overcome?
Answer:
The source-drain diffusions form parasitic diodes with the substrate. There is reverse bias
leakage current .The current is in the range 0.1nA to 0.5nA per device at room
temperature and the current doubles for every 10°C increase in temperature . This leads
to slow but steady discharge of the charge on the capacitor, which represent information.
This needs to be compensated by refreshing the charge at regular interval.
Q52. Explain the clock skew problem of dynamic CMOS circuits?
Answer:
Clock skew problem arises because of delay due to resistance and parasitic capacitances
associated with the wire that carry the clock pulse and this delay is approximately
proportional to the square of the length of the wire. When the clock signal reaches a later
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stage before its preceding stage, the precharge phase of the preceding stage overlaps
with the evaluation phase of the later stage, which may lead to premature discharge of
the load capacitor and incorrect output during evaluation phase
Q53. How clock skew problem is overcome in in domino CMOS circuits?
Answer:
In domino CMOS circuits the problem is overcome by adding an inverter as shown in the
diagram. It consists of two distinct components: The first component is a conventional
dynamic CMOS gate and the second component is a static inverting CMOS buffer. During
precharge phase, the output of the dynamic gate is high, but the output of the inverter is
LOW.As a consequence, it cannot drive an nMOS transistor ON. So, the clock skew
problem is overcome.
Q54. How clock skew problem is overcome in in NORA CMOS circuits?
Answer:
The problem can be overcome using NORA logic, nMOS and pMOS transistor networks
are alternatively used. The output of an nMOS block is HIGH during precharge, which
cannot turn a pMOS transistor ON. Similarly, the output of an pMOS block is LOW during
precharge, which cannot turn a nMOS transistor ON.
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Q55. Distinguish between Mealy and Moore machines.
Answer:
In a Mealy machine the outputs are dependent on the inputs and present state. The
Output transition function is represented by Z = λ(S,X).
Where as in a Moore machine the outputs are dependent only on present state. The
output transition function is represented by Z = λ((S)
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Q56. List various sources of leakage currents.
Answer:
Various sources of leakage currents are listed : Various sources of leakage currents are
listed below:
I1= Reverse = Reverse-bias p-n junction diode leakage current n junction diode
leakage current
I2 = Band-to-band tunneling current band tunneling current
I = Subthreshold leakage current
I3 = Subthreshold leakage current
I4 = Gate Oxide tunneling current
I5 = Gate current due to hot Gate current due to hot-carrier injection carrier injection
I6 = Channel punch Channel punch-through through
I7 = Gate induced drain Gate induced drain-leakage current leakage current
Q57. Why leakage power is an important issue in deep submicron technology?
Answer:
In deep submicron technology, the leakage component is a significant % of total power as
shown in the diagram. Moreover, the leakage current is increasing at a faster rate than
dynamic power. As a consequence, it has become an important issue in DSM.
Q58. What is band-to-band tunneling current?
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Answer:
When both n regions and p regions are heavily doped, a high electric field across a
reverse biased p high electric field across a reverse biased p-n junction causes nction
causes significant current to flow through the junction due to tunneling of electrons from
the valence bond of the p of electrons from the valence bond of the p-region to the to the
conduction band of n conduction band of n-region. This is known as band region. This is
known as band-to-band tunneling.
Q59. What is body effect?
Answer:
As a negative voltage is applied to the substrate with respect to the source, the well
respect to the source, the well-to-source junct source junction the device is ion the device
is reverse biased and bulk depletion region is widened. This leads to increase the
threshold voltage. This effect is known as body effect.
Q60. What is subthreshold leakage current? Briefly discuss various mechanisms

responsible for this leakage current?
Answer:
The subthreshold subthreshold leakage current in CMOS circuits is due leakage current
in CMOS circuits is due to carrier diffusion between the source and the drain regions of
the transistor in weak inversion, when the gate voltage is below Vt. The behavior of an
MOS transistor in the subthreshold operating region is similar to a bipolar device, and the
region is similar to a bipolar device, and the subthreshold hreshold current exhibits an
exponential dependence on the gate voltage. The amount of the The amount of the
subthreshold subthreshold current may become significant current may become
significant when the gate when the gate-to-source voltage is smaller than source voltage
is smaller than, but very close , but very close to the threshold voltage of the device.
Q61. Explain the basic concepts of supply voltage scaling.
Answer:
Power dissipation is proportional the square of the supply voltage. So, a factor of two
reduction in supply voltage yields a factor of four decrease in energy. But, as the supply
voltage is reduced, delay increases as shown in the diagram. So, the challenge is to
scale down the supply voltage without compromise in performance.
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Q62. As you move to a new process technology with a scaling factor S = 1.4, how the
drain current, power dissipation, power density, delay and energy requirement changes
for the constant field scaling?
Answer:
Drain current reduces by a factor of S. Although po ough power dissipation decreases by
a factor of S2 , the power density remains the same. The delay decreases by a factor of S
and the energy decreases by a factor of S3 .
Q63. Distinguish between constant field and constant voltage feature size scaling?
Compare their advantages and disadvantages.
Answer:
In this approach the magnitude of all the inte : In this approach the magnitude of all the
internal electric fields l electric fields within the device are preserved, while the
dimensions are scaled down by a factor of S. This requires that all potentials must be
scaled down by the same factor. Accordingly, supply as well as threshold voltages are
scaled down proportionately. But, in constant constant-voltage scaling, all the device
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dimension voltage scaling, all the device dimensions are scal s are scaled down by a
factor of S just like constant down by a factor of S just like constant-voltage s voltage
scaling, supply caling, supply voltage and threshold voltages are not scaled.
Q64. Compare Compare the constant constant field and constant constant voltage
voltage scaling scaling approaches approaches in terms of area, delay, energy and power
density density parameters parameters.
Answer:
Q65. Explain how parallelism can be used to achieve low power instead of high
performance in realizing digital circuits.
Answer:
Traditionally, parallelism is used to improve performance at the expense of larger power
dissipation. But, instead of trying to improve performance, the power dissipation can be
reduced by scaling down the supply voltage such that the performance remains
unaltered.
Q66. Explain how multicore architecture provides low power compared to the single core
architecture of the same performance.
Answer:
The idea behind the parallelism for low-power can be extended to multi-core architecture.
The clock frequency can be reduced with commensurate scaling of the supply voltage as
the number of cores is increased from one to more than one while maintaining the same
throughput.
Q67. Explain the basic concept of multi level voltage scaling.
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Answer:
This is an extension of SVS where two or few fixed voltage domains are used in different
parts of a circuit,. As we know, high Vdd gates have less delay, but higher dynamic and st
gates have less delay, but higher dynamic and static power dissipation and low power
dissipation and low Vdd gates have larger delay but gates have larger delay but lesser
power dissipation. Voltage islands can be generated at different levels of granularity, such
as macro level and standard cell level. The slack of the off cell level. The slack of the off-
critical path can critical path can be utilized for be utilized for allocation of macro modules
of low allocation of macro modules of low-Vdd to off-critical critical-path macro modules.
Total power dissipation can be reduced without degrading the overall circuit performance.
Q68. What is the impact of multiple supply voltages on the distribution of path delays of a
circuit with respect to that for single supply voltage?
Answer:
Path delay for different paths in a circuit for single supply voltage is shown. The graph of
a Gaussian is a characteristic symmetric "bell curve" shape that quickly falls off towards
plus/minus infinity plus/minus infinity. However, when multiple supply voltages are used,
the path delay distribution is not Gaussian because modules having smaller delays are
assigned with smaller supply voltage and their delay increases.
Q69. List and explain the important issues in the context of multiple supply voltage
scaling?
Answer:
Important issues in the context of MVS are listed below:
Voltage Scaling Interfaces
Converter Placement
Floor planning, Routing and Placement
Multiple Supply Voltages
Static Timing Analysis
Power up and Power down Sequencing
Clock distribution
23/24
Q70. What problem arises when a signal passes from low voltage domain to high voltage
domain? How this problem is overcome?
Answer:
A high-level output from the low level output from the low-Vdd domain has output domain
has output VddL, which may turn on both , which may turn on both nMOS and pMOS
transistors of the transistors of the high-Vdd domain inverter resulting in short circuit
between VddH to GND. A level converter needs to be inserted to avoid this static power
consumption
Q71. Explain the design decision for the placement of converters in the voltage scaling
interfaces.
Answer:
One important design decision in the voltage : One important design decision in the
voltage scaling interfaces is the placement of converters . As the high the high-to-low
level converters use low low level converters use low-Vdd voltage voltage rail, it is a
appropriate to place them in the receiving or destination domain. It is also recommended
to place the low place the low-to-high level converters in the r high level converters in the
receiving eceiving domain. As the low domain. As the low-to-high level converters req
high level converters require both low and high both low and high-Vdd supply rails, at
least one of the supply rails, at least one of the supply rails needs to be routed from one
domain to the other.
Q72. What problem arises when a signal passes from low voltage domain to high voltage
domain? How this problem is overcome?
Answer:
A high-level output from the low level output from the low-Vdd domain has output domain
has output VddL, which may turn on both , which may turn on both nMOS and pMOS
transistors of the transistors of the high-Vdd domain inverter resulting in short circuit
between VddH to GND. A level converter needs to be inserted to avoid this static power
consumption
24/24
Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Combinational vs. Sequential Logic
In Out
Logic Logic
In Out
Circuit Circuit
State
(a) Combinational (b) Sequential
Output = f(In) Output = f(In, Previous In)

Static CMOS Circuit
At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

Static CMOS
VDD
In1
In2 PUN PMOS Only
In3
F=G
In1
In2 PDN NMOS Only
In3
VSS
PUN and PDN are Dual Networks

NMOS Transistors in Series/Parallel
Connection
Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors in Series/Parallel
Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0

Complementary CMOS Logic Style Construction (cont.)

Example Gate: NAND

Example Gate: NOR

Example Gate: COMPLEX CMOS GATE
VDD
B
A
C
D
OUT = D + A•(B+C)
A
D
B C

4-input NAND Gate
Vdd
VDD
In1 In2 In3 In4

Out
In1
In2
Out In3
In4
GND
In1 In2 In3 In4

Standard Cell Layout Methodology
metal1 VDD
Well
VSS
Routing Channel
signals
polysilicon

Two Versions of (a+b).c
VDD VDD
x
x
GND GND
a c b a b c
(a) Input order {a c b} (b) Input order {a b c}

Logic Graph
VDD
x
b PUN
j c c
a x i VDD
x
b j a
c
i PDN
GND
a b

Consistent Euler Path
x i
VDD
b a
j
GND
{ a b c}
Example: x = ab+cd
x x
b c b c
x V DD x V DD
a d a d
GND GND
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
V DD
GND
a b c d
(c) stick diagram for ordering {a b c d}

Properties of Complementary CMOS Gates
High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)

Properties of Complementary CMOS
Gates
High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)

Transistor Sizing
•for symmetrical response (dc, ac)
•for performance
V DD
B 12
A 6
Input Dependent
C 12
Focus on worst-case
D 6
F
A 2
D 1
B 2 C 2

Propagation Delay Analysis - The Switch
Model
RON
=
VDD VDD
V DD
Rp Rp Rp
Rp
A B B
A F
Rn Rp
F CL
B A
Rn
CL F
Rn Rn Rn
A CL
A B
A
(a) Inverter (b) 2-input NAND (c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)

What is the Value of Ron?

Numerical Examples of Resistances for 1.2µm
CMOS

Analysis of Propagation Delay
VDD 1. Assume Rn =Rp = resistance of minimum
Rp Rp sized NMOS inverter
A B
2. Determine “Worst Case Input” transition
F (Delay depends on input values)
Rn
CL 3. Example: tpLH for 2input NAND
B - Worst case when only ONE PMOS Pulls
up the output node
Rn
- For 2 PMOS devices in parallel, the
A
resistance is lower
t pLH = 0.69Rp CL
2-input NAND 4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
t pHL = 0.69(2R n)CL

Design for Worst Case
V DD
V DD
1 1 B 4
A A 2
B
F C 4
2 CL
B D 2
F
2 A 2
D 1
A
B 2C 2
Here it is assumed that Rp = Rn

Influence of Fan-In and Fan-Out
on Delay
VDD
A B C D Fan-Out: Number of Gates Connected

2 Gate Capacitances per Fan-Out
A
B
FanIn: Quadratic Term due to:
C
1. Resistance Increasing
D 2. Capacitance Increasing
(tpHL )
tp = a1 FI + a2 FI 2 + a3 FO

tp as a function of Fan-In
4.0
tpHL
3.0
tp (nsec)
2.0 quadratic tp
1.0
tpLH
linear
0.0
1 3 5 7 9
fan-in
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Fast Complex Gate - Design
Techniques
•Transistor Sizing:
As long as Fan-out Capacitance dominates
•Progressive Sizing:
Out
InN MN CL
M1 > M2 > M3 > MN
In3 C3
M3
Distributed RC-line
In2 M2 C2
In1 M1 C1
Can Reduce Delay with more than 30%!

Fast Complex Gate - Design Techniques
(2)
•Transistor Ordering
critical path critical path
CL CL
In3 M3 In1 M1
In2 M2 C2 C2
In2 M2
In1 M1 C1 C3
In3 M3
(a) (b)
(3)
•Improved Logic Design

(4)
• Buffering: Isolate Fan-in from Fan-out
CL CL

Example: Full Adder
V DD
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A
Co B
Co = AB + Ci(A+B)
28 transistors
A Revised Adder Circuit
V DD
VDD V DD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate
Generate
A B B A B Ci A
24 transistors

Ratioed Logic
VDD VDD VDD
Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3
VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS

Ratioed Logic
VDD
• N transistors + Load
Resistive
Load • VOH = V DD
RL
• VOL = RPN
F RPN + RL
In1 • Assymetrical response

In2 PDN
In3 • Static power consumption
•tpL = 0.69 RL CL
VSS

Active Loads
VDD VDD
Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3
VSS VSS
depletion load NMOS pseudo-NMOS

Load Lines of Ratioed Gates
1
Current source
0.75
IL(Normalized)
Pseudo-NMOS
0.5
Depletion load
0.25
Resistive load
0
0.0 1.0 2.0 3.0 4.0 5.0
Vout (V)

Pseudo-NMOS
VDD
F
CL
A B C D
VOH = VDD (similar to complementary CMOS)
2
 VOL  kp 2
k n ( VDD – VTn )VOL – -------------  = ------ ( V DD – VTp )
 2  2
kp
V = (V – V ) 1 – 1 – ------ (assuming that V = V = V )
OL DD T k T Tn Tp
n
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Pseudo-NMOS NAND Gate
VDD
GND

Improved Loads
V DD
M1 M1 >> M2
Enable M2
CL
A B C D
Adaptive Load

Improved Loads (2)
VDD VDD
M1 M2
Out Out
A
A PDN1 PDN2
B
B
VSS VSS
Dual Cascode Voltage Switch Logic (DCVSL)

Example
Out
Out
B B B B
A A
XOR-NXOR gate

Pass-Transistor Logic
Switch Out A
Out
Inputs
Network B
B
•N transistors
• No static consumption

NMOS-only switch
C=5V C=5V
M2
A=5V A=5V B
Mn
B
CL M1
VB does not pull up to 5V, but 5V - VTN
Threshold voltage loss causes

static power consumption

Solution 1: Transmission Gate
C
C
A B A B
C
C
C=5V
A=5V
B
CL
C=0V

Resistance of Transmission Gate
30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
20000.0
R (Ohm)
Rp
10000.0
Req
0.0
0.0 1.0 2.0 3.0 4.0 5.0
Vout

Pass-Transistor Based Multiplexer
S S
VDD
V DD
S
A
M2
S F
M1
GND
In1 S S In2

Transmission Gate XOR
B
M2
A A
F
M1 M3/M4
B

Delay in Transmission Gate Networks
5 5 5 5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In
C C C C C
0 0 0 0
(a)
Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In
C C C C C
(b)
m
Req Req Req Req Req Req

In
C CC C C CC C
(c)
Elmore Delay (Chapter 8)
Vin R1 1 R2 2 Ri-1 i-1 Ri i RN N
C1 C2 Ci-1 Ci CN
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin
N N N i
τN = ∑ Ri ∑ Cj = ∑ C i ∑ R j
i=1 j=i i=1 j=1

Delay Optimization

Transmission Gate Full Adder
P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci
A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

(2) NMOS Only Logic: Level Restoring
Transistor
VDD
Level Restorer VDD
Mr
B
M2
X
A Mn Out
M1
• Advantage: Full Swing

• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Level Restoring Transistor
5.0 with
5.0
without
Vout (V)
3.0 3.0 without

with
VX
VB
1.0 1.0
-1.00 2 4 6 -1.00 2 4 6
t (nsec) t (nsec)
(a) Output node (b) Intermediate node X

Solution 3: Single Transistor Pass Gate with
VT=0
VDD
VDD
0V 5V
VDD 0V Out
5V
WATCH OUT FOR LEAKAGE CURRENTS

Complimentary Pass Transistor Logic
A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network
B B B B B B
A A A
B F=AB B F=A+B A F=A ⊕ ΒÝ
A A A
(b)
B F=AB B F=A+B A F=A⊕ ΒÝ
AND/NAND OR/NOR EXOR/NEXOR

4 Input NAND in CPL

Dynamic Logic
V DD V DD
φ Mp φ Me
Out
In1
CL
In1 In2 PUN
In2 PDN In3
In3 Out
CL
φ Me φ Mp
φn network φp network
•Precharge
2 phase operation:
•Evaluation
Example
V DD
φ Mp
•N + 1 Transistors
Out
•Ratioless
•No Static Power Consumption

A •Noise Margins small (NML )
C
•Requires Clock
B
φ Me

Transient Response
6.0
φ Vout
4.0
EVALUATION PRECHARGE
Vout (Volt)
2.0
0.0
0.00e+00 2.00e-09 4.00e-09 6.00e-09
t (nsec)

Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
φ GND

Reliability Problems —
Charge Leakage
VDD
φ
φ Mp
Out
(1) CL
A t
Vout precharge evaluate
(2)
φ Me
t
(a) Leakage sources (b) Effect on waveforms
Minimum Clock Frequency: > 1 MHz

Charge Sharing (redistribution)
VDD case 1) if ∆V out < VTn
φ Mp
L out ( )
C V = C V t + C (V – V ( V ))
L DD a DD Tn X
Out
or
CL Ca
A Ma ∆V out = Vout ( t ) – V DD = –-------- ( V DD – V Tn ( V X ))
CL
X
Ca
B=0 Mb case 2) if ∆V out > VTn
C
 a 
Cb ∆Vout = –V DD ---------------------- 
φ Me Ca + CL 

Charge Redistribution - Solutions
VDD VDD
Mbl φ Mp Mbl φ
φ Mp
Out
Out
A Ma A Ma
B Mb B Mb
φ Me φ Me
(a) Static bleeder (b) Precharge of internal nodes

Clock Feedthrough
VDD
could potentially forward

φ Mp
bias the diode
Out
CL 5V
A Ma φ
X
Ca
B Mb overshoot
Cb out
φ Me

Clock Feedthrough and Charge Sharing
output without redistribution (Ma off)

feedthrough
out
4
φ
V (Volt)
internal node in PDN
0
0 1 2 3
t (nsec)

Cascading Dynamic Gates
VDD VDD V
φ
φ Mp φ Mp
In
Out1 Out2
Out1
In VTn
Out2 ∆V
φ Me φ Me t
(a) (b)
Only 0→ 1 Transitions allowed at inputs!

Domino Logic
VDD VDD
VDD
φ Mp φ Mp
Mr
Out1
Out2
In1 Static Inverter
In2 PDN In4 PDN with Level Restorer
In3
φ Me φ Me

Domino Logic - Characteristics
•Only non-inverting logic
•Very fast - Only 1->0 transitions at input of inverter

move VM upwards by increasing PMOS
• Adding level restorer reduces leakage and

charge redistribution problems
• Optimize inverter for fan-out

np-CMOS
VDD VDD
φ Mp φ Me
Out1
In1 PUN
In2 PDN In4
In3 Out2
φ Me
φ Mp
Only 1→ 0 transitions allowed at inputs of PUN

np CMOS Adder
V DD V DD
VDD V DD
φ φ S1
φ φ
C i1
A1 B1 B1 A1
B1 Ci1 A1
A1
B1
φ
φ φ Ci2
φ
VDD
VDD
V DD φ
φ
φ B0
A0 Ci1
A0 B0 C i0 A0
A0 B0 B0 C i0
S0
φ φ φ
C i0
Carry Path
Manchester Carry Chain Adder
V DD
Total Area:
225 µm × 48.6 µm
φ 0.5
P0 P1 P2 P3 P4
M0 M1 M2 M3 M4
3 2.5 2 1.5 1
C i,0 1.5 1 C o,4
3.5 3 2.5 2
G0 G1 G2 G3 G4
4 3.5 3 2.5 2
φ 1.5

CMOS Circuit Styles - Summary

CMOS Fundamentals

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CMOS Fundamentals

Q7. Show the basic structure of a MOS transistor.

Q9. How the latch up problem can be overcome?

Q12. What are the basic assumptions of the fluid model?

Q14. Explain the three modes of operation of a MOS transistors ransistors.

Region I: nMOS non-saturated, pMOS cut-OFF.

Q26. How the noise margin is affected by voltage scaling?

Q.29 Find out the capacitance of a MOS capacitor.

Q48. How phase clocks can be generated using inverters?

Timing diagram of the two-phase clock generated from a single-phase clock.

Q52. Explain the clock skew problem of dynamic CMOS circuits?

Q53. How clock skew problem is overcome in in domino CMOS circuits?

Q54. How clock skew problem is overcome in in NORA CMOS circuits?

Q57. Why leakage power is an important issue in deep submicron technology?

Q58. What is band-to-band tunneling current?

Q59. What is body effect?

Q60. What is subthreshold leakage current? Briefly discuss various mechanisms

Q61. Explain the basic concepts of supply voltage scaling.

Q67. Explain the basic concept of multi level voltage scaling.

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Combinational (b) Sequential

Output = f(In) Output = f(In, Previous In)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

At every point in time (except during the switching

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

PUN and PDN are Dual Networks

Transistors can be thought as a switch controlled by its gate signal

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS switch closes when switch control input is low

PMOS Transistors pass a “strong” 1 but a “weak” 0

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

In1 In2 In3 In4

In1 In2 In3 In4

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Input order {a c b} (b) Input order {a b c}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

High noise margins:

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

High noise margins:

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Inverter (b) 2-input NAND (c) 2-input NOR

(assuming that CL dominates!)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Here it is assumed that Rp = Rn

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

A B C D Fan-Out: Number of Gates Connected

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

critical path critical path

•Improved Logic Design

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

• Buffering: Isolate Fan-in from Fan-out