VLSI DESIGN

17EC63
Chetan S, Dept of ECE,SJMIT, Chtradurga
Outline
 Unit-1: a) Introduction
b) Fabrication
 Unit-2: a) MOS and BiCMOS Circuit Design Processes
b) Basic Circuit Concepts
 Unit-3: a) Scaling of MOS Circuits
b) Subsystem Design Processes
 Unit-4: a) Subsystem Design
b) FPGA Based Systems
 Unit-5: a)Memory, Registers and Aspects of system Timing considerations
b) Testing and Verification
 Text books and Reference books
 Unit-1: a) Introduction b) Fabrication

• Introduction: A Brief History, MOS Transistors,

MOS Transistor Theory, Ideal I-V Characteristics,
Non-ideal I-V Effects, DC Transfer Characteristics
(1.1, 1.3, 2.1, 2.2, 2.4, 2.5 of TEXT2).

• Fabrication: nMOS Fabrication, CMOS Fabrication

[P-well process, N-well process, Twin tub process],
BiCMOS Technology (1.7, 1.8,1.10 of TEXT1). L1,
L2
 Unit-2: a) MOS and BiCMOS Circuit Design
Processes
 MOS andb)BiCMOS Circuit Design
Basic Circuit Processes: MOS
Concepts
Layers, Stick Diagrams, Design Rules and Layout.

 Basic Circuit Concepts: Sheet Resistance, Area

Capacitances of Layers, Standard Unit of
Capacitance, Some Area Capacitance Calculations,
Delay Unit, Inverter Delays, Driving Large Capacitive
Loads (3.1 to 3.3, 4.1, 4.3 to 4.8 of TEXT1). L1, L2, L3
Unit-3: a) Scaling of MOS Circuits
b) Subsystem Design
Processes
 Scaling of MOS Circuits: Scaling Models & Scaling
Factors for Device Parameters

 Subsystem Design Processes: Some General

considerations, An illustration of Design Processes,
Illustration of the Design Processes- Regularity, Design
of an ALU Subsystem, The Manchester Carry-
chain and Adder Enhancement Techniques(5.1,
5.2, 7.1, 7.2, 8.2, 8.3, 8.4.1, 8.4.2 of TEXT1). L1, L2, L3
Unit-4: a) Subsystem Design
b) FPGA Based Systems
 Subsystem Design: Some Architectural Issues,
Switch Logic, Gate(restoring) Logic, Parity Generators,
Multiplexers, The Programmable Logic Array (PLA)
(6.1to 6.3, 6.4.1, 6.4.3, 6.4.6 of TEXT1).

 FPGA Based Systems: Introduction, Basic concepts,

Digital design and FPGA‘s, FPGA based System
design, FPGA architecture, Physical design for FPGA‘s
(1.1 to 1.4, 3.2, 4.8 of TEXT3). L1, L2, L3
Unit-5: a)Memory, Registers and Aspects of system Timing
considerations
b) Testing and Verification
 Memory, Registers and Aspects of system
Timing- System Timing Considerations, Some
commonly used Storage/Memory elements (9.1, 9.2
of TEXT1).

 Testing and Verification: Introduction, Logic

Verification, Logic Verification Principles,
Manufacturing Test Principles, Design for testability
(12.1, 12.1.1, 12.3, 12.5, 12.6 of TEXT 2). L1, L2, L3
Text books and Reference books

Text Books:
1. “Basic VLSI Design”- Douglas A. Pucknell& Kamran Eshraghian,
PHI 3rd Edition (original Edition – 1994).

2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil

H.E. Weste, David Harris, Ayan Banerjee, 3rd Edition, Pearson
Education.
Unit-1: a) Introduction
A Brief History

 In 1958-Jack Kilby built the first integrated circuit flip-flop with two transistors
at Texas Instruments.
 In 2008, Intel’s Itanium microprocessor contained more than 2 billion transistor
and a 16 Gb Flash memory contained more than 4 billion transistors.
 This corresponds to a compound annual growth rate of 53% over 50 years. No
other technology in history has sustained such a high growth rate lasting for
so long.
 miniaturization of transistors and improvements in manufacturing processes.
 other fields of engineering involve tradeoffs between performance, power, and
price. However, as transistors become smaller, They also become faster,
dissipate less power, and are cheaper to manufacture.
Figure 1.1 shows annual sales in the worldwide semiconductor market. Integrated circuits became a $100 billion/year


business in 1994. In 2007, the industry manufactured approximately 6 quintillion (6 × 1018) transistors, or nearly a billion
for every human being on the planet.

Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization if multiple transistors could be


built on one piece of silicon.

 Figure 1.2(b) shows his first prototype of an integrated circuit, constructed
from a germanium slice and gold wires.

• The invention of the transistor earned the Nobel Prize in Physics in 1956
for Bardeen, Brattain, and their supervisor William Shockley. Kilby
received the Nobel Prize in Physics in 2000 for the invention of the
integrated circuit.
 Transistors can be viewed as electrically controlled switches with a
control terminal and two other terminals that are connected or
disconnected depending on the voltage or current applied to the
control.

 Soon after inventing the point contact transistor, Bell Labs developed
the bipolar junction transistor. Bipolar transistors were more reliable,
less noisy, and more power-efficient.

 Early integrated circuits primarily used bipolar transistors. Bipolar

transistors require a small current into the control (base) terminal to
switch much larger currents between the other two (emitter and
collector) terminals.

 By the 1960s, Metal Oxide Semiconductor Field Effect Transistors

(MOSFETs) began to enter production - advantage that they draw
almost zero control current while idle.
 In 1965, Gordon Moore observed that plotting the number of transistors
that can be most economically manufactured on a chip gives a straight
line on a semilogarithmic scale.

 At the time, he found transistor count doubling every 18 months. This

observation has been called Moore’s Law.

 Figure 1.4 shows that the number of transistors in Intel microprocessors

has doubled every 26 months since the invention of the 4004.
The level of integration of chips has been classified as small-scale,
medium-scale, large-scale, and very largescale.

• Small-scale integration (SSI) circuits, such as the 7404 inverter,

have fewer than 10 gates, with roughly half a dozen transistors per
gate.
• Medium-scale integration (MSI) circuits, such as the 74161 counter,
have up to 1000 gates.
• Large-scale integration (LSI) circuits, such as simple 8-bit
 MOS Transistor
• Silicon (Si), a semiconductor, forms the basic starting
material for most integrated circuits.

• Silicon is a Group IV element in periodic table, it forms

covalent bonds with four adjacent atoms, as shown in
Figure 1.3(a). As the valence electrons of it are involved
in chemical bonds, pure silicon is a poor conductor.

• However its conductivity can be increased by Fig 1.3 Silicon lattice and dopant atoms
introducing small amounts of impurities, called
dopants, into the silicon lattice.

• This results in As+ ion and a free electron. The free

electron can carry current and this is an n-type
semiconductor.

• A Metal-Oxide-Semiconductor (MOS) structure is

created by superimposing several layers of
conducting and insulating materials to form a
sandwich-like structure.
 • Transistors can be built on a single crystal of silicon, which are available as thin flat circular wafer
of 15–30 cm in diameter.

• CMOS technology provides two types of transistors an n- type transistor (nMOS) and a p-type
transistor (pMOS).

• Transistor operation is controlled by electric fields so the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. Cross-sections and symbols of
these transistors are shown in Figure 1.4. The n+ and p+ regions indicate heavily doped n- or p-
type silicon.

Fig 1.4
(a) nMOS transistor
and
(b) pMOS transistor
• Each transistor has conducting gate, an insulating layer of silicon dioxide (SiO2, also known
as glass), and the silicon wafer, also called the substrate/body/bulk. Gates of early transistors
were built from metal, so was called Metal-Oxide-Semiconductor, or MOS.

• Even though the gate has been formed from polycrystalline silicon (polysilicon), the name
is still metal.

• An nMOS transistor is built with a p-type body and has regions of n-type semiconductor
adjacent to the gate called the source and drain. They are physically equivalent and they
can be interchangeable. The body is typically grounded.

• A pMOS transistor is just the opposite, consisting of p-type source and drain regions with
an n-type body.

• In both the gate is the control input.

nMOS Transistor:
• It controls the flow of electrical current between the source and drain.

• Considering an nMOS transistor, its body is generally grounded so

the p–n junctions of the source and drain to body are reverse-biased. If
the gate is also grounded, no current flows through the reverse-biased
junctions and the transistor is OFF.

• If the gate voltage is raised, it creates an electric field that starts to

attract free electrons to the underside of the Si–SiO2 interface.

• If the voltage is raised enough, the electrons outnumber the holes and a
thin region under the gate called the channel is inverted to act as an n- nMOS transistor
type semiconductor.

• Hence, a conducting path is formed from source to drain and current

can flow. This is the condition for transistor is ON state.

• Thus when the gate of an nMOS transistor is high, the transistor is ON

and there is a conducting path from source to drain. When the gate is
low, the nMOS transistor is OFF and almost zero current flows from
source to drain.
pMOS Transistor:
• The condition is reversed.

• The body is held at a positive voltage and also when the gate
is at a positive voltage, the source and drain junctions are
reverse-biased and no current flows, the transistor is OFF.

• When the gate voltage is reduced, positive charges are

attracted to the underside of the Si–SiO2 interface. A
sufficiently low gate voltage inverts the channel and a
conducting path of positive carriers is formed from source to pMOS transistor
drain, so the transistor is ON.

• The symbol for the pMOS transistor has a bubble on the gate,
indicating that the transistor behavior is the opposite of the
nMOS.

• A pMOS transistor is just the opposite of that of nMOS. It is

ON when the gate is low and OFF when the gate is high.
MOS Transistor Theory:

• MOS transistor is a majority-carrier device - current in channel between the

source and drain is controlled by a voltage applied to the gate.

• In nMOS transistor - majority carriers are electrons

• In pMOS transistor - majority carriers are holes.

• To understand the behavior of MOS transistors, an isolated MOS structure with a

gate and body but no source or drain is consider.

For an N-Device,

• It has top layer of good conducting gate layer. Middle layer is insulating oxide layer
and bottom layer is the p-type substrate i.e doped silicon body. Since it is a p-type
body carriers are holes.
MOS Transistor Theory:
Operation:

Fig 1.6(b) Depletion

Fig 1.6 (a) Accumulation

• When a negative voltage is applied to the gate, the positively charged holes are attracted
to the region beneath the gate. This is called the accumulation mode shown in Fig 1.6(a)

• When a small positive voltage is applied to the gate, the positive charge on the gate
repels the holes resulting a depletion region beneath the gate as shown in Fig 1.6(b)
• When a higher positive potential exceeding a critical threshold voltage V t is applied, the
holes are repelled further and some free electrons in the body are attracted to the region
beneath the gate. This results a layer of electrons in the p-type body is called the inversion
layer.

Fig 1.6(c) Inversion

 Cutoff :
• When gate-to-source voltage, Vgs is less than threshold
voltage and if source is grounded, then the junctions
between the body and the source or drain are zero-
biased or reverse- biased and no current flows. We say
the transistor is OFF, and this mode of operation is called
cutoff. This is shown in above fig. 1.7(a).

linear, resistive, triode, nonsaturated, or unsaturated :

• When Vg> Vt = establishment of channel, & creating a
conductive path and turning the transistor ON Fig 1.7(b).

• The number of carriers and the conductivity increases

with the gate voltage. The potential difference between
drain and source is Vds= Vgs - Vgd. If Vds = 0 (i.e., Vgs =Vgd),
there is no electric field tending to push current from
drain to source.

• When a small positive potential Vds is applied to the

drain, current Ids flows through the channel from drain to
source. This mode of operation is termed linear, resistive,
triode, nonsaturated, or unsaturated mode as shown in
Fig 1.7 (c)
Fig 1.7 (a) nMOS demonstrating Cutoff and Linear operation
Saturation:
• If Vds becomes sufficiently large that Vgd < Vt, the channel is no longer inverted near
the drain and becomes pinched off (Fig 1.7(d)).
• However, conduction is still brought about by the drift of electrons under the
influence of the positive drain voltage. Above this drain voltage the current I ds is
controlled only by the gate voltage and ceases to be influenced by the drain. This
mode is called saturation.

Fig 1.7 (d) Saturation

pMOS Transistor
• The pMOS transistor in Fig 1.8 operates in just the opposite fashion. The n-type body is
tied to a high potential so the junctions with the p-type source and drain are normally
reverse-biased.
• When the gate is also at a high potential, no current flows between drain and source.
When the gate voltage is lowered by a threshold Vt, holes are attracted to form a p-
type channel immediately beneath the gate, allowing current to flow between drain
and source.

Fig 1.8 pMOS Transistor

Ideal I-V Characteristics:
• Considering Shockley model, which assumes the current through an OFF transistor is 0
i.e., when Vgs < Vt there is no channel and current from drain to source and is 0.(cutoff)
• In other 2 regions (linear and saturation) channel is formed and electrons flow from source to
drain at a rate proportional to electric field (field between source and drain).

• If the amount of charge in the channel and the rate at which it moves is known, we can
determine the current.

• The charge on parallel plate of capacitor is given by, Q = C.V

• Here the charge in the channel is denoted by Qchannel and is given by Qchannel = Cg . Vc
Where Cg – capacitance of gate to the channel
Vc – amount of voltage attracting charge to the channel

• If we model the gate as a parallel plate capacitor, then capacitance is given by Area/Thickness
 Fig a. Capacitance effect at the gate terminal Fig b. Transistor dimensions

• If gate is having length L and width W and the oxide thickness is t ox, as shown in Fig b, the
capacitance is given by,

• Often, the Ԑox/tox term is called Cox, the capacitance per unit area of the gate oxide.
• Thus capacitance is now Cg = Cox W L
• Now the charges induced in channel due to gate voltage is determined by taking the
average voltage between source and drain (Fig. a) and it is given by
• To form the channel and carriers to flow, the voltage condition at source and drain is as follows:

Qchannel = Cg . Vc
• The velocity of charge carrier in the channel is proportional to lateral electric field
(field between source and drain) and it is given by,

Where μ is the proportionality constant called ‘mobility’

• The electric field E is the voltage difference between drain and source to the length
of channel. Given by,

• The current in the channel is given by the total amount of charge in channel and
time taken by them to cross. The time taken is given by length to velocity.

Qchannel = Cg . Vc
Upon simplification, Ids is given by:

Expression of current
when mosfet in linear
region operation for Vgs
> Vt

• The above equation for current describes linear region operation for Vgs > Vt
• When Vds is increased to larger value i.e., Vds > Vsat = Vgs – Vt, the channel is no
longer inverted and at the drain channel gets pinched off.
• Beyond this is the drain current is independent of Vds and depends only on the gate
voltage called as saturation current.
• The expression for the saturation current is given by
Expression of current
when mosfet in
saturation region
pMOS Transistor:

• pMOS transistors behave in the same way, but with the signs of all voltages and
currents reversed. The I-V characteristics are in the third quadrant, as shown in Fig.

Fig. Plot of I-V characteristics of (a) nMOS and (b) pMOS

Non ideal I-V Effects:

• The ideal I-V model does not consider many effects that are important to modern devices. These
effects are as follows:

Velocity saturation:
• Electron velocity is related to electric field through mobility by the equation
v = μ E , where E is the lateral electric field or field between drain and source.
• It is assumed that μ is constant and independent parameter w.r.t, E
• At higher E, μ is no more constant and it varies and is due to velocity saturation effect
• When electric field reaches a critical value say Esat, the velocity of charge carriers tend
to saturate due to scattering effect at Esat. This is shown in graph below.
• The impact of velocity saturation is modelled as follows:
Before the velocity reaches critical value,
When the velocity reaches critical and greater it is given by,
𝑣 = 𝑉𝑠𝑎𝑡
 Basic MOS transistors

• E-MOSFET – does not conduct when Vgs =0 ( as there

is no channel established between source and drain)
• D-MOSFET remains in the conducting mode when
Vgs=0( due to presence of channel).
• For switching off D-MOSFET a negative voltage has to
be applied to the gate.
MOSFET as switch
Circuit Symbols of MOSFET
N-MOS Device formation
• Substrate used is of P-type with
moderate doping level
• Source and drain are formed with
suitable masks by diffusing n-type
impurities
• For connections metal is
deposited on S&D
• Oxide layer is formed between
S&D
• Polysilicon is deposited on top of
insulation layer and metal contact
is made for gate
 For D-MOSFET
• Channel is established in manufacturing
process itself by implanting suitable impurities
in between S&D.
E-MOSFET
 E-MOSFET Action
• When Vgs Vt then (Vgs –Vt) is called as the
‘effective gate voltage’
• Because there will be no current flow when
Vgs Vt
• Based on value of Vds , there are three
conditions
a)
b)
c)
• In saturated region as Vds is positive the depletion region expands near
the drain (channel established between S&D) and transistor will be in
conducting state

• In saturation region as Vds Vgs-Vt the depletion region’s expansion is

much larger due to which part of the channel get piched off.

• How ever transistor remains in the conducting state due to diffusion

current.

• But the current remains constant the onwards thus the channel exhibits
high resistance and the transistor behaves as a constant current source
Module 1- fabrication
nMOS FABRICATION
1. A thin wafer cut from a cylindrical
crystal of silicon is used as substrate.
• Typical dimentions: 75-150mm dia
0.4 mm thickness.
• Substrate is doped with boron to make it p-type
• Impurity concentration is 1015 /cm3 to 2516/ cm3
• Resistivity of 25Ω-cm to 2Ω-cm.

2. An oxide layer is grown all over the surface called

‘THICK-OXIDE’ or ‘FIELD-OXIDE’.
• Thickness - 1µm, acts as protective layer to
• the wafer for the subsequent processes
3. Surface is covered with an even distribution of PR
• Two types in PR – positive and negetive
• +ve PR – the exposed areas are removed
• -ve PR- the unexposed areas are removed
• Here –ve PR is used

4. PR layer is then exposed to UV light

by means of the required mask.
• The exposed areas are polymerized and they get
hardened

5. The unexposed areas are then etched away

Along with the underlying Sio2
6. Remaining PR is removed and,
• A thin layer of 0.1µm thickness is grown
over the entire chip surface.
• This layer is called as ‘THINOX’ or ‘GATE-OXIDE’
• heavily doped polysilicon is deposited over this
‘THINOX’ to define gate areas.
• Polisilicon deposition is done by CVD –chemical
vapour depostion.

7. The ‘thinox’ is removed by further

processes of PR coating, masking and etching
• The S and D are formed by diffusion of n-type
impurities, by passing PH3 over the surface.
As the polisi & oxide layer acts as masks, the
process is called self aligned.

8. Thick oxide is grown all over gain and then

the previous processes(PR coating, masking and
etching) are carried out, to expose the selected
Areas where contact cuts are to be made for S,G &D.
 9. Finally a metal of 1µm thickness is
deposited all over the surface
• It is again processed to form the required
Interconnections.

Note :
• For D-mosfet fabrication ‘ION IMPLEMENTATION’ process is performed
in which the n-type impurities are made to pass through the ‘thinox’.

• ‘self-alligning’ reduces the no of masks that are goin to be utilized.

• After metallization a final process called ‘ OVER GLASSING ‘ is performed to

prevent exposure of chip to the external atmosphere. This layer is called
‘pevention layer.
 CMOS FABRICATION

When we need to fabricate both nMOS and pMOS transistors on

the same substrate we need to follow different processes. The
three different processes are, P-well process ,N-well process and
Twin tub process.
 P-WELL PROCESS
• The p-well process starts with a n type substrate. The n type substrate can be used
to implement the pMOS transistor,
• But to implement the nMOS transistor we need to provide a pwell, hence we have
provided he place for both n and pMOS transistor on the same n-type substrate.
 Mask sequence.
Mask 1: Defines the areas in which the deep p-well diffusion takes place.

Mask 2: It defines the thin oxide region (where the thick oxide is to be removed or stripped
and thin oxide grown)

Mask 3: It‘s used to pattern the polysilicon layer which is deposited after thin oxide. Mask

Mask 4: A p+ mask (anded with mask 2) to define areas where p-diffusion is to take place.

Mask 5: We are using the –ve form of mask 4 (p+ mask) It defines where n-diffusion is to
takeplace.

Mask 6: Contact cuts are defined using this mask.

Mask 7: The metal layer pattern is defined by this mask.

Mask 8: An overall passivation (over glass) is now applied and it also defines openings for
accessing pads.
The cross section below shows the CMOS pwell inverter.

CMOS inverter (P-WELL)

 1.8.2 The n-WELL PROCESS

Advantages of n-well CMOS Device

 Lower substrate bias effects on transistor Vt.

 Lower parasitic capacitances associated with S & D regions.
N-well fabrication steps

1. The first mask defines n –well region

2. Followed by low dose PH implant driven by a high temperature diffusion
step to form n-wells
3. Define devices and diffusion paths
4. Grow field oxide
5. Deposit and pattern the polysilicon and carryout the diffusion
6. Make contact cuts
7. metallization
1. n+ mask and its complement may
be used to define the n- and
p+ diffusion regions respectively

2. These same masks also include the

VDD and Vss contacts.(respectively)

3. Alternatively, we could have used

a p+ mask and its Complemet
since the n+ and p+ masks are
generally complementary
Inverter circuit fabricated by the n-well process
1.8 TWIN-TUB process
 Twin-tub process allows separate optimization of the n- and p-transistors. Due
to individual control of doping. Due to which gain and vt can be individually adjusted.
 Start with a substrate of high resistivity n-type material and then create both
n-well and p-well regions.
 Through this process it is possible to preserve the performance of
n-transistors without compromising the p-transistors.
 Epi layer utilized here to prevent short circuit of the device
 Epi layer is lightly doped hence has higher resistivity is used to prevent latch-up

Latch-up
During fabrication of n-well and p-well it gives rise to formation of parasitic
bipolar transistors these gives rise to ‘LATCH-UP’ in which
Vdd and Vss is shortened.
• nmos is a lower temperature process
Compared to cmos.

• Hence nmos has advantage of ease fabrication

•And also it has higher density per unit area

•In contrast , cmos has the advantages of lower

power consumption an ease of circuit design.
 BICMOS TECHNOLOGY
• nmos technology has limited source and sinking capabilities.

• to design so called super-buffers using MOS transistors alone, such arrangements do not
always compare well with the capabilities of bipolar transistors.

•Bipolar transistors also provide higher gain and have generally better noise and high
frequency characteristics than MOS transistors and it may be seen Figure that BiCMOS
gates could be an effective way of speeding up VLSI circuits.
• The production of NPN bipolar transistors with good performance characteristics can be
achieved, for example,

• by extending the standard n-well CMOS processing to include further masks to add two
additional layers, the n + subcollector and p + base layers.

•The npn transistor is formed in an n-well and the additional P+ base region is located in
the well to form the p-base region of the transistor.

• The second additional layer-the buried n+ subcollector (BCCD) is added to reduce the n-
well (collector) resistance and thus improve the quality of the bipolar transistor.

• The simplified general arrangement of such a bipolar npn transistor may be appreciated
with regard to Figure 1.16.
 For clarity, the layers have not been drawn
transparent but, BCCD underlies the entire
area the layers have not been drawn
transparent but BCCD underlies the entire
area and the p+ base underlies all within its
boundary. and the p+ base underlies all
within its boundary.

Arrangement of BiCMOS NPN

transistor (Orbit 2 µm CMOS).
Ideal v-I characteristics
• A voltage on the gate terminal
induces a charge in the channel
that exists b/w S and D
• The charge then move from S to
D under influence of electric field
generated by voltage VDS applied
b/w D&S.
• The charge induced is dependent
on VGS. The current IDS is
dependent on both VGS & VDS
• the relationship between these
parameters can be developed
• Expression for transit time
Non saturated region
 15

16
14
VDS = VD – Vs =10-9.9=0.1V
VGS = 0v
Given Vt = -1v
ß=1mA/v2
drain current ID is given by
 Saturation region
• Device enter into
saturation when Vds = 17
VGS –Vt
18
• At this point the IR
drop in channel
19
equals to the effective
gate voltage.
• Current through the
channel remailns 20
constant for any
further increment in
VDS.
• The expression for IDS hold for both, the depletion and enhancement mode devices
• Vt for nmos-D device is –ve and denoted by Vtd

• Typical characteristics for nMOS

Transistors are shown in fig.
• pMOS transistor characteristics
are similar With reversal of polarity
summary
 Non ideal I-V characteristics

• In all three regions we derived some non theoretical effects were neglected.
• Practically in nonlinear saturation region, the saturation current increases less than quadraticaly
with increasing VGS because of velocity saturation and mobility degradation.

1.VELOCITY SATURATION
• If the transistor is completely velocity saturated i.e V=Vsat ,saturation current
expression is modified to IDS = C0 W(Vgs–Vt)Vsat
• here the Id is quadraticaly dependent on voltage without velocity saturation and
linearly dependent when fully velocity saturated.
• This behaviour is approximated by -power model where  is called velocity
modulation index.
• where ID can be moderated as
2. MOBILITY DEGRADATION

• Due to large VGS, vertical electrical fields cause the carriers to scatter and
reduces the carrier mobility-µ - this phenomenon is called mobility
degradation. Modeled by µeff.
3. CHANNEL LENGTH MODULLATION

• Perfect current source- transistor in saturation – ideally IDS independent of VDS

• Reverse biased p-n junction between D&B forms depletion region with width
Ld that increases with reverse bias vg. The depletion region effectively shortens
the channel length
Leff =L-Ld

• Shorter channel length results in higher Ids increases with Vds.

• Id in saturation is given by ( v  v ) 2

I  (1  V )
gs t
d ds
2
• λ = channel length modulation factor. And inversely proportional to channel
length.
4. BODY EFFECT – EFFECT OF SUBSTRATE BIAS

• Consider 2 nmos transistors connected in

vertically series.
• And Source to substrate vg Vsb is observed vertically
Upward .
• Vsb1 =0, Vsb2 ≠0 variation of Vsb leads to variation in Vt’s
• Vsb2 >Vsb1 therefore Vt2 >Vt1
• This variation of threshold voltage is referred as
‘BODY EFFECT’
• Body effect is because of variation in depletion
• region under oxide
Mos models – small signal model
 MOS LAYERS
MOS design is aimed at turning a specification into masks for processing silicon to meet the
specification.

We have seen that MOS circuits are formed on four basic layers-n-diffusion, p-diffusion,
polysilicon, and metal, which are isolated from one another by thick or thin
(thinox) silicon dioxide insulating layer.

The thin oxide (thinox) mask region include

n-diffusion , p-diffusion, and transistor channels . Polysilicon and thinox regions interact so
that a transistor is formed where they cross one another.

In some processes, there may be a

second metal layer and also, in some processes, a second polysilicon layer. Layers may
deliberatelY joined together where contacts are formed .
Encodings for a simple metal nMOS process
COLOR PLATE 1(a) Encodings for a simple single metal nMOS process.
COLOR PLATE 1 (b) Color encodings for a double metal CMOS p-well process. The same well encoding and demarcation
line is used for an n-well process. For a p-well process, the n features are in the well. For an n-well process, the p features
are in the well.
Additional encodings for a double metal double poly. BiCMOS n-well process
Stick diagrams and simple symbolic encoding
Transistors
A transistor exists where a polysilicon stick crosses either an N diffusion stick
(NMOS transistor) or a P diffusion stick (PMOS transistor).
Stick Diagram Colour Code
 DESIGN RULES AND LAYOUT

•Design Rules objective: to allow a ready translation of circuit design concepts, usually in stick
diagram or symbolic form, into actual geometry in silicon.

•The design rules are the effective interface between the circuit/system designer and the
fabrication engineer.

•Circuit designers in general want tighter, smaller layouts for improved performance and
decreased silicon area.

• The process engineer wants design rules that result in a controllable and reproducible
process.
 Lambda(ƛ)-based Design Rules

• Design rules and layout methodology based on the concept of ƛ provide a process and feature
size-independent way of setting out mask dimensions to scale.

• All paths in all layers will be dimensioned in ƛ units and subsequently ƛ can be allocated an
appropriate value compatible with the feature size of the fabrication process.

• For example, A can be allocated a value of 1.0 µm so that minimum feature size on chip will
be 2µm(2ƛ).

• Design rules, also due to Mead and Conway, specify line widths, separations, and extensions in
terms of ƛ, and are readily committed to memory.
ƛ - Design rules can be conveniently set out in diagrammatic form as - for the widths and
separation of conducting paths.
ƛ - Design Rules for extensions and separations associated with transistor layouts
The design rules associated with contacts between layers are set out in Figures (a) and (b) and it will be noted that connection can be made
between two or, in the case of nMOS designs, three layers.
 Contact Cuts
• There are three possible approaches When making contacts between polysilicon and diffusion in nMOS circuits.

1. Poly. to metal then metal to diff.,

2. Buried contact poly. to diff – Polysilicon comes over diffusion.
3. Butting contact (poly. to diff. using metal) – Polysilicon and diffusion are joined by metal.

• Buried contact is the most widely used, giving economy in space and a reliable contact.

• In CMOS designs, poly. to diff. contacts are almost always made via metal. When making connections between metal and
either of the other two layers ,

• The process is quite simple. The 2ƛ. x 2ƛ. contact cut indicates an area in which the oxide is to be removed down to the
underlying polysilicon or diffusion surface. When deposition of the metal layer takes place. the metal is deposited through
the contact cut areas onto the underlying area so that contact is made between the layers.
When connecting diffusion to polysilicon using the butting contact approach, the process is rather more
complex
• In effect, a 2ƛ. x 2ƛ. contact cut is made
down to each of the layers to be joined.

• The layers are butted together in such a

way that these two contact cuts become
contiguous.

• Since the polysilicon and diffusion

outlines overlap and thin oxide under
polysilicon acts as a mask in the diffusion
process , the polysilicon and diffusion
layers are also butted together.

• The contact between the two butting

layers is then made by a metal overlay as
shown in the figure.

Contacts polysilicon to diffusion (nMOS only in the main text).

The buried contact approach shown in Figures is
simpler,
• The contact cut (broken line) in this case indicating
where the thin oxide is to be removed to reveal the
surface of the silicon wafer before polysilicon is
deposited.

•Thus, the polysilicon is deposited directly on the

underlying crystalline wafer. When diffusion takes
place, impurities will diffuse into the polysilicon as
well as into the diffusion region within the contact
area.

•Thus a satisfactory connection between polysilicon

and diffusion is ensured .

•Buried contacts can be smaller in area than their

butting contact counterparts and, since they use no
metal layer, they are subject to fewer design rule
restrictions in a layout
 Double Metal MOS Process Rules
•Here the oxide below the metal is deposited by means of APCVD(atmospheric pressure
CVD)

•For the removal of selected areas of the oxide, plasma etching is employed

Routing tips :
1.use metal -1 for local distribution of power and signal lines
2.use metal -2 for global distribution of power buses (v dd, Vss , CLK)
3. Lay the two metal layers such that the conductors are mutually orthogonal, wherever
possible.
 Lambda based Design Rules for CMOS
•The CMOS fabrication process is much more complicated and elaborate design rules exist for the same.
A simplified abstract of the actual processing steps which are used to produce the chip are shown.
• Otherwise the documentation of actual set
of design rules used in practice would run
into several pages of diagrams and
description. Two such micron-based rule sets
are presented here.

• Actually these rules are an extension of the

lambda-based rules set out in Fig. 2.3.1 to
Fig. 2.3.5 for nMOS designs with the butting
and buried contacts excluded.
• The additional rules for CMOS
are given in Fig. and are,
pertaining to those features
unique to thep-well CMOS, like p+
mark and p-well and some special
'substrate' contacts.

• We note that the rules given for

the p-transistors and p-contacts
are also easily translatable to an
n-well process
A set of construction rules can be derived to construct logic functions.
• NMOS devices connected in series corresponds to an AND function.
• NMOS transistors connected in parallel represent an OR function
• A conducting path exists between the output and input terminal if at least one of the
inputs is high.
Using similar arguments, construction rules for
PMOS networks can be formulated. A series connection of PMOS conducts if both
inputs are low, representing a NOR function (A.B = A+B), while PMOS transistors in
parallel implement a NAND (A+B = A·B)
Using De Morgan’s theorems ((A + B) = A·B and A·B = A + B), it can be shown that the
pull-up and pull-down networks of a complementary CMOS structure are dual networks.
This means that a parallel connection of transistors in the pull-up network corresponds
to a series connection of the corresponding devices in the pull-down network, and vice
versa.
 Basic Circuit Concepts

• The MOS devices are fabricated by superimposing various layers of conducting,

insulating and transforming materials.
• In a conventional silicon gate process an active device requires a gate forming
region and source-drain forming region, which consists of diffusion, polysilicon and
metal layers separated by insulating layers.
• There are resistance and capacitance associated with each layer. These
resistances and capacitances are fundamental components in estimating
performance of overall system.
• System performance is evaluated in terms of delays and power dissipation. The
issues to be considered are listed here –
1. Resistance, capacitance and inductance. 2. Delay computation. 3. Calculation of
conductor size for clock and power. 4. Power dissipation/consumption. 5. Charge
sharing mechanism. 6. Design margin. 7. Reliability. 8. Effects of scaling.
 Sheet Resistance ( RS )
•The sheet resistance Rs is a measure of resistance of a thin
film that have a uniform thickness.

•The sheet resistance is used to evaluate the outcome of

semiconductor doping, metal deposition and resistive paste
printing.

• A uniform slab of conducting material is shown in Fig. with

dimensions. Resistance of sheet along its length AB is given
by

•. Where A = cross-section area

Note that Rs is completely independent of the area of the
square.
Thus
Now, consider the case in which L = W, that is, a where
square of resistive material, then
Rs= ohm per square or sheet resistance
Thus
Area Capacitances of Layers
• The conducting layers are separated from the substrate and each other by
insulating (dielectric) layers. Therefore parallel plate capacitive effects are
present.
For any layer, the area capacitances can be computed by knowing the dielectric (silicon
dioxide) thickness.
by formula,
Standard unit of capacitance
 Some Area Capacitance Calculations
The calculation of capacitance
values may now be undertaken by
establishing the ratio between the area of
interest and the area of standard (feature That is, the defined area in metal has a capacitance to
size square) gate (2λx2λ for λ-based rules) substrate 1.125 times that of a feature size square gate area.
and multiplying this ratio by the
appropriate relative C value from Table, The
product will give the required capacitance
in Cgunits. units.
First, we must calculate the area relative to that of a
standard gate. By,

Capacitance Calculation for Multilayer

In multilayer substrate total capacitance calculation is sum of

metal capacitance (Cm), polysilicon capacitance (Cp) and gate
capacitance (Cg).

Total capacitance C T = C m + C p + Cg
 3.

Therefore,

Consider the metal area (less the contact region where the
metal is connected to polysilicon and shielded from the
substrate)

1.

2.
 THE DELAY UNIT τ
For defining standard units for basic circuit
parameters, a standard delay unit τ is defined.
Consider one standard (feature size square) gate area
capacitance being charged through one feature size
square of n-channel resistance (that is through
substrate resistance RS of nMOS pass transistor
channel). As in fig we have,
However, circuit wiring and parasitic capacitances have an
effect on propagation of signals which must be catered for.
Hence, in practice, the figure for τ is often increased by a
factor of two or three and then used for design. Then
value of τ for 5 4m circuit comes out to τ = 0.2 to 0.3 n sec for
assessing likely worst case delays.

The τ so obtained is quite close to the transit time

τ sd calculated above.
As the gate capacitance Cg charges from 0 V to 63 %
of Vdd Vds also varies. Referring Fig. we take an
appropriate value for Vds as the average value of
3 volts. Then, for the 5µm process,
The safe figures recommended for use for
design in different technologies are as follows :
(a) 5 µm MOS technology, τ = 0.3 nsec
(b) 2 µm MOS technology, τ = 0.2 nsec
(c) 1.2 µm MOS technology, τ = 0.1 nsec

Which is not much different from the theoretical time

constant τ calculated above as 0.1 nsec. Thus the
transit time and time constant (as defined for the delay
unit τ ) are synonymous and can be interchangeably
used.
The 'stray' capacitances are usually catered for by
doubling (or more) the theoretical values
calculated. Thus τ serves as a fundamental time
unit and all timings in a system can be assessed
interms of τ .
INVERTER DELAYS - Delay Associated with Single and Cascaded Inverters
• Thus there is an asymmetry in and Rp.u and Rp.d Hence
delay associated with inverter will depend on whether it is
being turned-off or on. However, conditions are different
with a pair of cascaded inverters.

• As shown in Fig. , here the delay over the inverter pair is

constant irrespective of the type of logic level transition of
the input of the first inverter. This is because transition
at input of second inverter is opposite to that at the input
of first inverter.

• Note that the delay in turning on is τ while the

corresponding delay in turning-off is 4 τ. Taking τ = 0.3
nsec and making no extra provisions for wiring
capacitances, the overall delay comes out to τ + 4 τ = 5 τ.
Interms of p.u. and p.d. impedances, the delay through a
pair of identical nMOS inverters can be generalized as

Thus, the inverter pair delay for inverters having 4: 1 ratio is 5 τ

• As per this formula, also, delay for pair of inverters
having 4 : 1 ratio comes to 5 τ.

• In case of CMOS inverters, the ratio rule relevant in

nMOS no longer applies. However there is a natural
asymmetry in the Rs between the pull-up and pull-
down devices which has to be catered for.

• This is because the pull-up device is a p-type and the

pull-down device is of n-type. Estimation of delay
associated with a pair of minimum size (both n and p-
transistors) lambda-based inverters.

• is illustrated in Fig.Since the input to a CMOS inverter is

connected to the gate of both the transistor the gate
capacitance is double that of the comparable nMOS
inverter. Fig. also indicates the consideration made
for the asymmetric channel resistances.
Note:
The asymmetry of resistance values can be eliminated by
increasing the width of the p-device channel by a factor of
two or three, but it should be noted that the gate input
capacitance of the p-transistor is also increased by the same
factor.
 A More Formal Estimation of CMOS Inverter Delay

• The delay associated with the CMOS inverter can be more

precisely estimated by splitting the output transitions
into fall-time τf and rise-time τr corresponding to the
charging and discharging of the capacitive load CL.

• These two phenomenon can be independently

estimated more precisely to arrive at the overall delay.
Estimation of Rise-time.

Estimation of Rise-time

• The pull-up p-device drives the capacitive load and can

be assumed to be in saturation for the entire charging
period of the load capacitor CL.
This current being constant the output voltage is given
by
• The equivalent circuit for this condition is shown in
Fig. Now the saturation current for the p-transistor is
given by
 Estimation of Fall-time
• Fall-time is associated with the discharging of LC
through the pull-down n-type device. The equivalent
circuit model for fall-time estimation is shown in Fig.
which shown a constant discharge current.

• the rise time τr corresponds to time taken by

Vout to reach Vdd (apprx.) so that

Making similar assumptions we may write for fall-time:

 • From τf and τr , we can deduce
• However µn and µp are not same, But µn =
2.5µp and ßn = 2.5 ßp. so that the rise-time is
slower by a factor of 2.5 when using minimum
size devices for both 'n' and 'p’.
• The analytical models used above for the
estimation of rise and fall-times are
adequate enough to get optimistic
results. However, they do not consider
certain factors affecting the rise and fall-
times such as,

• we would need to make WP = 2.5Wn and for

minimum size lambda-based geometries this
would result in the inverter having an input

capacitance of 1 Cg (n-device) + 2.50 Cg(p-

device) = 3.50 Cg in total In order to achieve
symmetrical operation using minimum
channel length.
 Driving Large Capacitive Loads

• For driving large capacitive loads, inverters This situation can be improved by using N
should present low pull-down and pull-up cascaded inverters, each one of which is
resistances. This, in turn means that MOS devices larger than the stage that it follows by a
must be designed with low L : W ratios to have width factor f as shown in Fig. where
low resistance values for Zp.u and Zp.d nMOS inverters are taken as an example.
• For this, channels must be made very wide to
reduce resistance value which in consequence
makes the inverter occupy a larger area.
• Another limitation on L is that it cannot be
reduced below the minimum feature size
which makes L : W ratio large.
• Hence the gate region area L x W becomes
significant and a comparatively large
capacitance is presented at the input.
• This in turn increases time required for
transitions of voltages at the input.
 Super Buffers
• A "super buffer" is a specially designed nMOS drive
circuit that eliminates the basic asymmetry in
ratio-type logic, which is unable to provide equal
amounts of currents during the rising and falling
transitions because of differing Rpu and Rpd .
• An inverting type nMOS super buffer is shown
in Fig, This is how the circuit works.

• A positive going (0 to 1) transition at input Vin turns

on the inverter formed by T1 and T2. With a small delay,
the gate of T3 is pulled down to 0 volts. Thus device T3 is
cut-off.
• However, since gate of T4 is connected to Vin, it is turned
ON and the output is pulled down very fast. For the
opposite transition of Vin (1 to 0), Vin drops to 0 volts.
• The gate of device T3 is allowed to rise to Vdd very
quickly. Simultaneously the low Vin turns-off T4 very fast.
This makes T3 to conduct with its gate voltage
approximating VDD. This gate voltage is twice the
average voltage that would appear if the gate was
connected to the source as in the conventional nMOS
inverter.
• Now, as Ids  vgs doubling the effective Vgs increases
the current and thereby reduces the delay in
charging at the load capacitance of the output. The
result is more symmetrical transitions.
A non-inverting nMOS super buffer circuit is
given in Fig.

• To Gain an idea of the effectiveness of super

buffer designs, we note that the structures
fabricated in 5 µm technology are capable of driving
capacitance of 2 pF i with a rise-time of 5 nsec.
 MODULE 3 : Scaling of MOS Circuits
OBJECTIVES

Microelectronic technology may be characterized in terms of several indicators, or

figures of merit. Commonly, the following are used:
SCALING MODELS AND SCALING FACTORS
• Minimum feature size
• Number of gates on one chip
• Power dissipation
• Maximum operational ·frequency
• Die size
• Production cost.
SCALING FACTORS FOR DEVICE PARAMETERS
Summary of Scaling Effects
 Subsystem Design Processes - General Considerations

• The aim of any practicing VLSI designer is to produce • Improved repeatability - Fewer processes
'better' products with expectations like, are required to be controlled if the complete
system or most of it is realized on a single chip.
• Higher reliability - By having reduced
interconnections, by high levels of system integration • Better performance - This can be gauged in
(more regularity). Interconnections happen to be a terms of speed power product.
weak spot in any system.
• Any scope for reducing
• Lower power dissipation - lower weight and
design/development period - By adopting
lower volume in comparison with most other
suitable design procedures and using design aids,
approaches to a given system.
this can be tried, especially for more complex
systems.
• Lesser cost
In comparison with other approaches meeting the
same requirement. Cost is generally closely related to
quantity being produced. However by adopting co-
operative ventures such as multiproduct wafer (MPW)
and multiproject chip (MPC), cost can be substantially
reduced.
 An Illustration of Design Processes
Documentation of a design may be
• Design processes are basically undertaken
done by different representations
bearing in mind the following rules.
at different stages such as :
1. The process is strictly a top-down approach.
• Stick diagrams
2. The top-down approach dictates that any
• Logic symbols
complex function is possible to be divided into
• Conventional circuit symbols
less complex subfunctions - bottom level
• A combination of stick diagrams
defining the leaf-cells or basic structures.
and circuit symbols as found
3. Layout should ensure that components
convenient at the particular
interacting more frequently -physically in close
stage
proximity otherwise long, high bandwidth
• Mask layouts
interconnects may cause severe problems.
• Floor plans
5. Design should be aimed at minimum
• Block diagrams showing the
interaction between subparts in order to
architecture.
achieve independence of design.
4-Bit Arithmetic Processor

Communication strategy for data path

• These two data ports can be conveniently combined
into a single bidirectional port assuming that storage
facilities exist in the data path. Control signals dictate
the control over functions to be performed by this
port.
Sequence:
1. 1st operand from registers to ALU. Operand is stored
there.
2. 2nd operand from register to ALU and added.
3. Result is passed through shifter and stored in the
register.
4. Hence it requires 3 clock cycles.

Sequence:
1. Two operands (A & B) are sent from register(s) to ALU &
are operated upon, results in S from ALU.
2. Result is passed through the shifter & stored in
registers.
3. It requires 2 clk pulses.
Sequence:
1.Two operands (A & B) are sent from registers,
operated upon, and shifted result (S) returned to another
register, all in same clock period.
2. It does not require any clock pulse

In pursuing this design exercise, it was decided to

implement the structure with a 2 - bus architecture. A
tentative floor plan of the proposed design which
includes some form of interface to the parent system data
bus is shown following fig.
 Design of a 4-bit Shifter

• Any general purpose n-bit shifter should be able to

shift incoming data by up to n-1 place in a right-shift
or left-shift direction.
• all shifts should be on an end-around basis, so that any
bit shifted out at one end of a data word will be shifted
in at the other end of the word, then the problem
of right shift or left shift is greatly eased.
• It can be analyzed that for a 4-bit word, that a 1-bit shift
right is equivalent to a 3-bit shift left and a 2-bit shift
right is equivalent to a 2-bit shift left etc. Hence, the
design of either shift right or left can be done. Here the
design is of shift right by 0, 1, 2, or 3 places.

The shifter must have:

• input from a four line parallel data bus

• four output lines for the shifted data
• means of transferring input data to output lines with any
shift from 0 to 3 bits.
 In this arrangement ,any input can be connected to any or
all the outputs. Furthermore, 16 control signals (swoo -
sw15), one for each transistor switch, must be provided to
drive the crossbar switch, and such complexity is highly
undesirable.

An adaptation of this arrangement - we couple the

switch gates together in groups of four and also form
four separate groups corresponding to shifts of zero,
one, two and three bits.
Which results in a BARREL SHIFTER
 DESIGN OF AN ALU SUBSYSTEM
• Now we undertake the design of the ALU on the next It will be seen that for any column k
subsystem of 4 bit data path shown below
there will be three inputs-the
corresponding bits of the input numbers,
Ak and Bk, and the ' previous carry' -carry
in (Ck - 1). It will also be seen that there
are two outputs, the sum (Sk) and a new
carry (Ck).

• The heart of the ALU is a 4-bit adder circuit

• A 4-bit adder must take sum of two 4-bit
numbers, and there is an assumption that all
4-bit quantities are presented in parallel form
and that the shifter circuit is designed to
accept and shift a 4-bit parallel sum from
the ALU.
Standard adder equations assuming not a ‘look
ahead carry adder’.
These equations may be directly
implemented as And-Or functions or,
most economically,
Sk and Hk can be directly implemented
with Exclusive-Or gates
Adder Element
Standard cells required to be designed for the adder element
Adder element bounding box
• First estimate the bounding box for the multiplexer area
of the adder. Each standard multiplexer cell (Figure 8.6)
is 7λ x 11λ. and there are .16 such elements side by side
'horizontally' and four stacked 'vertically'.

• width for the metal to metal spacings required by

the clock bus passing through the center.

• In the vertical direction we must allow spacings

for the interconnections between the tops of the
multiplexers

• further lOA. for the connection out from Sk and Ck

at the bottom.
4-BIT ADDER ELEMENT
Implementing ALU Functions with an Adder
Adder Enhancement Techniques
 Carry select adder

also referred to as a conditional sum adder-the adder is divided into blocks. Each block is
composed of two adders, one with a logical 0 carry in and the other with a logical 1 carry in.
The sum and carry out generated are then selected by the actual carry in which comes from
the carry out output of the previous block as shown in Figure.
 Optimization of the carry select adder
consider an n-bit ripple carry adder. The
computation time T is given by,
where k1 is the delay through one adder
cell. If we now divide the adder into blocks,
each with two parallel paths, then the
completion, time T becomes
where k2 is the time needed by the
multiplexer of the next block to select the
actual output carry.
For ex..
the n-bit adder is divided into M blocks, and that
each block contains P adder cells in series, and
considering the arrangement of Figure 8.17, we may
see that the completion time T for the overall carry
output signal is composed of two parts:
• the propagation delay through the first block.
• the propagation delay through the multiplexers.
so that,
 Carry Skip(carry bypass) Adders

• Improves on the delay of ripple carry adder.

• The improvement of worst case delay is achieved by using several carry skip adders to
form a block carry skip adder.
• It utilizes advantages of both generation(gk) and propagation(pk).
• Working principle :
1. The adder can be divided into several blocks,
for each block a special circuit is used to detect
the condition , when A and B bits differ
in all bit positions in the block.
(i.e pi =1 for all ‘i’ in the block).

2. The output signal from such a circuit is called

Block propagation signal, if BP signal =1,
then the carry signal entering the block
can bypass it and be transmitted through
a multiplexer to the next block.
 Optimization of the carry skip adder

1.Let k1 denote the time needed by the carry signal to propagate through the adder cell, and k 2 the
time needed for a carry to skip over a block. Further, let us divide the n-bit carry skip adder into M
blocks-each block containing P adder cells.
2. Since, as was the case for the ripple carry adder, the actual computing time depends on the
configuration of the input numbers, the completion time may well be small but may also reach the
worst case.
The total (worst case) propagation delay time T is given by
where,
carry Look ahead adder
Reg expressions
In particular the expression for carry,
 Module 4 – Sub System Design
SOME ARCHITECTURAL ISSUES
In all design processes, a logical and systematic approach is essential. Guidelines may be set out as follows:
 Switch logic is based on the 'pass SWITCH LOGIC
transistor' or on transmission gates.
This approach is fast for small arrays
and takes no static current from the
supply rails. Thus, power dissipation
of such arrays is small since current
only flows on switching.

• The Pass transistor is used as a

switch in relaying the signals. The
path through each switch is
isolated from the signal activating
the switch.
• Switch logic arrangements using basic
OR and AND connections are shown in Fig.
many such combinations of switches are possible
 Pass Transistors and Transmission Gates

Switches or switch logic can be realized either using simple n or p pass

transistors or from transmission gates.

The transmission gates are complementary switches made up of a p-

pass and a n-pass transistor in parallel as shown in Fig.

Simple pass transistors may suffer from undesirable threshold voltage

effects which gives rise to loss of logic levels as indicated in Fig.
• The transmission gate is free from any such degradation of logic levels although it occupies
more area and requires complementary signals to drive it. Also, the ’on’ resistance of
transmission gates is lower than that of the simple pass transistor switches.

• There is one restriction which must be observed when using nMOS switch logic in the way
that no pass transistor gate input must be driven through one or more pass transistors.

• As shown here, the logic levels, logic levels propagated through pass transistors get
degraded by threshold voltage effects. The signal out of the pass transistor T 1 is not a full
logic 1 but rather a voltage that is one transistor threshold below the true logic 1. Hence
this degraded voltage does not permit the output of T 2 to reach an acceptable logic 1 level.
Gate (Restoring) Logic
• In the gate logic, the inverter is the simplest gate on which are
built logic circuits. With this, AND and OR gate arrangements are
possible with CMOS and NAND and NOR for other systems.
Another use of inverters is to complement and restore logic levels
that may have passed through pass transistors and got degraded.
 Inverter
Inverters come in all the CMOS, nMOS and
BiCMOS technologies and the most
commonly used inverter circuit diagrams
along with the inverter symbol and the
corresponding stick and symbolic diagrams
are shown in Fig

Note that the channel length to width ratio

for each mos transistor and/or the nmos the
nmos inverter Zp.u /Zp.d is usually indicated as
shown.
A particular pull-up to pull-down
ratio can be achieved in several
possible ways as shown in Fig
An 8:1 nMOS inverter is considered
here and effect on power dissipation
Pd, area occupied, resistance and
capacitance values due to different
approaches is clearly indicated.
 Two-Input nMOS, CMOS and BICMOS nand Gates
The nMOS (and pseudo-nMOS) L: W ratios should be carefully noted since they must be chosen to
achieve the desired overall Zp.u / Zp.d ratio.

In order to arrive at the required L: W ratios for an

nMOS (or pseudo-nMOS) Nand gate with n inputs,
consider simple circuit model of the gate in the
condition when all n pull-down transistors are
conducting as in following fig.

The critical factor here is that the output

voltage vout be near enough to ground
to turn off any following inverter-like stages,
that is

thus nMOS Nand ratio determination.

 where Zp.d applies for any one pull-down transistor. The boundary condition then is

from which the ratio for nMOS NAND gate is =

the ratio between Zp.u and the sum of all the pull-down Zp.d must be 4:1 (as for the nMOS
inverter). This ratio must be adjusted appropriately.
This ratio requirement and the other aspects pertaining to the nMOS NAND gate
geometry bring out two significant factors

1. nMOS Nand gate area requirements are considerably greater than nMOS inverter, since
not only must pull-down transistors be added in series to provide the desired number of
inputs, but, as inputs are added, so must there be a corresponding adjustment of the length
of the pull-up transistor channel to maintain the required overall ratio.
2. nMOS Nand gate delays are also increased in direct proportion to the number of
inputs added. If each pull-down transistor is kept to minimum size (2λx 2λ), then
each will present at its input, but ..

if there are n such inputs, then the length and resistance of the pull-up transistor must
be increased by a factor of n to keep the correct ratio.
Thus, delays associated with the nMOS Nand are

Where,
n is the number of inputs
τ inv is the corresponding nMOS inverter delay
The alternative approach of keeping Z p.u constant and widening the pull-down
channels has the same effect, since in this case Cg for each pull-down transistor will
be increased to
nMOS, CMOS and BICMOS 2-input Nand gates
Two-Input nMOS, CMOS and BICMOS nor Gates

(c) Stick diagrams (nMOS and CMOS) and symboliC form (BiCMOS)

(a)~(c) nMOS, CMOS and BiCMOS two-input Nor gate.

 • Arrangements for 2 input NOR gates in CMOS, nMOS and BiCMOS are shown in Fig. The
nMOS two-input NOR gate can be expanded for more number of inputs and wherever
possible, it is preferred to the NAND gate.
• The CMOS NOR gate has a pull-up p-transistor-based structure for the logic 1 conditions
and a complementary n-transistor arrangement to implement logic 0 at the output.

Due to this, the already higher resistance of the p-devices is further increased by the
number of devices connected in series. This thus increases the asymmetry in rise and fall
times on capacitive loads.

• Risetime and fall-time asymmetry on capacitive loads is thus increased and there will also
be a shift in the transfer (Vin vs Vout) characteristic which will reduce noise immunity.

• For these reasons, CMOS (complementary logic) Nor gates with more than two inputs
may require adjustment of the p- and/or n-transistor geometries (L: W ratios).
•As already mentioned, the nMOS NOR gate can be expanded to accommodate more
number of inputs.

•Since there are two paths to ground from p.u for two input NOR gate. Hence the ratio
should be like providing any one path to give inverter like structure.

•Thus each 'leg' would have the same ratio as would be in an nMOS inverter. This applies
for any number of inputs.

• An advantage of the nMOS NOR gate is that the dimensions of the pull-up transistor are
unaffected number of inputs incorporated because of which the area occupied by the NOR
gate is quite reasonable making the NOR gate as fast as the corresponding inverter.
 Comparison of CMOS and BiCMOS Logic

1. CMOS logic supports technology scaling i.e lower supply voltage and large number of
transistors on chip. But technology scaling is not possible in bicmos.

2. BiCMOS inverters offers several advantages in applications like high current sinking and
sourcing compared to CMOS inverters.

3. BiCMOS cricuits are free from latchup problems (due to parasitics ---- +ve or –ve
spikes).
 Pseudo-nMOS logic

• Clearly, if we replace the depletion mode pull-up transistor of the

standard nMOS circuits with a p-transistor with gate connected to
Vss, we have a structure similar to the nMOS equivalent.

• Structure In which(b) a pseudo-nMOS inverter is being driven by

another similar inverter, and we consider the conditions necessary
to produce an output voltage of Vinv for an identical input voltage.

• As for the nMOS analysis, we consider the conditions for which

Vinv = Vdd /2

• At this point the n-device is in saturation (i .e. 0 < Vgsn -Vtn < Vdsn)

• p-device is operating in the resistive region (i.e. 0 < Vdsp < Vgsp –V
tp )
equating currents of n-transistor & the p-transistor, and by suitable rearrangement, we
get

with We obtain

A transfer characteristic, Vout vs Vin can be drawn and, as

for the nMOS case, the characteristic will shift with
changes of Zp.u./Zp.d. ratio.
• the ratio obtained indicates that pseudo nMOS consumes lesser area when compared
to nMOS. And,

• pseudo nMOS offers large resistance and thus it has about 60% lesser power consumption.

•Due to large resistance in pull up network the delay get increases (about 70%) compare
to nMOS.
Dynamic CMOS logic

The actual logic fig(a)is implemented in the

inherently faster nMOS logic (the n-block)

 for the non-time-critical

a p-transistor is used
precharging of the output line 'Z' so that the output
capacitance is charged to VDD during the OFF period of
the clock signal . During this same period the inputs
are applied to the n-block and,

the state of the logic is then evaluated during the on

period of the clock when the bottom n-transistor is
turned ON.
As we know and observed that single phase dynamic
logic structures cannot be cascaded
However, this limitation can be overcome by
utilization of MULTIPHASE CLOCKING for four
phase clocking. As shown in which the actual signals
used are the derived clocks
, and as illustrated in Figure.

The basic circuit of Figure (a) is modified by the

inclusion of a transmission gate as in Figure (c), the
function of which is to sample the output during the
'evaluate‘ period and to hold the output state while
the next stage logic evaluates.

For this strategy to work, the next stage must operate

on overlapping but later clock signals
A Parity Generator

A circuit is to be designed to indicate the

parity of a binary number or word.
A little reflection will readily reveal that the
requirements are:

A suitable arrangement for such a cell is given in stick

diagram form in Figure (a) (nMOS) and 6. 18(b) (CMOS)

The circuit implements the function.

 FPGA BASED SYSTEM

A FPGA is a programmable logic device

which supports implementations of relatively
large logic circuits. • The building blocks of
FPGA are :
1. Logic cells (LCs) grouped into configurable
logic blocks (CLBs)
2. I/O blocks
3. Programmable interconnects.
1. Logic Cells : Each logic block is an FPGA
typically has a smaller number of inputs and
outputs.
• The most commonly used logic block is a
lookup table (LUT), which contains storage
cells that are used to implement a small logic
function.
• Each cell is capable of holding a single logic
value, either 0 or 1. The stored value is
produced as the output of the storage cell.
• where the size is defined by the number of
inputs.

• Two Input LUT

shows the structure of a small LUT. It has two

inputs, it has 2 inputs x1 and x2 and one o/p ‘f’
• It is capable of implementing any logic function of
two variables. Because a two-variable truth
table has four rows, this LUT has four storage
cells. One cell corresponds to the output
value in each row of the truth table.
• Similarly, for all valuations of x 1 and x2, the
• The input variables x1 and x2 are used as the logic value stored in the storage cell
select inputs of three multiplexers, which corresponding to the entry in the truth
depending on the valuation of X1 and X2, select table chosen by the particular valuation
the content of one of the four storage cells as the appears on the LUT output.
ouptut of the LUT.

• The arrangement of multiplexers in the LUT

correctly realizes the function f.
• When x1= x2 = 0, the output of the LUT is
driven by the top storage cell, which
represents the entry in the truth table for x 1 x2 =
00.
 Three Input LUT
It has eight storage cells because a three-variable
truth table has eight rows.

Some FPGAs, usually have extra circuitry, besides

LUT in each logic block.

Fig. 4.6.4 shows how a flip-flop may be included in an

FPGA logic block.

When a circuit is implemented in an FPGA, the

logic blocks are programmed to realize the
necessary functions and the routing channels are
programmed to make the required
interconnections between logic blocks.
 I/O Blocks

• Each bank can be configured individually to support a particular I/O standard

• Allows the FPGA to work with device using multiple I/O standard.

• FPGA can actually be used to interface between different I/O standards.

• Modem FPGA output signals with fast edge rates requires termination to prevent
reflections and maintain signal integrity.

• High pin count package cannot accommodate external termination registers.

Thus a Digitally Controlled Impedance (DCI) is employed.

• DCI eliminates the need for external register and improves signal integrity.
 Programmable Interconnect
A programmable switch matrix form the heart of interconnect in a FPGA.
The actual switching matrix employed is a structure of six pass transistors
per cross point.

Types of connections

1) Single lines : Used to connect a CLB to
another CLB is one hop way. These wires
have to go through a programmable switch
hence add delay.
2) Double lines : These wires travel past two
CLB before hitting the switch, hence they
provide shorter delays for longer connections.
3)Long lines : Wires in long groups do not go
through any programmable switch at all,
instead they travel all the way across or down
a row or column and are driven by tri-state
drivers.
4) Global clock lines : These lines are
optimized for case as clock inputs to the CLB,
providing short delay and minimal skew(clock
skew).
The FPGA has two-input LUTs, and there are four
wires in each routing channel.
The Fig. 4.6.5 shows the programmed states of both
the logic blocks and wiring switches in a section of
the FPGA.
• Programmable wiring switches are indicated by
an X. Each switch shown in blue is turned on
and makes a connection between a horizontal and
vertical wire. The switches shown in black are turned
off.
The truth tables programmed into the logic blocks in
the top row of the FPGA correspond to the
functions
f1 = X1 X2 and f2 = X2 X3

• The logic block in the bottom right of the figure is

programmed to produce
 FPGA Programming
• FPGAs are configured by using the ISP(in SRAM based FPGA
system programming) method.
• The storage cells in the LUTs in an FPGA The SRAM based FPGA uses SRAM cells for following
are volatile, which means that they loose purposes.
- Storing logic value 0 or 1.
their stored contents
- Storing value of Look-up Table (LUT) in logic
blocks.
• Often a small memory chip that - To configure interconnection of FPGA.
holds its data permanently, called a - Reprogramming of SRAM is possible.
programmable read-only memory - The SRAM based FPGA uses one or two way
(PROM), is included on the circuit switches and multiplexers for defining paths.
board that houses the FPGA(volatile)
Fig. shows six pass transistors that allow any
combination of connections of the four wires.
• SRAM cells may be used to control the state of
these pass transistors, which can establish
connections between horizontal and vertical wires
(N, S, E, W). When T1 is ON, it makes connection
between N and W wires.

An SRAM memory cell consists of five transistors as

shown in Fig.

• One transistor used for addressing i.e. used to

select the memory cell for programming, four
transistors are used to form two inverters.
• An SRAM cell is reprogrammable and volatile.
• The programming circuitry for SRAM elements
must include the addressing and data registers.
• SRAM FPGAs do not have routing architectures
for which there is a programmable element at
nearly intersection.
Antifuse base FPGA
• Devices based on antifuse technology are one
time programmable. An antifuse initially provides
insulation between two conductors, but when
sufficient programming voltage is applied across
it, conducting path forms.
• It is one time programmable, once an antifuse
is blown it can not be removed.
• There exists two classes of antifuse technology.
1. Poly-diffusion antifuse
2. Metal-metal antifuse
1- Poly-diffusion antifuse :
• An oxide nitride dielectric
normally prevents current from
flowing between diffusion and poly-
silicon layers.
• When programming pulse is
applied the dielectric melts and a
circuit formed between the diffusion
and poly-silicon.
2. Metal-metal antituse :
• The link is an alloy of tungsten
titanium and silicon. Usually the
conductive link is formed at the corner
or at via where the electric field is
highest during programming.
 Antifuse Element

• Fig. 4.6.8 shows an unprogrammed antifuse element and programmed antifuse

element.
• In an amorphous silicon based FPGA, two
layers of metal are separated by amorphous
silicon, it provides electrical insulation.

• A programming pulse of 10V to 12 V

and of necessary duration can be applied
across the via. It creates a bidirectional
conductive link between two metals.

• The programmable elements can . be placed

very densely. Once programmed, an antifuse
element cannot be erased or reprogrammed.
Features of Antifuse based FPGA
Difference between SRAM & ANTIFUSE FPGA

1. Highest density
2. Lowest switch resistance
3. Very low capacitance
4. Non-volatile
5. Radiation hard
6. Software is easy to place
and route.
 Module 5
Memory,registers, aspects of system timing, testing and verification
SYSTEM TIMING CONSIDERATIONS
 SOME COMMONLY USED STORAGE/MEMORY ELEMENTS

Some important factors for assessing storage/ memory elements are :

• Area Requirement
• Estimated dissipation per bit stored;
• volatility

The Dynamic Shift Register Stage

One method of storing a single bit is to use the shift register approach
Layout of nmos shift register cell
Area:
This calculation applies to an nMOS design, as in Figure, with buried contacts .
Allowing for the sharing of VDD and GND rails between adjacent rows of register cells, area of each bit
stored will require.

Dissipation:
For CMOS circuits, dynamic power consumption Pd is given by

Where, m is the duty cycle, CL is effective load

capacitance and f is the clock frequency.
Volatility:
Data is stored by the charge on the gate capacitance of each inverter · stage, so that data
storage time (without refresh) is limited to 1 msec or less.
 A Three-transistor Dynamic RAM Cell
An arrangement which has been used in RAM (random access memory) and other storage arrangements is
set out in Figure
1. Dynamic : Must be refreshed(re
energized) periodically.
2. Volatile : Loses data when power is
removed.

Comparing with SRAM

Static RAM(SRAM) is faster and less
volatile than Dynamic RAM(DRAM), but
it requires more power and is more
expensive.
This utilize a single transistor as storage device and
one transistor each for RD and WR operation.

When control line RD is LOW,

Then a bit may be read from bus through T 1 by
making WR to HIGH this in turns WR to LOW through
T2.

The bit value is stored by gate capacitance (Cg) of T2

while RD and WR are LOW. by making WR to HIGH.

To read the stored bit, it is only necessary to make

RD HIGH and the bus will be pulled down to ground
through T3 and T2 if a 1 was stored, otherwise T2 will
be non conducting and the bus will remain HIGH due
to its pull-up arrangements .
A One-transistor Dynamic Memory Cell

It is one of the approaches to reduce the area

per bit requirements.

consists of a capacitor Cm which can be charged

during 'write' from the read/write line, keeping
the row select line HIGH.

The state of the charge Cm can be read

subsequently by detecting the state of the
charge via the same read/write line with the row
select line HIGH again, and a sense amplifier of a
suitable nature can be designed to differentiate
between a stored 0 and a stored 1.
 A One-transistor Dynamic Memory Cell
• This is an approach which reduces area/bit
• It consists of capacitor Cm and pass transistor. The circuit arrangement and
stick diagram is shown in Fig a & b. Write operation
• The capacitor Cm will be charged when Read/Write =
1 and Row Select = 1
• If the Read/Write line is provided with logic 1, Cm will
be charged to logic 1 and,
• If the line is provided with logic 0 charge stored will
be logic 0.

Read operation

• If logic 0 is stored in Cm and when Row select line is

high M1 is ON. Then,
•The sense amplifier at the bit line will sense and give
the output as logic 0
• If logic 1 is stored in Cm and when Row select line is
high M1 is ON, the logic 1 stored will begin to discharge
as the path exists.
•The sense amplifier senses this and this gives the
output as logic 1
 Pseudo-static RAM/register cell
•This is a memory cell which combines high storage capability of DRAM and ease of use of SRAM.
• It can be used as SRAM as no external refreshing circuit is required and also used as a DRAM having built-in refresh
logic.
•This is a static storage cell which will hold data indefinitely. This is achieved by storing bit in 2 inverters with
feedback. This feedback is used to refresh the data in every clock cycle.

• ϕ1 and ϕ2 are mutually exclusive clock signals, WR

and RD signal coincides with ϕ1 signals
•When ϕ1 is high and WR = 1, transistor T1 is ON and
data is charged/stored on Cg (gate capacitance) of
inverter. ---WRITE operation
•When ϕ1 is high and RD = 1, transistor & the data
stored at inverter stage is made available at the
output and also the compliment. Thus data is READ at
the output.
•When Φ2 = 1, T3 is ON. The output is read and
feedback i.e., refreshed (reading and
storing back the data). The gated feedback path from
output of T2 is fed to the input of T1
The pseudo static memory cell can also be implemented
using transmission gate (TG).
▪ The cells here include both n type and p
type transistors and are intended for CMOS
systems.

• Both the dynamic and static elements uses

2 bus per bit arrangement so that the bit is
available in both normal and compliment
form on bit and bit’ bus

▪ Prior to reading and writing operation of

the data, the buses are precharged to VDD or
logic 1.