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Layout Dependent Effect: Impact on device performance and reliability in

recent CMOS nodes

Conference Paper · January 2016

DOI: 10.1109/IIRW.2016.7904894

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 Reliability Compact Modeling approach for Layout Dependent Effects in
advanced CMOS nodes
C.Ndiaye1, 2, R. Berthelon1, 3, 4, V. Huard1, A.Bravaix2, C. Diouf 4, F. Andrieu 4, S.Ortolland1, M. Rafik1, R. Lajmi1, X. Federspiel1,
F. Cacho1
1
REER/STMicroelectronics – 850 rue Jean Monnet 38926 Crolles, France
2
ISEN REER-IM2NP, UMR CNRS 7334, Pl. G. Pompidou, 83000 Toulon, France
3
CEMES-CNRS, 29 Rue Jeanne Marvig, 31055 Toulouse, France
4
CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 4, France
Corresponding author: Tel: + 33(0)438923487; email: cheikh.ndiaye@st.com

Abstract
In this paper, we have analysed and modelled the layout
dependent effects (LDE) found in pMOSFET transistors from
14nm UTBB FDSOI CMOS technology. Experiments show that
changing the layout has a clear impact on threshold Voltage
(Vth), under NBTI reliability and on Ring Oscillator (RO)
Frequency drift. Compact models taking account the impact of
LDE on Vth, NBTI reliability, and on RO frequency are
proposed. Measurement data are fitted with a new compact
model showing that the obtained results are in very good
agreements with the modelling.
Key-words: Layout effects, compressive strain, FDSOI, CMOS
performance, NBTI damage
Introduction
width dependence between symmetrical and asymmetrical
layout effect on time-zero performance and under Negative-
Bias-Temperature Instability (NBTI) degradation where we
have developed an accurate compact model to describe the strain
effects, that is further extended to the case of Multi-finger
structures in section 4. Finally, we determine in section 5 a useful
methodology to combine a performance gain under strain effects
and reliability control in high performance Ring-Oscillators
designed from a 14nm Fully Depleted Silicon On Insulator
(FDSOI) CMOS node at high temperature.
Gate
SA SB
(a) LOD
DRAIN
SOURCE

Length of active
(c) Multifinger
With the continuous scaling down of CMOS technologies in
order to follow Moore’s law, MOSFET device parameters
become more sensitive to the Layout Dependent Effects (LDEs) (b) width ratio SA1 SB1

[1], [2], [3]. Threshold voltage (Vth), transconductance (gm) and SA1=SB1=980nm SA1=80nm SB1=980nm
DRAIN

linear and saturation drain currents (IDLin, IDsat) of MOSFET can

T1 T1
be affected by the layout effect which induce additional device W1 W1 SOURCE
variability and a critical issue in modern analog and mixed- T2 W2 T2 W2
SA3 SB3
signal circuit designs [4], [5]. Next to device’s performance, SA2=SB2=80nm
SA2=SB2=80nm
NBTI and HCI degradation induce circuit aging that is also Symmetric case Asymmetric case
impacted by the LDE [1], [6]. For this reason, LDE became an
urgent demand to guarantee sufficient design margin while
improving the reliability at MOSFET level up to circuit level. Fig. 1: Illustration of layout dependency Effect studied in this
work, (a) length of diffusion, (b) Width ratio and (c) Multi-finger
effects.
In this paper, some of LDE like the impact of the length of
oxide diffusion (LOD) also called SA/SB variation, non- 1. Device Process
rectangular layout (width ratio) and the numbers of Finger Devices used in our study of Layout Dependent Effect
(Multi-finger) are investigated (Fig.1). Compact models for (LDE) were fabricated at STMicroelectronics Company. These
fresh Vth and NBTI degradation of pMOSFET that reproduce are pMOSFETs fabricated in 14nm Ultra-Thin Body (UTB) –
experimental data for each kind of layout configuration are FDSOI node which are composed of a dual work-function gate-
developed based on a physical mechanical behavior model first High-K Metal Gate (HKMG) integration, on a 6 nm-thick
proposed in [7]. The impact of LDE on Ring Oscillator (RO) dual SOI/cSiGe film with a 20nm (tBOX) thick-oxide (BOX) and
operation is also investigated and an accurate compact model is a dual in-situ doped SiGeB for N/P raised source-drain on
proposed. channel. Gate stack processing and the corresponding gate
After a short presentation of the technology tested in this chemical composition were previously detailed in [8].
study (section 1), we start by the study of the Length of Oxide
Diffusion (LOD) effect in section 2. Section 3 focusses on the

978-1-5090-6641-4/17/$31.00 ©2017 IEEE 4C-4.1

 A model of the mechanical strain is established by using
the stress model developed in [7]. The following model,
equation (1) is proposed by Bertholon [9] to explain the strain
along the active length (lac):

( , )= 1 − exp − + 1 − exp (1)

with σ0= 2GPa is the initial level of stress from cSiGe channel
and SiGeB, x is the position along the active length lac, α and β
are fitting parameters. A compact model of compressive strain
taking into account SA and SB variations is now proposed by
extending equation (1) to the relationship:

Fig. 2: PMOS transistor TEM cross-section in 14nm UTB- ( , )= 1 − exp − + 1 − exp − (2)
FDSOI CMOS technology.

The strained-SiGe channel (cSiGe) and SiGeB for source-drain with Lg= 20nm the effective length of the transistor.
are used to enhance pMOS performance thanks to the intrinsic
mechanical strain. cSiGe is realized before Shallow Trench
2,5
Isolation (STI) patterning. The strain is measured by Nano-

Longitudinal Mechanical Stress σ (GPa)

Beam Diffraction (NBD) technique and it is observed in Fig. 3
that the strain tends to relax at the edges of the film. 2,0

1,5
Strain measured after STI brick
0.4
Strain ε xx m easured by NBD [% ]

1,0

0.0 Relaxation SA=59nm

0,5 SA=80nm
SA=149nm
-0.4 α=0.124 SA=239nm
0,0 SA=419nm
β=104nm SA=950nm
-0.8 0,0 0,2 0,4 0,6 0,8 1,0

Fully strained Si0.75Ge0.25 Relative Position along the active

-1.2
-1.6
0 100 200 300 400 500 600 700 800
Distance from STI [nm]
Fig. 3: Strain is relaxed on active edge after STI formation as
measured by NBD.
Fig. 3 plots the strain distribution from the NBD scan along the
SiGe channel assuming 25% of Germanium in this film. We can
see that the strain is relaxed and the relaxation increases as the
transistor gets closer to the active edge (or STI) while it
decreases far from the STI, inducing an increase in mechanical
strain.
2. Length of Oxide Diffusion: (LOD)
LOD reflects the distance from the channel to the stress
source, i.e. the gate-to-STI distances on active that are called SA
and SB effect. LOD variations are directly linked to the active
volume available on which the compressive strain is applied, as
well as the distance between the active edge and the channel
center due STI formation-induced strain relaxation.
Fig. 4: Stress value along the active position modelled for
various SA with λ= 104nm and α= 0.124
Fig. 4 plots the longitudinal mechanical stress of the relative
position along the active. The strain value is taken at the middle
of the channel (x= SA+Lg/2), which is an approximation for
short channels (Lg= 20nm). Fig. 4 shows that longitudinal
mechanical stress decreases with the decrease of SA value. This
strain reduction is due to the strain relaxation explained before.
However, LOD might enhance/degrade the channel mobility and
the threshold voltage (Vth) of NMOS/PMOS transistors, but the
threshold voltage of nMOS devices does not depend on SA/SB,
because the n-channel is not stressed, especially by the STI [9].
Contrary to nMOSFET, Vth in PMOS is impacted by the LOD
effect. A Vth modelling as a function of LOD variation (SA/SB)
parameters is established by using the proposed stress model. It
can be described by two terms, a first one without strain
dependence and a strain dependent part as expressed in (3).
( , )= ( = 0) + . (3)
where S0 is the stress sensitivity (S0= 130mV/GPa) and σ is the
strain factor proposed by the modelling in equation (2).
Experimental data are reproduced by the model and for different

4C-4.2
increased stress time from T0, T1 to T2 as shown in Fig.5. we observe that the NBTI degradation modelling (lines)
reproduces accurately the experimental data. With respect to the
Vth (SA, SB) dependence proposed in (3), NBTI degradation
-0.10
modelling can be described by equation (4) below:
T0
model(T0)
-0.15 T1
∆ ( , )( ) = ∆ ( = 0)( ) + ∆ ( ). (4)
Threshold Voltage Vth(V) @ time

model(T1)
T2
-0.20 model(T2)

-0.25 with ∆Vth (σ= 0) the NBTI drift of PMOS device without strain
-0.30 and ∆S(t) the drift of stress sensitivity under NBTI damage. The
-0.35
decrease of Vth degradation (∆Vth) in PMOS under NBTI stress
with the increase of SA/SB values (Fig.6) is due to stress
-0.40
Vth(σ=0) sensitivity (S) that increases with stress time in Fig.7.
-0.45

-0.50 PMOS
150
14FDSOI
-0.55 Stress Sensibility Variation under NBTI stress tests
W=170nm & Lg=20nm 148
-0.60

Stress Sensibility S (mV/GPa)

0 200 400 600 800 1000 146
SA=SB(nm) 144

142

Fig. 5: Threshold voltage Vth as function of SA/SB for 140

symmetric layout. Experimental data (labels) are compared to the 138

modelling (solid line) for various times T0 < T1 < T2.
136
No NBTI
In Fig.5, we can see that the threshold voltage of PMOS device 134
impact PMOS
14FDSOI
decreases with the increase of SA/SB values. The variation of 132 W=170nm & L=20nm
the LOD impact is more important for low SA and there exists a 130
SA value that limits the Vth increase with SA/SB. According to 0.00102
1E-3
0.00104
00.00106
0.00108 10 100 1000 10000 100000

Berthelon, the Vth shift of the active length reduction is mainly Stress Time (s)
due to the modification of strain into the channel transistor.
Strain from SiGe can be compressive biaxial and may become Fig. 7: Mechanical Stress sensibility used in the modelling
uniaxial for short SA/SB value depending on the device type. To with (4) increases for reproducing NBTI degradation (125°C).
highlight the LOD effect on PMOS reliability, NBTI tests are
performed on PMOS transistors and a compact model is The variation of stress sensitivity (S) with time under NBTI
proposed. AC NBTI stressing has been carried out at 125°C with damage can be defined with a power-law in time (5):
VG= -2V and a 50% duty cycle was applied on PMOS devices
( )= . (5) with n= 0.012 for this case
with various SA/SB values. The threshold voltage shift ∆Vth vs.
SA = SB values is given in Fig.6 for different stress times. We
can see that ∆Vth is strongly dependent on the SA/SB value and These statements can now allow us to predict the NBTI
that the Vth drift is higher for low SA/SB values than larger degradation of PMOSFET transistor, by considering the LOD
SA/SB values. effect that strongly impacts the device performance and the end-
of-life of digital circuits.

3. Non-rectangular active- area layout (width ratio)

60
VGstress=-2V shift Vth Experiments(T1)
shift Vth model (T1)
T1=100s shift Vth Experiments(T2)
shift Vth model(T2)
In the design of standard cells, it is possible to find non-
T2=1000s
50 shift Vth Experiment (T3)
rectangular active layouts. For this kind of layout (Fig. 1(b)), the
NBTI Degradation ΔVth(mV)

shift Vth model(T3)

T3=3000s
extension length (SA) in the X direction can be different along
∆Vth(σ=0)

40 the channel width (in the Y-direction) and the level of stress in
such non-rectangular active area is more complex to determine.
30 We have studied the layout effects in such configurations
between symmetrical case and non-symmetrical case Fig.1 (b)
20
with respect to the (poly gate) position. Vth is impacted by the
PMOS
14FDSOI
width ratio (Wratio) and can be also modelled. The threshold
W=170nm & Lg=20nm voltage Vth of PMOSFET can be modelled by using 2 sub-
10
-200 0 200 400 600 800 1000 transistors (T1, T2) in parallel whereas changing the width ratio
SA=SB(nm) means to change the SA/SB values. The weight of each sub-
transistor varies with the jog-ratio which is defined as
Fig. 6: Dependence of NBTI degradation in pMOS devices Wratio=W2/ (W1+W2). We propose a compact model extending
which worsens with reduced SA value. Experiments (labels) and the work developed in [9] with relating:
modelling (lines) are compared under stressing at 125°C.
( , ) ( , )
( )=− − + − (4)
From the model of fresh Vth initially extracted for SA = SB
condition, a NBTI degradation model is determined. In Fig.6,

4C-4.3
with W=W1+W2 the width of the PMOS transistor and SS is the (4) that we now relate to NBTI degradation (ΔVth) into the
subthreshold slope extracted from linear drain current giving an channel. This is expressed as follows:
average value SS= 80mV/dec. In this proposed model, any
shared strain level at the limit between T1 and T2 transition is ( )=− −
∆ ( , )
+ −
∆ ( , )
(5)
not considered as the strain between both transistors remains
very small. Vth is extracted in the subthreshold regime because
SS is found independent of mechanical strain. Experimental where ∆Vth (SA, SB) is obtained from the LOD NBTI
results and modelled data are compared in Fig.8 and Fig.9, for degradation model expressed with (4). With that proposed
symmetric and asymmetric cases, respectively. compact model we see that it accurately reproduces
experimental results in Fig. 10 and Fig. 11. We can notice that
NBTI degradation increases with the increase of Wratio because
of the decrease of the SA and SB values. Then, we can conclude
-0.16 Vth Exp W1+ W2= 170nm that NBTI degradation can be reduced by decreasing Wratio.
Vth Model
Fresh Threshold Voltage Vth(V)

-0.18 SA1=SB1=980nm
T1 W1
-0.20 45
Y
X
T2 W2 W1+ W2= 170nm
-0.22 ΔVth Exp
SA2=SB2=80nm ΔVth model
42

NBTI Degradation ΔVth(mV)

-0.24 Symmetric case

-0.26 39 VGstress=-2V
PMOS Tstress=3000s
-0.28 14FDSOI
Lg=20nm
36
-0.30
0.0 0.2 0.4 0.6 0.8 1.0
Wratio=W2/(W1+W2) PMOS Symmetric case
33
14FDSOI
Fig. 8: Data of Vth measurements (labels) vs. modelling (solid Lg=20nm
line) as a function of width ratio for symmetric case in PMOS devices. 30
0.0 0.2 0.4 0.6 0.8 1.0
Wratio=W2/(W1+W2)

Vth Exp Fig. 10: Model and experiments under NBTI (125°C)
-0.16
degradation in pMOS plotted as a function of width ratio in the
Fresh Threshold Voltage Vth(V)

Vth Model W1+ W2= 170nm

-0.18 symmetric case.

-0.20

Assymmetric case 40
-0.22
W1+ W2= 170nm
SA1=80nm SB1=980nm ΔVth Exp
NBTI Degradation ΔVth(mV)

-0.24 ΔVth Model

38
T1 W1
-0.26 PMOS
T2 W2 14FDSOI
36
-0.28 Lg=20nm
Assymmetric case
SA2=SB2=80nm
-0.30
0.0 0.2 0.4 0.6 0.8 1.0 34
Wratio=W2/(W1+W2)
VGstress=-2V
32 PMOS Tstress=3000s
Fig. 9: Vth vs. width ratio for PMOS transistors with
14FDSOI
asymmetric case; experiments (labels) vs. the modelling (line)
Lg=20nm
30
0.0 0.2 0.4 0.6 0.8 1.0
In Fig. 8 and Fig. 9, we can see that the compact model in (4)
Wratio=W2/(W1+W2)
accurately reproduces experimental data for symmetrical and
asymmetrical case. Absolute value of the threshold voltage Vth
increases with Wratio for both symmetric and asymmetric cases.
Fig. 11: Experimental data (labels) and model (solid lines) of
The |Vth | increase is due to the decrease of gate-to-STI distance NBTI degradation as function of width ratio for PMOS transistor in
with Wratio, as this later impacts the values of SA and SB, and asymmetric case.
consequently the threshold voltage in 20 nm length PMOSFET.
4. Multi-Finger structures
SA and SB values are impacted with Wratio, so NBTI degradation
might be impacted, and this effect needs to be studied. A NBTI In standard cells design, several transistors can be built
degradation compact model is proposed in this paper for on a same active area. Multi-finger MOSFET’s are different
symmetric and asymmetric layout topology cases modelled by transistors in parallel (Fig. 1(c)) and designed on the same active
area, sharing source and drain nodes. In this layout, each gate
finger exhibits different extension lengths SA/SB (Fig. 1(c)).

4C-4.4
Depending on the number of fingers (N) on the transistor, the
impact of strain relaxation is thus different for each gate finger.
45
Multi-finger effect has a clear impact on threshold voltage Vth Shift_Vth Experiments
that can be modelled by using LOD dependence (section 2). The Shift_Vth model
compact model that enables to evaluate the Multi-finger impact 40

NBTI Degradation ΔVth(mV)

on Vth is established by using similar methodology as in (5)
extended to N fingers: Vgstress=-2V
35 Tstress=3000s
( , )
( )=− . [ ∑ − ] (6)
30
Data for 14nm FDSOI node in PMOS (Lg= 20nm, W= 170nm)
are compared (Fig. 12) to the compact modelling for fresh values
(T0) and after T1= 1000s of NBTI stress. 25 PMOS
14FDSOI
Lg=20nm & W=170nm
-0.20 20
measure (T0) 0 3 6 9 12 15 18 21 24
model (T0)
measure (T1) Number of Fingers
model (T1)
-0.25
Threshold Voltage Vth(V)

Fig. 13: NBTI degradation in pMOS Multi-finger structures

-0.30
-0.35
PMOS
14FDSOI
Lg=20nm & W=170nm
-0.40
0 3 6 9
Number of Fingers
Fig. 12: Threshold voltage Vth as a function of Multi-fingers.
Experimental data (Labels) are compared to the modelling (solid line)
for two stress times T0 and T1.
We can see that we have same impact (Fig. 12) of multi-Finger
effect on threshold voltage (Vth) like LOD effect. This means
that PMOS |Vth | value increases with the decrease of the number
of fingers due to the reduction of SA/SB values. This also points
out that the Vth of the whole structure is more impacted by the
nearest transistor to the STI with the large |Vth | increase.
Another advantage of increasing the finger number N in the
Multi-finger structure, is that NBTI degradation becomes also
reduced with N when measurements are carried out at longer
stress time (ts = 3000s) as shown in Fig.13.
at 125°C reduces with the number of fingers N. Data (labels) vs.
VGstress=-2V
modelling (solid line).
T0=0s
T1=3000s
The compact model of NBTI degradation for Multi-Finger effect
is proposed by using a NBTI compact model similar to the LOD
effect established in section 2. The study of Layout Dependent
Effect (LDE) must be considered for a better modelling of
device performance and reliability at transistor level but it has to
be compared to dynamic environment for a more realistic
12 15 18 21 24 reliability determination. The impact of LDE in circuit is
consequently studied in Ring Oscillators (RO) that we now
discuss in the following.
5. Impact of LOD on Ring Oscillators (RO)
LDE on elementary circuits as ROs is of primarily
importance for circuit-layout optimization with respect to
electrical response stability, performance and reliability. To
study the LOD impact (SA/SB variation) on circuits, Ring
Oscillators design based on connected inverters are built-up with
different SA/SB values. Topology and NBTI reliability are
distinguished in two steps, first with the impact of SA/SB values
on RO fresh operating frequency ( f ) and then, on the frequency
drift ( Δf / fo ) under NBTI (AC) stressing. A compact model for
RO operation is considered by the contributions of PMOS and
NMOS sides and SA, SB impact by equating (7):
( , ) ( ) ( , ) ( )
= ( )
+ ( )
(7)
, ,

where the Vth shifts are expressed with respect to their value
without strain (Vthn, p (σ= 0)) and C1, C2 are fitting parameters
for N and P-channel devices, respectively. Even though the
impact of LOD in NMOS transistor is very small [10], we must
accurately take into account the effect on electron mobility (µn)
that is initially higher than hole mobility (µp), but uniaxial strain
in PMOS UTB-FDSOI shows a significant hole mobility
enhancement [1,11], that we observe in IOn value (IDsat (Vdd,
Vdd)), and peak gm. Experimental results and the modelling are
compared for fresh frequency RO variation in Fig.14 and for RO
frequency drift under NBTI stressing in Fig.15 after ts= 100ks
AC operation.

4C-4.5
 1200 2.8
RO fresh frequency Experiments
Model SA=80nm
1000 2.4 SA=149nm
RO Fresh Frequency (MHz)

SA=239nm
SA=419nm
800 2.0 Vdd: 1V0 1V0 0V8 0V7

RO Normalized Iddq
Frequency: ref +22% +50% +76%
Vdd=0.8V 1.6
600

1.2
400
RingOscillator 1.0
14FDSOI 0.8
Lg=20nm & Wn=Wp=170nm
200
0.4 RingOscillator
0 100 200 300 400 500
14FDSOI
SA=SB(nm)
0.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
Fig. 14: RO fresh frequency increases with SA=SB value. RO Normalized Frequency
Model (lines) compared to experiments (Labels) at T=125°C.
Fig. 16: RO leakage vs. frequency trade-off showing that
higher SA / SB values enable greater RO operating frequency (T=
5 125°C) for a fixed limited leakage.
Experiments
model
RO Frequency Drift (%)

4
3 Vddsens=0.8V
2
RingOscillator
14FDSOI
1 Lg=20nm &Wn=Wp=170nm
0 100
Fig. 15: AC experiments using NBTI Stressing (Vdd= 1.5V) at
T= 125°C measured by RO frequency drifts at Vddsens= 0.8V, (Labels),
compared to the model (lines) with SA, SB variations.
As shown in Fig. 14, increasing SA/SB values leads to better
performance on RO because RO fresh frequency is strongly
increased when SA/SB values are increased. At the same time
RO frequency drift (Fig. 15) under NBTI stressing (125°C) is
reduced, due to the higher strain into the channel. With the Vth
and NBTI models of SA/SB variation proposed above, the
compact model used for the combined effects of RO fresh
frequency and NBTI-induced frequency drift with (7) is
proposed to match the AC RO results. In order to evidence the
benefit of LOD effect in Fig.16, fresh frequency of RO designed
with different SA/SB values is first measured at different supply
voltages Vdd= 1V, 0.8V and 0.7V. The nominal Vdd for this 14nm
FDSOI CMOS node is 0.8V. Vdd=1 V is intentionally chosen
here as the reference, because it first combines an accelerated
NBTI stressing condition that can be mitigated by the strain level
by SA variation and by Vdd lowering at high temperature.
Measurements show that we can have different Vdd/SA coupled
parameters that give the same frequency. These results allow us
to investigate the advantage of using SA/SB variation for speed
and leakage optimization at the circuit level as proposed with
Fig.16, that we detail below.
Fig.16 shows RO normalized static current (Iddq) with respect to
Tstress=100ks
its reference value (at Vdd= 1V) as a function of the
Vddstre=1.5V
corresponding RO normalized Frequency in RO designed with
various SA/SB values. Frequency and leakage currents in RO
with different SA/SB are measured for the different supply
voltages Vdd. LOD design clearly shows experimentally a
benefit of Δf / fo =+ 22% at a fixed leakage at Vdd=1V for SA=
SB= 149nm, which moves up to +76% for SA= SB= 419nm
while Vdd is reduced to 0.7V. This points out that the combined
200 300 400 500
effects of strain (Fig. 14) and NBTI damage reduction (Fig. 15)
SA=SB(nm)
allows to enhance RO performance under high temperature
stress. This further confirms that the highest strain level see the
smallest NBTI effects which can be further enhanced under a
lower temperature. This is in agreement with previous work [12]
that observed such effect related to Through Silicon Vias (TSV)
proximity. These results illustrate that LOD effect provided by
the compressive strain, is a new powerful tool to perform
dynamic management of digital products. This can be performed
under an accelerating NBTI stressing condition at high
temperature through the balance between performance and
reliability. This can be useful for the optimization of future high
performance CMOS node as a function of layout dimensioning
at the cell level.
Conclusion
We have experimentally reviewed the impact of some Layout
Dependence Effects (LDE) on devices, circuit performance and
reliability at high temperature. Several layout configurations as
length of oxide diffusion, variable width, symmetric and non-
symmetric active variations, and as a function of finger number
in Multi-finger structures have been studied in 20nm effective
gate-length transistors, fabricated with 14nm UTB-FDSOI
CMOS technology node. Compact modelling has been
developed for each layout configuration that accurately
reproduces experimental results of initial characterizations and
reliability robustness encountered in device and Ring
Oscillators. With this analysis, we have demonstrated that LDE
impacts devices that is reported to digital circuits and can be
strong depending on the topology. These effects cannot be

4C-4.6
neglected for modelling circuit electrical performance and
layout transfer. These results are helpful for design optimization
of CMOS technologies by a proper sizing of nanoscale circuits
dedicated to very high performance, low consumption, and low
voltage operation.

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