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Oxide Edge Trap Density Extraction in Silicon

Nanowire MOSFET from Tunnel Current Noise
Measurement in Gated Diode like Arrangement
Deepak K. Sharma and, Arnab Datta

Abstract—Edge traps in the gate oxide of silicon nanowire

MOSFETs have been extracted from tunnel current noise
measurement in a gated diode like arrangement. We have found
that, low frequency noise in tunnel current results from collective
response of the edge traps available within the gate oxide
surrounding band-to-band generation (BTBG) region of silicon
nanowire, and when the BTBG region is accessed by favorable
terminal biases. From detail modeling of the phenomenon, we
derived a closed form expression of the tunneling current noise
power spectral density (PSD) employing which oxide edge trap
density in nanowire MOSFET had been extracted through its fit
with the experimental noise PSD data. We furthermore validated
our model for different BTBG biases, and contrasted our result
with the bulk oxide trap density in identical MOSFET, while the
latter was separately estimated from the gate current noise PSD
measurement. Mismatch between the oxide bulk trap and edge
trap concentrations has been found, whereby actual edge trap
density remains otherwise hidden from the widely employed gate Fig. 1. Experimental scheme of noise measurement in gated diode like
current noise measurement technique. It is because, the present arrangement of silicon nanowire MOSFET. Source terminal was open in all
measurements including tunnel current
scheme improves the resolution of the extracted oxide edge trap
concentration in surrounded gate MOSFET owing to constricted
tunnel current flow near the corner of the gate which imposes
selectivity on the oxide edge traps
the fringe capacitance, the same should also be directly
Index Terms— Silicon Nanowire FET (SNWFET), Noise, Oxide influenced by the edge traps in the gate oxide, whereas process
Traps induced edge traps in the gate oxide is expected to remain
higher over the traps available in the rest of the oxide over
I. INTRODUCTION MOSFET channel. The oxide edge traps are necessarily bulk
Silicon nanowire field effect transistor (SNWFET) is traps, but the difference is that, their spatial inclusion is
considered to be a potential MOSFET technology to continue limited only at the corner of the gate. In fact, presence of
CMOS scaling beyond the sub 22 nm technology node [1]-[6]. oxide edge traps was felt from random telegraph noise (RTN)
Because of the surrounded gate structure, the devices offer signal in planar MOSFETs [13]-[14], but direct extraction of
improved electrostatics over the bulk planar MOSFETs. its concentration in the gate oxide had never been made,
However, due to narrow diameter of the silicon nanowire, neither that in silicon nanowire MOSFET till date. In this
unwanted parasitic elements similar to the scaled bulk planar context, floating body structure of advanced MOSFETs (e.g.,
MOSFET can become the roadblock to improving the circuit as in surrounded gate silicon nanowire) does not allow one to
performance [7]-[10]. The dominant ones are the inner and realize the well-known charge pumping (CP) experiments to
outer fringing capacitances which join the gate to the source profile oxide edge trap. Furthermore, CP does not guarantee
and drain regions. In earlier investigations, their overall having reliable trap profile in the gate insulator especially
contribution in nanowire MOSFET had been determined to be when it contains non-uniform edge traps, as earlier reported
~40 % [11]-[12], which is substantial, hence should not be for charge trap flash (CTF) memory [15]. Low frequency
overlooked. In addition to the obvious dimension impact on noise (LFN) measurement on the other hand shows promise to
assess oxide traps in nanowire MOSFETs [16]-[17]. But, no
exhaustive LFN technique and model for oxide edge trap
The authors are associated with the Department of Electronics and profile extraction in surrounded gate nanowire MOSFET has
Communication Engineering, Indian Institute of Technology (IIT), Roorkee,
Uttarakhand – 247 667, India. Email: (arnabfec@iitr.ac.in), Tel: +91 – 1332 – been developed so far. In this context, we conceived the idea
285464 of tunnel current noise measurement in nanowire MOSFET

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especially in its gated diode like arrangement aiming to extract and positive respectively with respect to their common ground
oxide edge trap concentration. (i.e., common supply ground), so that field lines join gate to
For discussion, the paper has been organized as follows. drain through p-silicon nanowire. Thus, in principle, biasing in
SECTION – II discusses experimental detail in the context of the latter is similar to the gated diode connection of planar
noise measurement in gated diode like SNWFET. SECTION – MOSFET.
III discusses modeling of related LFN PSD and on the Fig. 2 shows measured tunnel current (IT) in an n-SNWFET
extraction method of oxide edge trap concentration, followed gated diode. IT is suppressed when VG = VD, but, as expected,
by conclusion in SECTION – IV. it increases with a negative increment of VG. We will
subsequently see that, for the said biasing to the nanowire
band-to-band generation (BTBG) is expected near the gate
14 edge from the drain, which results I T because of the expected
current continuity. Noise measurements were performed with
similar BTBG biases [gate current noise measurements were
12 performed by applying fixed overdrives on the gate (G)
leaving source (S) and drain (D) grounded]. Fig. 3(a)-(b) show
S
normalized noise current power spectral densities (PSD) ( 2I )
10 IT
in silicon nanowire gated diode for various VG and with the
IT(× 10 ) [A]

fixed VD, where 1/f behavior can be observed at the lower

8 frequency, which should be due to the trapping and de-
trapping of carriers to and from the oxide edge traps,
-8

6
-2 -2
10 10
(a) (b)
4 10
-3
1.6 10
-3
1.6
-4 1/f -4 1/f
10 10
SI/I T (1/Hz)

2 ILEAK -5 -5
10 1/f 10 1/f
-6 -6
10 10
2

0 10
-7
10
-7

-3 -2 -1 0 1 2 3 10
-8
SYMBOL - EXPT. 10
-8

-9 LINE - MODEL -9
VG [V] 10 1 10 100 1000 10 1 10 100 1000
f (Hz) f (Hz)
Fig. 2. Measured tunneling current (IT) of the n-silicon nanowire field effect
transistor (SNWFET) under two terminal gated diode like arrangement (VD =
2V). Junction leakage (ILEAK) is obtained when VG = VD

II. EXPERIMENTAL DETAIL
Measurements were taken on the devices fabricated at Institute
of Microelectronics (IME), Singapore. Nanowires used in our
experiments were n-channel (NA = 1×1017/cc), and
individually having 15 nm diameter (T Si), 500 nm gate length
(LG) and 3.5 nm gate oxide thickness (TOX) (SiO2). Current-
voltage (IV) and, noise measurements were performed in
Keithley 4200 semiconductor parameter analyzer, and
Keysight 35670A dynamic signal analyzer (DSA) with
Stanford Research Systems (SRS) low noise current pre-
amplifier (SR570) stages, respectively. Experimental scheme
of noise measurement in gated diode like arrangement of
silicon nanowire MOSFET is shown in Fig. 1. In actual gated
diode experiment on planar n-MOSFET, p-body is connected
to the supply ground which serves as the voltage reference,
gate is connected to the negative bias (with respect to the p-
body at supply ground) and drain to the positive bias (with
respect to the p-body at supply ground). In case of nanowire
MOSFET the biases connected to gate and drain are negative
Fig. 3. Normalized noise current power spectral density (PSD) (data is shown
as is including 50 Hz harmonics from power supply) as measured in gated
diode like arrangement of SNWFET (SYMBOLS) for: (a) VG = -2 V, (b) VG =
-3 V (in both cases VD = 2 V was applied), respectively. Model fits (LINE) are
shown for the same biases. Slow convergence to the Lorentzian slope
(frequency exponent = 1.6) at the higher frequency side results due to
dominant edge traps available at a narrow access length near the gate edge,
extracted later
respectively. Moreover, we measured instrumental noise (not
shown here) accounting the effect of background noise and
noted its negligible contribution to the distinctive noise feature
found at the measurement bias.
III. MODELING OF TUNNEL CURRENT NOISE PSD AND OXIDE
EDGE TRAP DENSITY EXTRACTION
We modelled the observed LFN behavior of the IT using linear
superposition of PSDs from uncorrelated edge traps available

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within the gate oxide. It is well known that, individually they into channel) around the nanowire. The cone should have its
cause RTN, PSD of which can be written as [18]:
IT 2 fT (1 − fT )τC
SRTN = 4a2 ( )
A [1 + (ωτC )2 ]
(1)

BTB GEN. RATE (cm s )

‘a’ is the single electron blocking area (blocking radius is

-3 -1
TOX/2). ‘A’ is the area through which IT flows, and fT is the 15
(a)
10

LBTB

GATE EDGE
10
10
0.19 0.20 0.21

z (m)

0.6
(b)
0.0

-0.6
E(eV)

Fig. 4. T-CAD simulated BTB generation rate near the gate edge from the
drain for VG = -3 V, and VD = 1 V (in gated-diode like SNWFET), which
shows steady fall in carrier concentration from the gate edge near the drain -1.2 EC BTB
until the LBTB inside channel (INSET) EV
-1.8 GATE EDGE
CHANNEL
trap occupation function, which can be written in terms of -2.4
Fermi-Dirac (FD) distribution function. Trap time constant 0.15 0.20 0.25
(τC) is related to the depth of the trap in oxide (r) over the z (m)
silicon nanowire by,
τC = τ0 eαr
(2) Fig. 5. (a) 1-D line cut of T-CAD simulated BTB generation rate, which once
rotated along the nanowire (from the gate edge into channel) one can obtain
the carrier availability cone as described in the text, used for PSD
τ0 is the characteristic time constant, and α is the tunnel representation, and (b) Energy band diagram for the applied bias as mentioned
attenuation co-efficient. in Fig. 4 (caption)
To have PSD of LFN from Eqn. 1 it is important to understand
(lateral) height as LBTB and have Δ (= TSi/2 + δ) its base radius,
how trapping occurs near the gate edge of the nanowire
with δ being the maximum tunneling depth of carriers into the
MOSFET in its gated diode like biasing arrangement, for
oxide. We can hence state without ambiguity that, noise effect
which we may refer to a typical BTBG contour as shown in
due to carrier trapping in gate oxide near the drain edge of the
Fig. 4, as simulated in our device. From the color tones of it
nanowire should not necessarily be treated as a problem in
we can infer that BTBG is non-uniform around the gate edge
plain cylindrical co-ordinate (where r and z are independent),
(near drain), which decays towards the channel. Line plot
rather it can be correctly represented by integrating the RTN
shown in Fig. 5(a) demonstrates the variation of actual BTBG
PSD function over the cone describing carrier availability in 3-
over the length (LBTB) [follow the direction of carrier flow out
D. The total noise current PSD (SI) thus can be written in the
of the BTBG in the simulated band diagram shown in Fig.
following integral form (ΦB is the oxide barrier height),
5(b); (arrow)]. As carrier trapping into the oxide is directly
related to the number of available carriers inside channel, 2π Δ LBTB ΦB
hence it should have similar variation to that of the BTBG,
and, in 3-D carrier availability within small z can be SI = ∫ ∫ ∫ ∫ SRTN NT (E)dErdzdrdθ
represented by a cone inscribed by the annular rotation of the θ=0 r=0 z=(LBTB )r E=0
Δ
BTBG spatial variation line of Fig. 5(a) (from the gate edge (3)

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The PSD expression in Eqn. (3) can further be divided into I with respect to the same energy reference is also likely.
and II [in II, NT(Ef) is the oxide edge trap density centered at However, it is the dominant edge traps at a narrow access
the Ef], and we have, length causing a slow roll over in the Lorentzian tail at the
SI higher frequency side of the PSD [20], which can also be
TSi⁄ observed from the experiments (see, Fig. 3). Now, ignoring
2π 2 LBTB ΦB
T
= ∫ ∫ ∫ ∫ S̃(τ, E) dErdzdrdθ the higher order terms of r [since,(∆ − Si) ≤ TOX ] in the
2
θ=0 r=0 L integration of II, SI can further be simplified as,
⏟ z=( BTB )r E=0
Δ SI
τmax
I τ
2π Δ LBTB
2 T
I 2 2πLBTB ln( c⁄τ0 )
IT 2 τC = [4a ( ) kTNT (Ef )] ( ) . ∫ dτ
+ 4a2 ( ) kTNT (Ef ). ∫ ∫ ∫ rdzdrdθ A α2 [1 + (ωτC )2 ] c
A [1 + (ωτC )2 ] τc = τmin
θ=0 r=TSi⁄ z=(LBTB )r (5)
⏟ 2 Δ
II τmin and τmax are the oxide edge trap time constants for r =
TSi/2 (near interface) and r = Δ (bulk oxide), respectively.
Integrating-by-parts the integral relation in (5), we further

Fig. 6. (a) Schematic representation of the Gaussian surfaces used for writing Eqn. 11, and, (b) graphical solution of LBTB as obtained from Eqn. 11 (with VD = 2
V). LHS and RHS are the left hand side and the right hand side of Eqn. 11, respectively. NUM is the numeric value

(4) obtain,
τmax
I arises from the silicon nanowire itself due to expected τ
ln( c⁄τ0)
stochastic generation-recombination (g-r) (S̃) within the ∫ dτ
[1 + (ωτC )2 ] c
narrow space charge region. However, our specific interest τc = τmin
here is to model the superseding 1/f noise spectrum, because
expected small variance of g-r of carriers within a small length 1 τ
= [tan−1 (ωτmax ) ln( max⁄τ0 )
of silicon nanowire will not contribute to it [19]. Moreover, ω
BTBG rate at the silicon band is faster than the trapping rate at ωτmax
the oxide. Hence, for determination of 1/f response, PSD tan−1 (ωτC )
contribution from I can be ignored. − ∫ d(ωτC )]
ωτC
Integration over trap energy (E) in II had been carried out ωτmin
considering dominant oxide edge traps that reside near the (6)
Fermi energy level, though non-uniform edge trap distribution

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Since, the first term in the square bracket of (6) is greater than Line integral of Ẽ(z = 0) is sufficient to fix voltage at z = 0
tan−1 (ωτC ) plane of nanowire, because of the same heavy doping of the
the area under [ ], thus, we arrive at the following
ωτC LEXT residing immediately next to it. Taking into account both
simplified PSD expression of the tunnel current noise resultant VD and VG, ETOP can be expressed as,
from the edge traps in the oxide, which requires LBTB for its VDG − 1.1
evaluation. ETOP = ( )
3TOX
2πa2 IT 2 (13)
SI = ( ) LBTB kTNT (Ef )δ
αf A For the given dc biases in experiments we found that, E TOP
(7) favors direct tunneling (DT) current through the gate oxide.
For the fixed bias LBTB had been extracted from simultaneous So, δ was fixed at the classical turning point of DT, which is
analytic solution of Poisson’s equation and Gauss relation in the farthest scanning depth of oxide edge traps.
nanowire. For the given bias arrangement, electrostatic field Fig. 6(b) shows graphical solution of LBTB which was used
E(r, z, θ) inside the nanowire (z>0) within the LBTB can be with α = 1.52×1010/m in the main noise PSD model, we
written using the depletion approximation as: derived earlier. Now, for VG= -2 and -3 V Figs. 3(a) – (b)
∂E E 1 ∂E ∂E qNA respectively show modelled normalized noise PSDs. From the
+ + + = −
∂r r r ∂θ ∂z ϵs ϵ0 best fitting between experiment and model, oxide edge trap
density was calculated as, 8×1020 – 1.55×1021/cc-eV (note
(8) that, molecular density of thermal SiO2 is ~ 2×1022/cc,
NA and εS are the channel doping density and relative indicating inferior edge oxide quality of silicon nanowires),
permittivity of silicon, respectively. Though we take depletion which shows at least 1 - 2 order increase in the concentration
approximation here, but soon we will see that it closely from the oxide mean bulk trap density concentration (found
reproduces LBTB. Now, if we symbolize the oxide tunneling between 2.3×1019– 3.5×1019/cc-eV); the latter was extracted
̃, then Eqn. (8) at r = TSi/2
field at r = TSi/2 and for all θ as E from the same device by the existing gate current noise PSD
including the z variation of E ̃ can be re-written in the (SIG) measurements [18] [see, Fig. 7(a) – (b)]. In fact,
following simplified form: difference between the two trap densities caused because of
̃
E dẼ qNA having abrupt interface of the gate oxide near the S and D of
+ = − the narrow diameter nanowire. Hence, for oxide trap density
TSi⁄ dz ϵs ϵ0
2 extraction in surrounded gate MOSFET, our scheme can
(9) supplement the gate current noise PSD measurement and it
The above linear differential equation was integrated with the
2z⁄
integrating factor (IF): e TSi , and we reached the following -6 -6
closed from relation of E ̃ after employing the boundary 10 10
̃ = 0, at z = LBTB+; as in reality for (a) (b)
condition at z =LBTB+ (i.e. E -7 -7
10 10
z> LBTB BTBG holes are not available, source end is open and
SIG/I G (1/Hz)

holes till LBTB screen the field due to VD, all of it causes oxide -8 -8
10 10
tunneling field to reduce),
qN T 2
(L
̃ = − ( A ) ( Si ) [1 − eTSi BTB −z) ]
E 10
-9
10
-9
2

ϵs ϵ0 2 1/f 1/f
-10 -10
(10) 10 10
LBTB was derived from the simultaneous solution of Eqns. (10)
-11 -11
and, (11), where the latter can be written by matching the 10
10 100 1000
10
10 100 1000
electrostatic fluxes around the Gaussian surfaces (z = 0 -, LBTB+
f (Hz) f (Hz)
and, r = TSi/2+) which enclose the depletion charges as shown
in Fig. 6(a). dS1 and dS2 are the differential surface elements
of the surfaces S1 and S2, and ESIDE and ETOP are the fields
entering the surface S1 (z = 0-) and, leaving the surface S2 (r = Fig. 7. Normalized gate current (IG) noise current power spectral density
(PSD) (SIG/IG2) as measured in same SNWFET by applying (a) 0.57 and (b)
TSi/2+), respectively. No field can leave the remaining surface 0.77 V uniform overdrives to the gate (G) while tying up S and D terminals
(S3), since source terminal was left open. together (GND) (i.e., two terminal MOS capacitor); Here 50 Hz peaks are
qNA T 2 eliminated
−ESIDE ∯ dS1 + ETOP ∯ dS2 = − ( ) . π ( Si⁄2) LBTB
ϵs ϵ0
(11)
ESIDE at z = 0- can be written as follows, which remains can isolate edge traps from the oxide bulk traps. In fact,
constant over the drain extension length (L EXT = 5 nm), resolution of the edge traps has been found more in gated
because of heavy extension doping of our devices (N DEXT = diode like measurement because of having narrow access
1×1019/cc). length of the gate by the carriers. However, we found that
[VD − E ̃(z = 0). 2π (TSi )] depth profiling of edge traps is challenging with the scheme,
ESIDE = 2 ⁄
LEXT as BTBG requires high VG and VD thus it limits trap scanning
(12) near the classical turning point in oxide, which eventually

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results in a weak shift in PSD with V G as can be seen from [14] J-W. Lee, C. H. Park, H. Shin, B-G. Park and, J-H. Lee, “Accurate
extraction of ΔI / I due to random telegraph noise in gate edge current of high-
Fig. 3.
k n-type metal-oxide-semiconductor field-effect transistors under
accumulation mode,” Applied Physics Letters, vol. 98, pp. 023505-1-023505-
IV. CONCLUSION 3, 2011
[15] P. B. Kumar, P. R. Nair, R. Sharma, S. Kamohara and, S. Mahapatra,
To summarize, the present work discusses an oxide edge trap “Lateral Profiling of Trapped Charge in SONOS Flash EEPROMs
density extraction method in silicon nanowire MOSFET from Programmed Using CHE Injection,” IEEE Transactions on Electron Devices,
tunneling current noise measurement in a gated diode like vol. 53, no. 4, pp.698-705, 2006
arrangement. Besides the experimental scheme, we have [16] N. Cle´ment, X. L. Han and, G. Larrieu, “Electronic transport
mechanisms in scaled gate-all around silicon nanowire transistor arrays,”
devised a methodology to analyze experimental data. A radical Applied Physics Letters, vol. 103, pp. 263504-1-263504-5, 2013.
difference between the edge trap concentration and oxide bulk [17] P. Singh, N. Singh, J. Miao, W.T. Park and, D. L. Kwong, “Gate-All-
trap concentration has been found which must be taken into Around Junctionless Nanowire MOSFET With Improved Low-Frequency
account while assessing the lateral trap density distribution in Noise Behavior,” IEEE Electron Device Letters, vol. 32, no. 12, pp. 1752-
1754, 2011
the gate oxide of surrounded gate nanowire MOSFET. [18] F. Crupi, G. Giusi, G. Iannaccone, P. Magone, C. Pace, E. Simoen and,
C. Claeys, “Analytical model for the 1 ∕ f noise in the tunneling current
ACKNOWLEDGEMENT through metal-oxidesemiconductor structures,” Journal of Applied Physics,
The authors sincerely thank Dr. Navab Singh, Institute of vol. 106, 073710-1-073710-6, 2009
Microelectronics (IME), Singapore, for the fabrication of [19] F. Pascal, S. Jarrix, C. Delseny, G. Lecoy and, T. Kleinpenning,
‘Generation‐recombination noise analysis in heavily doped p‐type GaAs
silicon nanowire MOSFETs used in our experiments, and Dr. transmission line models,” J. Appl. Phys., vol. 79, no. 6, pp.3046-3052, 1996
Sanjeev Manhas, Department of Electronics and [20] J.W. Lee, W.S. Yun, and G. Ghibaudo, “Impact of trap localization on
Communication Engineering, IIT – Roorkee, India, for his low frequency noise in nanoscale device,” J. Appl. Phys., 115(194501), 2014
encouragement. The work has been funded through the grant
received from SERB-DST, India (SR/FTP/ETA-0124/2013)
Deepak Kumar Sharma received
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