IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO.
5, MAY 2006
High-Performance Fully Depleted Silicon Nanowire
(Diameter ≤ 5 nm) Gate-All-Around CMOS Devices
N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar,
G. Q. Lo, N. Balasubramanian, and D.-L. Kwong
Abstract—This paper demonstrates gate-all-around (GAA)
n- and p-FETs on a silicon-on-insulator with ≤ 5-nm-diameter lat-
erally formed Si nanowire channel. Alternating phase shift mask
lithography and self-limiting oxidation techniques were utilized to
form 140- to 1000-nm-long nanowires, followed by FET fabrica-
tion. The devices exhibit excellent electrostatic control, e.g., near
ideal subthreshold slope (∼ 63 mV/dec), low drain-induced bar-
rier lowering (∼ 10 mV/V), and with ION /IOFF ratio of ∼ 106 .
High drive currents of ∼ 1.5 and ∼ 1.0 mA/µm were achieved
for 180-nm-long n- and p-FETs, respectively. It is verified that the
threshold voltage of GAA FETs is independent of substrate bias
due to the complete electrostatic shielding of the channel body.
Index Terms—CMOS-compatible process, gate-all-around
(GAA), silicon nanowire transistor, surround gate, wrap-
around-gate.
I. I NTRODUCTION
F OR NANOSCALE CMOS, various nonplanar device
structures have been explored for better gate electrostatic
control of the channel potential [1], [2]. Among the many
innovative approaches, double-gated FinFET [3], [4], tri-gated
[5], Π-gated [6], Ω-gated [7], nanowire body [8]–[11], and gate-
all-around (GAA) [12]–[14] MOSFETs have attracted much
attention. As the name suggests, the GAA FET features the gate
fully surrounding the channel body and thus providing the best
possible electrostatic control [12]–[16]. The reduction in chan-
nel width and thickness can further increase the effectiveness
of the gate control. Therefore, an ultrathin and narrow body
(nanowire) MOSFET, when combined with the GAA structure,
is deemed to be a major candidate for extreme CMOS scaling
provided the process complexities such as fabrication of short
wires and the gate definition under the body are solved.
Besides theoretical studies [15], [16], there have been several
experimental attempts (although several of them suffer in gate
definition) that demonstrated the advantages of GAA, or near
GAA devices, e.g., relaxed body thickness yet gaining similar
short-channel control as thin-body double-sided FinFET [7],
[8], excellent transconductance [12], and drain-induced bar-
rier lowering (DIBL) suppression [13]. However, none of the
experimental works demonstrated a complete surrounded-gate
ultranarrow (diameter ≤ 5 nm) lateral silicon nanowire (SiNW)
structure with uniform gate dielectric.
Manuscript received January 5, 2006. The review of this letter was arranged
by Editor B. Yu.
The authors are with the Institute of Microelectronics, Singapore 117685
(e-mail: navab@ime.a-star.edu.sg).
Digital Object Identifier 10.1109/LED.2006.873381
0741-3106/$20.00 © 2006 IEEE
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383
In this paper, by using processes prevalent in conven-
tional CMOS technology, we demonstrate the fabrication of
n-type and p-type GAA FETs on silicon-on-insulator (SOI)
with SiNW of diameter ≤ 5 nm. To define the small length
wires down to 140 nm, we used alternating phase shift mask
(alt-PSM). Although the parasitic capacitance would be large,
to keep low series source/drain resistance and to surmount
the issue of defining the gate underneath the overhanged Si
body, we designed the gate slightly wider than the wire length
[Fig. 1(a)]—similar to the method used in [4] for FinFET.
The fabricated GAA nanowire transistors show the best per-
formance among those reported so far in terms of high drive
current, near ideal subthreshold slope (S.S.), low DIBL, and
high ION /IOFF ratio. The transistors also exhibit a substrate-
bias-independent threshold voltage (Vth ) as a result of the
complete electrostatic shielding of the channel.
II. F ABRICATION OF S I N ANOWIRE AND MOSFET S
8 -(100) silicon-on-insulator (SOI) wafers with a top Si
(p-type, ∼ 1015 /cm3 ) of thickness 200 nm on a 150-nm-
thick buried oxide (BOX) were used as starting materials.
Active areas were patterned and etched down to the BOX
to make 140- to 1000-nm-long 50-nm-wide Si fins between
wider source and drain using alt-PSM lithography in a KrF
scanner and dry etch. Small length fins can be achieved us-
ing advanced lithography tools such as ArF with immersion
and/or by some kind of spacer techniques. Fig. 1(b) shows the
scanning electron microscope (SEM) image of a 1000-nm-long
and 50-nm-wide fin connecting the source and drain regions.
The patterned Si was then oxidized in dry O2 at 875 ◦ C
for 5 h, which due to stress limited oxidation results in two
Si cores (nanowires) [17]—one at the bottom and the other
at the top of the Si fin. The top nanowire was etched out
using dry etching, and the bottom nanowire was released from
the oxide using wet etch process—6-min dip in 1:25 DHF.
The release was followed by 9-nm gate oxide deposition and
130-nm amorphous silicon (α-Si). Fig. 1(c) shows the released
wire after gate oxide deposition. Fig. 1(d) shows the SEM im-
age after α-Si deposition. The α-Si deposition was followed by
gate patterning and etching. To surmount the issue of defining
the gate under the body and to ensure that the gate dry etching
process does not damage the wire in case of misalignment, the
gate was defined with 70-nm overlapping source/drain (S/D)
regions [Fig. 1(a) and (d)]. This overlap increases the parasitic
capacitance but on the other side reduces significantly the
series resistance. S/D and α-Si gate were then implanted using
384
Fig. 1. (a) Layout of the masking layers used in the fabrication process.
(b) Tilt view SEM image of 1000-nm-long, 50-nm-wide, and 200-nm-tall Si
fins after top silicon etch with ends of the fin connected to S/D pads. (c) SiNW
after 9-nm-thick SiO2 deposition. (d) SiNW after 9-nm-thick gate oxide and
130-nm α-Si deposition. The drawn rectangle shows the gate pattern schematic.
(e) TEM image perpendicular to the wire of 200-nm-long nanowire GAA
showing a circular 4-nm-thick wire 9-nm oxide with full coverage by α-Si from
all the sides.
As/4 × 1015 cm−2 /30 keV and BF2 /2 × 1015 cm−2 /35 keV
for n- and p-FETs, respectively. A long S/D activation anneal
(950 ◦ C/15 min) was used to ensure dopant diffusion uni-
formly in the gate α-Si and S/D overlap regions beneath the
gate—reducing the effective channel length. It was followed by
the standard metal contact formation and sintering processes.
Fig. 1(e) shows the TEM cross section of ∼ 4-nm-diameter
SiNW surrounded by a uniform gate oxide and fully doped
poly-Si gate.
III. R ESULTS AND D ISCUSSION
Fig. 2 shows the Id –Vd and Id –Vg plots of nanowire GAA
n- and p-FETs with ≤ 5-nm-diameter 180-nm-long SiNW. The
ON -state Ids of ∼ 1.5 and ∼ 1.0 mA/µm are obtained for n- and
p-FETs, respectively, with OFF-state Ids < nA at an operating
voltage of 1.2 V (|Vgs − Vth | = 0.95 V and |Vds | = 1.2 V).
Considering the volume inversion in the channel [18] and to
facilitate comparison with previous works [4], [7], [9]–[11],
we normalized the current to the diameter of the wire. More
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IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 5, MAY 2006
Fig. 2. Id –Vd and Id –Vg characteristics of ≤ 5-nm-diameter 180-nm-long
nanowire GAA n- and p-FETs. The currents are normalized to the wire diameter
(5 nm). The value shown in volts with each curve in Id –Vd plots is overdrive
(Vg − Vth ).
conservative normalization could be due to the perimeter of the
wire [19]—divide reported current values by π. However, the
normalization does not affect the ION /IOFF ratio and that re-
mains ∼ 106 . In view of 180-nm channel length and 9-nm-thick
gate oxide, the reported drive currents are high and are more
than earlier reports on nanowire transistors [8]–[11]. One can
expect much higher drive currents by further reducing the
channel length and gate oxide thickness.
We estimate the carrier mobility using the standard
MOSFET equation in the linear region: Ids = µC ∗ W/L ∗
(Vgs − Vth − Vds /2) ∗ Vds . The capacitance per unit area “C”
was calculated—which is too small to be measured—using the
formula C = 2ε/{a ∗ ln(b/a)} [20], where a (= 5 nm) and
b (= 23 nm) are the diameters of the nanowire and gate elec-
trode, respectively. The estimated electron and hole mobilities
are ∼ 750 and ∼ 325 cm2 /V · s at high field (|Vgs − Vth | =
1.0 V). High mobilities in nanowire FETs have been reported
previously [10], [21], [22] and can probably be due to one or
more of the following: cylindrical morphology of the channel
body, reduced phonon scattering, strain in SiNW due to the
oxidation process, and volume inversion.
Despite the use of a 9-nm-thick gate oxide, n-FET ex-
hibits near ideal S.S. (∼ 63 mV/dec) and very low DIBL
(∼ 10 mV/V). p-FET also shows low S.S. (∼ 66 mV/dec)
and DIBL (∼ 20 mV/V). These show that the body thick-
ness and GAA feature can play more dominant roles than
gate oxide scaling. This is an advantage of GAA nanowire
devices as oxide scaling becomes one of the limiting factors
SINGH et al.: HIGH-PERFORMANCE FULLY DEPLETED SiNW (DIAMETER ≤ 5 nm) GAA CMOS DEVICES
Fig. 3. ION versus Vth plot for 200- and 250-nm-long channel devices with
wire diameter as ∼ 4 nm. The inset shows the effect of wire length on ION
and IOFF .
for conventional MOSFET. Also, the absence of a kink effect
on the current–voltage (I–V ) curves (Fig. 2) confirms that the
devices are fully depleted and there are no sharp corners on
the body structure. The asymmetry in the threshold voltages
(Vthp > Vthn ) could be because of one or more of the following
differences: confinement effects due to minor differences in
channel diameter, dopants in the SiNW channel, and gate poly
doping (n-FET poly is more heavily doped than p-FET poly).
Fig. 3 shows absolute ION versus Vth plot for 200- and
250-nm-long GAA nanowire n-FETs. A reduction in ION with
increase in channel length as well as with Vth is clearly seen.
The increase in Vth could be due to the confinement effect
caused by reduction or nonuniformity in the wire diameter.
Once normalized, the effect of Vth on ION may disappear, but
it would need TEM on all the measured devices to know the
exact diameter. The inset in Fig. 3 shows the effect of channel
length on ION and IOFF for nanowire GAA n-FET, where
with decrease in channel length ION keeps on increasing until
the lowest fabricated channel length of 140 nm, which is an
indication of nonballistic transport.
Fig. 4 shows the immunity of GAA FETs to the substrate
biasing effects through a plot of Vth against the substrate bias
for n- and p-FETs and corresponding reference planar SOI
MOSFETs. There is no change in Vth for nanowire GAA FETs
with the applied substrate bias from −5 to 5 V (not shown,
no change was found from −20 to 20 V either). As expected,
Vth of the reference devices changed significantly as expected.
These data support the results presented in [22] on multibridge
channel MOSFETs. The immunity of nanowire GAA devices
to substrate bias is a result of shielding of the transistor body by
the gate poly.
IV. C ONCLUSION
We have demonstrated a fully CMOS-compatible fabrication
method for SiNW-based GAA n- and p-FETs. High drive
current and excellent gate control, revealed by low DIBL and
near ideal S.S., were demonstrated in those devices. With
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385
Fig. 4. Substrate bias effect on a GAA nanowire device threshold compared
with a reference planar SOI device on the same wafer. The nanowire GAA has
a channel length of 300 nm, whereas on the reference devices the gate length is
500 nm.
further gate length reduction, one can expect extremely high
drive current from GAA SiNW structures. Besides excellent
electrical performance, these devices are immune to substrate
bias effects.
ACKNOWLEDGMENT
The authors would like to thank the staff of the Semiconduc-
tor Process Technology Laboratory, Institute of Microelectron-
ics, Singapore, for their assistance in wafer processing.
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