Course Content Overview

 MOSFET physics (W1)

 Short channel effect (W2)
 Advanced Devices module:(W2-W5)
 Multi-Gate device structure
 FinFet and Gate all-around
 High-k materials + metal gate
 Strained technology
 Silicide process and RSD
 High mobility Channel
 Process integration (W6)
 Future device candidates (W6)
Gate

Si

Planar FinFET Gate-all-around

1
 High-k/Metal Gate Integration

 Simpler process, but metal gate suffers high-Temp S/D anneal.

Iwai “High-k, Metal Gate, Channel Materials
2
New material integration in CMOS technologies”
 High-k/Metal Gate Integration

 Complicated process, but metal gate is formed after S/D anneal.

Iwai “High-k, Metal Gate, Channel Materials
3
New material integration in CMOS technologies”
 Gate-last, HK-first & HK-last?
HK-first Gate-last:
Metal gate
Poly(dummy)
High-K

High-K

HK-last Gate-last: Both Poly/oxide

Poly(dummy) removed
High-K
Metal gate

 For HK-last, HK does not go through S/D anneal (good for

reliability)
 HK-first gate-last is used for 28nm only, and HK-last gate-last is
4
used from 20nm and onward (i.e. 16nm, 10nm, 7nm, 5nm …)
 HK-first vs. HK-last?
45nm 28nm 20nm 16/14nm 10nm
planar planar FinFET FinFET
Gate-first IBM, Samsung,
GF,
Gate-last / HK-first Intel
Gate-last / HK-last Intel Intel, TSMC, all all
UMC, IBM,
Samsung, GF,

 HK-last has the advantage that the HK film does not go through high-
temperature (>1100°C) S/D anneal.
 Good for HK stack reliabilities (NBTI and TDDB)
 Hole-trapping efficiency↑ for the IL SiON, which is bad for NBTI.

 Gate-last HK-last has become the mainstream baseline since 20nm.

5
 Process Flow for (HK-last) Gate-last
For planar CMOS (e.g. 20nm)

Contact Contact

SiP SiGe

NFET PFET

 In principle, FinFET uses the same HK-last gate-last process

sequence as planar CMOS. Except that the process
complexity is (much) higher, due to the fin topography.
6
 Technology Progression

7
Novel Transistors? -Low-voltage approaches
Goal of scaling: What prevents VDD scaling?
 Extract maximum ION for given IOFF Mobility: sets ION
 Subthreshold swing: sets IOFF
Sub-VT
Swing Device Structure node
(mV/dec)
>80 Planar(HKMG) CMOS ≥20nm

FinFET (GAA), UTB-SOI 16~5nm

80-60
III-V / Ge , 2D channel (TMD),
?
carbon nanotube(CNT)
Tunnel-FET(TFET)
<60 ?
Negative capacitance FET

 Improving Electrostatics (Lower Sub-Vt swing and DIBL)

 Enhance Performance (Increase drive ION, Reduced parasitic )
 Mitigate Variability (Noise, Reliability, Random vs. systematic)
Gate-All-Around Nanowire FET is the limit to MOSFET
Subthreshold Swing Scaling need new transistor options
Ge, III-Vs:
8
Much higher mobility than Si -> ION ↑
 High mobility channels
Several other semiconductors show better mobility than Si
IV-IV III-V
Si Ge InP GaAs In0.5Ga0.5As GaSb InAs InSb

Elec. Mobility
(cm2/V-sec)
1400 3900 5400 8500 12000 3000 40000 77000

Electron m1:0.19 m1:0.082

effective(/m0) m1:0.98 m1: 1.6
0.082 0.067 0.041 0.041 0.023 0.014

Hole mobility
(cm2/V-sec)
450 1900 200 400 450 1000 500 850

Hole effective mHK: 0.49 mHK: 0.33 mHK: 0.6 mHK: 0.51 mHK: 0.45 mHK: 0.4 mHK: 0.41 mHK: 0.43
mass(/m0) mLH: 0.16 mLH: 0.043 mLH: 0.089 mLH: 0.082 mLH: 0.052 mLH: 0.05 mLH: 0.026 mLH: 0.015

Bandgap(eV) 1.11 0.67 1.34 1.42 0.74 0.72 0.36 0.17

Lattice parameter 5.431 5.658 5.868 5.653 5.868 6.095 6.058 6.479
Possible candidate materials with good carrier mobility:
e-: Ge, InGaAs, InAs, InSb
h+: Ge, GeSb, InSb (cross out due to larger lattice mismatch with Si)

 SiO2 is an excellent dielectric, which is the foundation for the Si MOS

technologies, while the corresponding GeO2 is unstable (soluble in water).
 Now people re-new the interest on Ge due to the high mobility for both n & p.
9
 Ge Channel
 Higher mobility than Si for both electrons and holes.
 low doping activation low resistance.

 Bandgap of Ge is much smaller than Si.

Larger off-state leakage.
 Worse MIS Interface quality.
Worse Subthreshold slope.
Undesirable Vt Shift.
Mobility Degradation due to Dit. Ge channel have much
 The Cleaning of Ge Substrate higher mobility than Si.
No standard cleaning procedure
 Lower melting point (~935C)
 Lower breakdown voltage
 Lower resistance to the mechanical stress

10
 Hole Mobility Universality in Ge pFETs
 Short channel (60nm) Ge pFETs with NiGe metal S/D.
 Hole mobility shows 1.8x Si universal.

11 T. Yamamoto et al., IEDM, p1041, 2008.

 FinFET with III-V material or Ge: Fin
Replacement Technique
Selective epi

Challenges of 5nm CMOS Technology 2016 IEDM SC

 Use InP as a “buffer layer” to reduce the strain due to lattice mismatch.
 This technique can be used to build Ge (or SiGe) fins as well.
12
 Ge FinFET using fin replacement technique
Fin pitch down to 45nm L. Witters et al., VLSI Symp. 2015

Challenges of 5nm CMOS Technology 2016 IEDM SC

13  Similar technique can be used to build Ge FinFET (on Si substrate).
 Challenges of using Ge (or SiGe) as
high-mobility channel material
 Gate stack (esp. IL, interfacial layer) on Ge substrate have high Dit (interface
trap) density, and poor N/PBTI (negative/positive bias temperature
instability).
 A proposed solution –deposit a very thin (~1nm) layer of Si on Ge (referred to
as “Si-cap”) so that IL is formed on Si.

 Channel electrons can stay in the Si-cap layer, while due to the EV offset (as shown)
the channel holes remain in Ge this increases the Tox_inv for pMOS by Tsi /3,
which is very undesirable.
 Si-cap-free Ge is back to the main theme… how to form IL on Ge is the key challenge!
 TSMC is using Ge (or SiGe) as high-mobility channel (HMC) material in 5nm FinFET,
14 which is in mass production ! –no publication about the details.
 III-V MOSFET architecture 1:
Implanted Self-Aligned MOSFET

 10 nm HfO2 by MOCVD
 Si I/I + RTA 600°C, 60 s
 Lg=95 nm

15
Lin, IEDM 2008
 III-V MOSFET architecture 2:
MOSFET with Regrown Ohmic Contacts

 15 nm HfAlO by MOCVD
 TaN gate, SiON spacers
 In-situ Si doped InGaAs S/D by MOCVD (635 C, 2 min)
 Lg=250 nm

16
Chin, EDL 2009
 Narrower Bandgap & Carrier Spillover

 Narrower bandgap of higher mobility channel

results in larger leakage current.
 Quantum confinement induced by electric
field (or structure confinement) induces
carrier spillover to lower mobility valleys.
17
 The DOS (density of states) trade-off
for III-V materials
 DOS (density of states) is the no. of states for carriers to reside. Dc(E) is for
electrons, and DV(E) is for holes. This is related to the material properties (energy
band structure). TABLE 1-4 Electron and hole mobilities at room temperature

ℏ2 Ga Si GaAs InAs Ga Si GaAs InAs

Effective mass ≡ 2 2
𝑑 𝐸/𝑑𝑘 m /m 0.12 0.26 0.068 0.023 µ n(cm2/V·s) 39000 2400 8500 30000
n 0

mp/m0 0.30 0.39 0.50 0.30 µ p(cm2/V·s) 1900 470 400 500
TABLE 1-4 Values of Nc and Nv for Ga, Si, GaAs at 300K.

Ga Si GaAs
Nc(cm-3) 1.04x1019 2.8x1019 4.7x1017
8𝜋𝑚𝑛 2𝑚𝑛 (𝐸−𝐸𝐶 )
𝐷𝐶 𝐸 = , 𝐸 ≥ 𝐸𝐶 Nv(cm-3) 6.0x1018 1.04x1019 7.0x1018
ℎ3

𝑊 𝑛 = 𝑁𝑐 𝑒 −(𝐸𝑐−𝐸𝐹 )/𝑘𝑇
𝐼𝑑𝑠𝑎𝑡 = 𝜇𝑛𝑠 𝐶𝑜𝑥𝑒 (𝑉𝑔𝑠 − 𝑉𝑡 )2
2𝑚𝐿
𝑄𝑖𝑛𝑣 = −𝐶𝑜𝑥 (𝑉𝑔 − 𝑉𝑡 )

 For III-V materials (GaAs, InAs), effective mass↓ high mobility.

 Low effective mass  DOS is low (i.e. DOS ∝ effective mass )
 DOS is directly proportional to the free channel carriers
(electrons or holes), or C (Vg-Vt) , or Idsat(or ION)
 Because of this fundamental trade-off, most people shift attention
18 to Ge, instead of III-V material.
 The DOS concern for III-V channel
𝑛 = 𝑁𝑐 𝑒 −(𝐸 −𝐸 )/𝑘𝑇 materials
𝑐 𝐹

𝑄𝑖𝑛𝑣 = −𝐶𝑜𝑥 (𝑉𝑔 − 𝑉𝑡 )

𝑊
𝐼𝑑𝑠𝑎𝑡 = 𝜇𝑛𝑠 𝐶𝑜𝑥𝑒 (𝑉𝑔𝑠 − 𝑉𝑡 )2
2𝑚𝐿
 For III-V channel, we gain the mobility,
but lose charge. InGaAs DOS is smaller than Si
 The net ION gain is quite marginal. by more than one order of
magnitude  Gate capacitance
is reduced by factor of 4!
Challenges of 5nm CMOS Technology
2016 IEDM SC

 EOT is 1nm  III-V FETs show greater performance

than Si.
 EOT is 0.5nm  Because of smaller DOS, the
19 performance of III-V FETs is worse than Si
 Summary: III-V (or Ge) as channel
Potential advantages:
materials
✓ High mobility (small m*) Density of State (DOS)
✓ High injection velocity (small m*)
8𝜋𝑚𝑛 2𝑚𝑛 (𝐸−𝐸𝐶 )
✓ Near-ballistic performance 𝐷𝐶 𝐸 = 3 , 𝐸 ≥ 𝐸𝐶
ℎ
The Trade-offs and Concerns:
• Low DOS and gate cap (small m*)
• Tunneling (small m*) 𝑊
• Source starvation 𝐼𝑑𝑠𝑎𝑡 = 𝜇𝑛𝑠 𝐶𝑜𝑥𝑒 (𝑉𝑔𝑠 − 𝑉𝑡 )2
2𝑚𝐿

 III-V material generally has (very) low DOS due to small m*

 ION ∝ channel charge (= Cox · (Vg–VT) ) ∝ DOS · probability
 Low DOS means low Coxe or channel charge.
 So even if electron mobility µ n in III-V material is very high (e.g. 5,000-10,000 cm/v-
sec, which is 15-30X higher than µ n in Si), the low DOS (and thus low Coxe) makes the
best-case ION of III-V device only about ≤1.5x higher than that of Si.
 Recent publications focus more on Ge or SiGe as alternative channel material. how
to form an IL on Ge is the key !

20
 The Steep Switch

 Below 0.5V Vcc, the threshold voltage does not

scale since sub-threshold slope is limited by
60mV/decade
 Quest for Ideal switch with < 60mV/dec swing for
21 high speed ultra-low power applications
 Inter-band Tunnel Transistor

22
 MOSFETs vs. TFETs

MOSFET TFET

E VG E VG
EC

EF
EF EV
EC

EV
N+ P+ N+
N+
equilibrium x equilibrium x

23
Band diagram for VG= VD= 0
OFF-state: MOSFET
E VG Dominated by
TE thermal emission
IBT over the barrier (TE).
EC HIBL Tunnel currents
FN become important
EV BTBT2 below 10 nm.
Tunneling enhanced
N+ N+ by small bandgaps
x and by small eff
masses.
OFF-state: TFET
𝑛𝑖2 VG
E Dominant leakage
𝑁𝐴 Note: IOFF is determined by
EC I0≈0 current for MOSFET
is suppressed. BTBT (band-to-band
tunneling) current
EV BTBT BTBT currents direct tradeoff with ION!
become important
FN
𝑇∝𝑒 −𝐿 𝑚𝑟∗ 𝐸𝐺 below 10 nm.
L BTBT enhanced by
P+ I N+ small bandgaps and
x by small eff masses.
24
Lundström et al. IEDM 2015
 OFF-state: calculations

SS advantage for TFET

occurs for LG > 8λ
David Esseni, et al.
TED, 62, 3084, 2015

 LG too short would have high tunneling

25 leakage, which degrades the SS.
 ON-state:
V
MOSFET
G
E
T≈1
TE ON current is a
EC thermionic emission, over
the barrier current
EV
Channel transmission
coefficient is about one.
N+ I N+
x

ON-state: TFET ON current is a BTBT

current. This is a fundamental
E
VG issue for all TFET’s.
High On-current BTBT on-current
EC requires small bandgap, almost certainly will be
𝑇 ∝ 𝑒 −𝑊 𝑚𝑟∗ 𝐸𝐺 small eff mass, small lower than the drift
EV BTBT tunneling width. current of a MOSFET !
FN Steepness of turn-on
controlled by source
W
doping, phonon
P+ I N+ scattering, band tails,
x defects, . . .
26
Lundström et al. EDM 2015
 Tunnel Barrier and Width

 Lower band-gap material improves the

tunneling rate and on-current at very
low electric fields and low voltages.
 Narrow bandgap InAs tunnel
transistors show promise in scaling
VDD to 0.25V.

27
 Steep-slope Tunnel-Effect Transistors using III-V
Nanowire/Si Heterojunction
Katsuhiro Tomioka1,2, Masatoshi Yoshimura1 and Takashi Fukui1 1.Graduate School of
Information Science and Technology, and Research Center for Integrated Quantum
Electronics (RCIQE), Hokkaido University, Kita 13 Nishi 8, Sapporo 060-8628, Japan
2.Japan Science and Technology Agency (JST) - PRESTO E-mail :
tomioka@rciqe.hokudai.ac.jp

Drain
BCB Source Gate Drain
n+-III-V nanowire
HfALOx
III-V nanowire III-V n+-III-V
Gate
VG>0
Source SiO2 p-Si
p-Si

Drain Source Gate Drain

BCB p-III-V nanowire
HfALOx
n-III-V nanowire
n-Si
Gate
VG<0
Fig. 10 Experimental transfer
Source SiO2 characteristics of optimized
n-III-V p-III-V
n-Si TFET with a NW-diameter of 30
nm (pink curve) Vps = 0.10 V

 Though not single slope, demonstrated 21mV/dec of sub-VT swing ! (This result is not
repeated in the next 4 years though.)
 On-state (tunneling) resistance needs reduction.  Ion< 10-8A/um is no good !

28 2012 VLSI –Hokkaido Univ.

 TFET Benchmarking & progress
[1] H. Zhao et al, IEEE EDL,
Dec. 2010
[2] M. Noguchi et al., EDM
2013
[3] B. Garipour et al., ACS
Nano, Apr. 2012
[4] D. Sarkar, et al., Nature
Vol. 526, Oct 2015
[5] L Knoll et al., IEEE EDL,
June 2013
[6] A. Villalon et al, VLSI 2012
[7] R. Pandey et al, VLSI
2015

Target region

 Needs much efforts to improve (reduce) SS below

60mV/dec and reach desired on-current.
 Performance remain far inferior to CMOS.
 Drive currents~2 orders of magnitude below Si devices
due to imperfections of tunneling heterojunction-defects
(trap-assisted tunneling) and non-ideal band structure at
29 the junction.
 Transistor Scaling –Modern Scaling
Paths
Single thread performance (1000 x SpecINT)

Modern Scaling
Benefits
Path
# of transistors (thousands)

Strained Silicon Higher channel Mobility

Higher lon@ lower gate
High-k/Metal-Gate
leakage
Improved short channel effect
FinFET
for low power application
SiGe Channel Higher channel Mobility
Standard cell lib and EDA tool
co- optimization with
DTCO
technology for better block
Year of introduction level performance
S. Samavedam et al, IEDM 2020 Based on original data plotted by M. Horowitz,
F. Labonte, O. Shachan, K. Olukotun, L.
Hammond, and C. Batten. Additional data
compiled by K. Rupp

 # of transistors continue to grow but single thread

perf. has plateaued post 2000.
 New technology features were introduced to
continue the performance and transistor density
30 scaling.
 Technology Node Scaling Beyond Dennard

A. Kelleher, Intel Investor Day 2022

Key performance booster post 2000 Strain Si, HKMG, FinFET,

DTCO, PowerVia, RibbonFET
31 （Design-Technology Co-Optimization，DTCO）
 From FinFET to Gate-All-Around FET

GAA benefits over FinFET

 More effective and flexible transistor width per footprint
 Better short channel control over FinFET
 Can leverage current EDA infrastructures
32
C-H Lin, IEDM 2021
 Gate-All-Around/RibbonFET/Nanosheet is
Happening
Intel VLSI 2020 IBM Research

TSMC ISSCC 2021

Samsung IEDM 2018 IMEC

 All major semiconductor companies and institutes are adopting GAA as

33 transistor architecture in the future leading-edge technology
 3D Stacked CMOS (Complimentary FET)
2-D CMOS NR
Inverter

3-D Stacked
CMOS NR Inverter

J. Ryckaert et al, IEDM 2019; VLSI 2018

3-D stacked CMOS enables aggressive cell

height scaling to continue Moore's law.
Flexibility to integrate optimized channel for N
and P drive strength.
Need to consider process complexity,
additional parasitic cap and extraction
34 capability.
 Complementary FET (CFET)
 No area penalty from N-P
space due to stacked
N&PMOS
 Maximized effective width due
to stacked N&PMOS and
stacked NS channel in single
fin arch.
 Options to integrate optimized
channels for N/P
independently by sequential
integration

35 N. Horiguchi, VLSI 2021

 CFET PNR demonstrates CFET logic area
scaling potential

CFET full PNR loop to compare 5T-NS to 4T-CFET.

> 13% area scaling expected.

36 NHigh VLSI 2021

 Review and Summary
 High-k/Metal Gate Integration
 Gate-last, Gate-first, HK-first
 High mobility channels
 Ge channel Transistors
 III-V channel Transistors
 Steep Switch Transistor
 Tunnel Transistor
 Technology Node Scaling Beyond Dennard :
Gate-All-Around/RibbonFET/Nanosheet
Complementary FET (CFET)

Acknowledgement
NCTU Prof. Chao-Hsin Chien, Prof. Ih-Chin Chen
37