Lecture 5: Scaled MOSFETS for ICs

MSE 6001, Semiconductor Materials Lectures

Fall 2005

5 MOSFETS and scaling

Silicon is a mediocre semiconductor, and several other semiconductors have better electrical and
optical properties. However, the very high quality of the electrical properties of the silicon-silicon
dioxide interface allows metal-oxide-semiconductor field-effect transistors (MOSFETs) to be fab-
ricated. These devices have several properties, such as operation frequency and power consump-
tion, that improve as their size is scaled down to smaller dimensions, which also allows more
transistors to be packed onto a chip. The smaller sizes are achieved using higher-resolution pho-
tolithography, which is improved by steadily improving the fabrication technologies. The trends of
steadily improving performance and greater integration density with time are generically refered to
M test vehicle with >0.5 billion transistors
as “Moore’s Law”. Of course, scaling has to end eventually, somewhere before the scale of atoms
all of the features described in this paper
is reached.
ed on this technology. The aggressive de-
or a small 0.57!m2 6-T SRAM cell that is
with high performance logic processing. A
5.1is shown
ell after poly patterning Basic MOSFET
in Figure
o small size, this cell has a robust static
wn to 0.7V VDD to allow low voltage opera-
MOSFETS turn on and off via the non-linear gate capacitor between the gate electrode and the
Figure 14 is a Shmoo plot for theThe
substrate. 70 MbMOSFET of Fig. 1 controls the flow of electrons (an NMOSFET) from the n-type
frequency vs voltage, showing the SRAM
source
GHz at 1.2V. A die photo in Fig- to the n-type drain electrode.
electrode
is shown
A positive gate potential attracts a very thin layer of electrons to the interface of the substrate,
VII.
forming
Conclusion
a “channel” that allows current to be conducted from the source to drain. The gate length
ed an industry leading 65nm CMOS tech- Figure 2: Transistor size trend for technology nodes.
performance microprocessors with excel-
nd interconnect performance, along with
sional scaling. A high performance, high
SRAM test vehicle has been successfully
ng all of the 65nm process features. This
is on track for high volume manufactur-

L = 35 nm
References
al., Symp. VLSI Tech. Dig., 2004.
., IEDM Tech. Dig., pp. 197-200, 2003.

Pitch Thick AspectRatio Transmission electron

(nm) (nm) micrograph of MOSFET,
220 320 - Intel 65 nm process
220 90 -
tch 220 - - Figure 3: TEM cross section of 35nm NMOS
210 170 1.6 P. Bai, et al., “65 nm Logic Technology Featuring 35 nm Gate Lengths, Enhanced
210 190 1.8
Channel Strain, 8 Cu Interconnect Layers, Low-k ILD, and 0.57 µm2 SRAM Cell”,
220 200 1.8
IEDM Proceedings, 2004
280 250 1.8
330 300 1.8
480 430 1.8 F IGURE 1: The MOSFET gate controls the conductivity between the source and drain.
720 650 1.8
1080 975 1.8

tch, thickness and aspect ratio 5-1

10
 r thick buried oxide, there is no
otential,resultinginrelatively
mpared to other device types
re not likely to be used at the
cussed here. We do, however,
f the more novel double gated
erein both the insulator on the
and the Si layer itself are very
nnel are gated. There are also
with buried oxide thin enough
thin enough for use in active Fig. 1. Schematic illustration of the scaling of Si technology by a
eresting from a circuit point of factor alpha. Adapted from [5].
used to dynamically adjust the
cussed here forlack ofspace. Table 1 F IGURE 2: Scaling the size of a MOSFET.
s as follows. Section II ad- Technology Scaling Rules for Three Cases
ndamental limitations
L is thetoseparation
the between the source and drain. The smallest feature that can be fabricated in an
Ts that appear IC to technology
be on the is approximated by the “half-pitch width”, which characterizes the IC technology
fundamental limits,
and is ait measure
may of L. For example, this year 90 nm ICs have been in full production, and 65 nm
wn to very smallchips dimensions,
have been introduced. The thin gate oxide, made from silicon dioxide, has a thickness tox ,
smaller. Sectionwhich
III describes
in the current advanced chips is approximately 2 nm thick.
s fundamental limit regime:
n the more practical world of
are many types5.2 Scaling
of variations
he design of MOSFETs with et al., “Device scaling limits of Si MOSFETs and their application dependencies”,
Figure 2 (Frank,
ok at some of these practical
Proc. IEEE, 2001) depicts the effects of scaling and Fig. 3 tables the resulting changes in transistor
nces for deviceand design. Sec-
circuit properties.
epts of the previousScaling
sectionswill be limited by a number of issues. For a very thin gate oxide, less than about 1
ed to meeting nm, the electrons
needs of can quantum mechanically tunnel directly from the gate electrode to the conducting
The paper endschannel,
in Section VI large leakage currents. For very short channels, electrons can tunnel directly from
giving
s into a large table, followed
the source to drain, for L less than about 5 nm. Some of the smallest transistors made to date have
II. L = 8 nm. Doping becomes a problem, because the random distribution of dopant atoms means
that different MOSFETs have different numbers of dopants and thus different electrical properties.
MITS At the highest doping levels, which can approach 1019 cm−3 , the dopant atom spacing is only about
3 nm.
is the dimensional scaling parameter, is the electric field scaling
nking of MOSFETs has been parameter, and and are separate dimensional scaling parameters for
g [14], [15]. The5.3basic 25
ideanm MOSFET
is the selectivetechnologies
scaling case. is applied to the device vertical dimensions
T is scaled down by a factor and gate length, while applies to the device width and the wiring.
Within a few years, the semiconductor industry expects to produce 25 nm MOSFETs, where,
th similar behavior. When all the current Intel 65 nm technology has 35 nm physical gate lengths, A generic
by comparison,
s are reduced by the scaling
device that has beenbeen slowisbecause
studied of the given
schematically nonscaling
in Fig.of4 (Frank,
the subthreshold
et al.). This IC technology
harge densities should
are increased
enable many new applications, as tabled in Fig. 5, including, fortrend,
slope and the OFF current. To accommodate this example, the ability to
field configuration inside the more generalized scaling rules have been
2 created, in which
translate languages in real time that will only require 0.2 cm of chip area and need only 10 mW of
s in the originalpower.
device.Human
This intelligence-scale
the electric field is allowedpower
computation to increase
wouldby require some[17].
a factor tens-of-square meters,
which results inaccording
circuit speed Furthermore, the device widths and wiring
to Frank, et al., Device Research Conference, 1999. dimensions have
factor and circuit density not been scaled as fast as the channel lengths, leading to
g relations are shown in the a further scaling parameter for those dimensions. These
g with the scaling behavior of generalized rules are also shown
5-2 in Table 1 and are described
ysical parameters. in more detail in [5], [9], and [18].
l past and projected future The preceding scaling rules do not tell a designer how
these parameters versus the short he can make a MOSFET for given doping profiles and
nnel are gated. There are also
with buried oxide thin enough
thin enough for use in active Fig. 1. Schematic illustration of the scaling of Si technology by a
resting from a circuit point of factor alpha. Adapted from [5].
sed to dynamically adjust the
ussed here forlack ofspace. Table 1
as follows. Section II ad- Technology Scaling Rules for Three Cases
damental limitations to the
s that appear to be on the
fundamental limits, it may
n to very small dimensions,
maller. Section III describes
fundamental limit regime:
n the more practical world of
are many types of variations
e design of MOSFETs with
ok at some of these practical
ces for device design. Sec-
pts of the previous sections
d to meeting the needs of
The paper ends in Section VI
into a large table, followed
I.

MITS

is the dimensional scaling parameter, is the electric field scaling

king of MOSFETs has been F IGURE
parameter, and 3:and Scaling
areproperties of siliconscaling
separate dimensional MOSFETs.parameters for
[14], [15]. The basic idea is the selective scaling case. is applied to the device vertical dimensions
T is scaled down5.4
by a New
factor materials
and gate needed for scaling
length, while applies to the device width and the wiring.
h similar behavior. When all
Since the early 1980s, the materials used for integrated MOSFETS on silicon substrates have not
are reduced by the scaling been slow because of the nonscaling of the subthreshold
changed greatly. The gate “metal” is made from highly-doped polycrystalline silicon. The gate
arge densities are increased slope and the OFF current. To accommodate this trend,
oxide is silicon dioxide. For the smallest devices, these materials will need to be replaced.
ield configuration inside the more generalized scaling rules have been created, in which
in the original device. This the electric field is allowed to increase by a factor [17].
which results in 5.4.1 New gate oxides
circuit speed Furthermore, the device widths and wiring dimensions have
factor and circuit density
The capacitance pernot been
area of thescaled
gate as fastisas the channel lengths, leading to
oxide
g relations are shown in the a further scaling parameter for those dimensions. These
with the scaling behavior of generalized rules areCalso=shown ox inK Table
o 1 and are described
ox = , (1)
sical parameters. in more detail in [5], [9], and tox [18].tox
past and projected
where future The preceding
ox is the permitivity scaling
of the oxide, rules
o the do not tell
permitivity of athedesigner
vacuum,howand K the dielectric
these parameters versus the short he can make a MOSFET for given doping profiles and
constant. Scaled MOSFETs require larger Cox , which has been achieved with smaller tox . Increas-
seen, the voltages
ing Khave
cannot layerCthicknesses;
also increase ox , and otherthey only“high
oxides, describe how to shrink
K dielectrics” a known
are being developed, including
he length, in violation of the good design. Furthermore,
for example, mixtures of HfO2 and Al2 O3 . since the built-in potentials are
ove. In earlier generations of not usually scaled, the rules are inaccurate anyway. To find
se carrier velocities
5.4.2were in-gate metal
New the minimum gate length at each generation of technology,
ielding higher performance, one must analyze the two-dimensional (2-D) field effects
The doped
ects were kept in check by polycrystalline silicon
inside the FET.used
Thisforis gates
often has
donea very thin depletion
numerically layer, approximately 1
using com-
nm thick,
age. More recently, which causes
carrier scaling
plex 2-D problemstools,
simulation for small devices.
but the recent Other metals
analytic are being investigated
analysis
ed, but voltagefor replacing
scaling has the silicon gates,
by Frank et including tungsten
al. [19] reveals theand molybdenum.
primary dependencies. Other

5-3
PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001
 0- d
-0.1 - 16 nmldec.
-0.2-
-0.3- Super-Halo
-0.4 xi= 25 nm
101 ' """' 10
I
100
I

-0.5 I I Dielectric Constant

10 20 30 40 50
Channel Length (nm) Fig. 9 Scale length versus dielectric constant for three val-
ues of equivalent oxide thickness. Adapted from 171.
Fig. 7 Dependence of short channel effect on lateral doping
gradient. From [3].
DoubleGate. V, = 1.0 V

Fig. 17. Short-channel threshold rolloff for superhalo

Fig. 15. Source, drain, and superhalo doping contours in a 25-nm retrograde (nonhalo) doping profiles. Threshold voltage is d
nMOSFET design. The channel length is defined by the points as the gate voltage where A/ m. From [27].
10
where the source–drain doping concentration falls to 2 10 cm . 100
Dashed lines show the potential contours for zero gate voltage and Gate Length (L,) [nm]
a drain bias of 1.0 V. refers to the midgap energy level of the
substrate. From [27].
threshold voltage magnitudes far too high for bo
Fig. 10 VT rolloff characteristics of double-gated
[48]. With doped poly-Si gates, a frequently r
Electric Field (MVlcm) MOSFETs. From [SI. is the effect of poly-Si depletion on CMOS pe
Fig.F IGURE 4: 25 nm
8 Band-to-band gate length
tunneling currentMOSFET
density (at(Frank,
1 V et al., “Device scaling limits ofDepletion
Si MOSFETs and in polysilicon in the
effects occur
applied) versus electric field. Adapted from [3].
their application dependencies”, Proc. IEEE, 2001). thin-space charge layer near the gate oxide interf
acts to reduce the gate capacitance and invers
Application
density for a given gate drive. The percentage
pacitance attenuation becomes more significant a
thickness is scaled down. Actually, the net perfor
due to poly-Si depletion effects is much less s
Speech recognition (to text)
is suggested by – measurements. As it ha
Real time language translation delay of intrinsic, unloaded circuits is only slightl
Video encoding ( 5%) because although poly-Si depletion cause
QClF (174 x 144, 10 fps) the drive current, it also decreases the charge
CCIR 601 (720 x 480.30 fps) the next stage. These two effects tend to cancel
Vew hiah res. 1920Fig.
x 1200.30 fos)
16. Subthreshold currents for channel lengths from 30 to For the heavily loaded case in which the devic
15
2-way video wrist watch nm. A/cm (1 nA/ m) for 20, 25, and 30 nm large fixed capacitance, the delay degradation
devices. From [27]. those of the ON currents ( 15%). This can be co
PDA
to some extent by using wider devices. On the a
Tablet of about 2 10 cm [48]. Any source–drain doping that performance loss due to poly-Si depletion effe
Factoring 5 12 bit numbers
extends beyond this point into the channel tends to compen- 10% for partially loaded 25-nm CMOS circu
Deep Blue chess sate or counterdope the channel region and aggravate the 1.5-nm-thick oxide [27].
short-channel effect. The abruptness requirements of both
OM-based device simulation Extensive 3-D statistical simulations have been
the source–drain and the halo doping profiles dictate abso- on the effects of dopant fluctuations on threshold
petaFLOPS computing challenges the above 25-nm device design [49]. Some of the
lutely minimum thermal cycles after the implants. Note that
Table 1. Selecteda possible applications
raised source–drain of 25 nm
structure mayCMOS technology
help making and theirpresented
contacts, estimatedin Section IV-C.
requirements. Power but doesestimates
not by are forsatisfy
itself general thepurpose
abruptness processors (GPP) andTospecial
requirement evaluate the potential ON-state perfor
purpose DSP-likediscussed
processors.here.Adapted from [ 13. 25-nm CMOS, detailed Monte Carlo simula
As discussed in Section II-B, a key issue with the high performed using the simulator DAMOCLES [50
F IGURE 5: Future applications p-type dopingenabledlevel by
and 25 narrow
nm depletion
gate length regions in this (Frank,
MOSFET and p-channel MOSFETs have been simulated
et al., Device
25-nm design is the band-to-band tunneling through the low-output conductance high-performance –
Research Conference, 1999). high-field region between 21 the p-halo and the drain. For the teristics for both device types [27]. The transco
peak field intensity (1.75 MV/cm) at high drain and zero exceeds 1500 mS/mm for this nFET, with an es
gate biases shown in Fig. 15, the tunneling current density is higher than 250 GHz. Transient Monte Carlo s
5.4.3 Removing the substrate: on the order Silicon
of 1 A/cm on insulator
(Fig. 9). This should not constitute were also done for a three-stage chain of 25-nm
a major component of the device leakage current given the verters. Fig. 18 shows the output waveforms. The
For high-frequency circuitsnarrow (about 5 GHz
width and above),
of the high-field region,capacitive
15 nm accordingcoupling
to todelay
the time
silicon substrate
is 4–4.5 ps, about three to four times
Fig. 15.
limits the switching frequency. Also, leakage into the substrate from the small devices can cause 100-nm CMOS operated at 1.5 V.
The threshold design in Fig. 17 assumes dual n /p One way to go beyond 25-nm bulk CMOS is
extra power dissipation. These Si work problems are being
function gates avoided by
for nMOS/pMOS, makingAcircuits
respectively. CMOS onchip
insulating sub- as discussed in
to low temperatures
strates (either sapphire or siliconmidgap work dioxide)
function that
metalhavegateawould
thin,clearly
approximately
result in 100
to thenm
11-nmlayer
bulk of crys- described in Section
MOSFET
talline silicon, in which the MOSFETs are fabricated.
FRANK et al.: DEVICE SCALING LIMITS OF Si MOSFETs AND THEIR APPLICATION DEPENDENCIES

5-4
 l l
100 polysilicon half-pitch
l printed gate L
l s
l physical gate L
l
l
50 l
t l
l
feature size [nm]

t l
t l
t l
t l
t l
20 t l
t l
t
poly half-pitch t
t
t
10 t
t
t
t

2000 2005 2010 2015 2020

Year

F IGURE 6: The ITRS roadmap for the gate length and polysilicon half-pitch in DRAMs. (ITRS
2004 update: http://public.itrs.net/)

5.5 The Roadmap

The semiconductor industry collaborates on predicting and determining the future changes to IC
technology, contained in the International Technology Roadmap for Semiconductors (ITRS). Fig-
ure 6 gives an example from the 2004 update for dynamic random access memory (DRAM) MOS-
FETs. The gate length is projected to drop below 10 nm in about 10 years.

5-5