Design And Implementation Of 4-Bit ALU Using
FINFETS For Nano Scale Technology
Likhitha Dhulipalla
Student, M. Sc in VLSI System Design M. S.Ramaiah School of
Advanced Studies Bangalore, India
E-mail: likhitha.ec@gmail.com
Abstract-In VLSI technology, continuous scale down of the
transistor proves the Moore's law which describes the transistors
placed in a chip doubles in every 2 years. As MOS transistors
sizes scales down, challenges and limitations also doubles in each
shrinking of the transistors such as short channel effects and sub­
threshold voltage variations etc. To reduce such challenges and
keep shrinking the size of transistor will attain the certain level of
achievements in nanoelectronics with the help of FINFET based
transistors. In this paper, we've described about FINFET based
Arithmetic Logic Unit (ALU) is developed which acts as core
part of a CPU, with the arithmetic functions such as addition,
subtraction, and logical functions such as AND, OR etc.
Keywords- FINFET; 4-Bit ALU
I. INTRODUCTION
MOSFET technologies that are proposed as a
replacement to planar devices that uses gates on more than
one side of a thin channel have shown better short channel
characteristics. These FIN type devices have a single gate
wrap around multiple silicon surfaces. These devices offer
excellent characteristics for a given bias across the gate.
Scaling down in the MOS transistor increased the
interconnections and limits the circuit density. This is
intended the VLSI technology to invent the new transistor
called FINFET.
II. BACKGROUND THEORY
A. FINFET
The major design issues in Metal Oxide
Semiconductor Field Effect Transistor (MOSFET) based
designs are [1]:
• Gate oxide tunneling leakage: as the gate oxide
thickness is scaled to maintain gate control voltage VT
and performance, gate insulator direct tunneling
leakage increases. The electron tunneling from the
Valence Band (EVB) generates the substrate current
in both nMOS and pMOS. This substrate current and
its effects are neglected in bulk CMOS.
• Self heating: the heat transfer is dominated by
photon transport in semiconductors and by electron
transport in metal. The thermal resistance increase is
prominent for thinner Si film with thick buried oxide.
978-1-4673-0074-2/11/$26.00 @2011IEEE 190
Lourts Deepak .A
Student, M. Sc in VLSI System Design M. S.Ramaiah School of
Advanced Studies Bangalore, India
E-mail: lourdu.lourdu@gmail.com
• Soft Error Rate: the a-generated charges are less, due to
the presence of buried oxide. Scaling of the device
reduces the charge generation volume, the Qcrit
decreases due to a lower capacitance at the cell's
storage node and scaled V DD.
• Strained-Si channel and high-K gate: strained Si
surface channel CMOS has high- performance
applications due to higher mobility and improved
current. The lattice mismatch between the Si channel
and the SiGe layer results in biaxial tensile strain, it
reduces the scattering by increasing sub-band splitting
and enhances carrier transport by reducing
conductivity effective mass. High-k dielectrics are
used to contain the gate leakage and extend device
scaling. The high-k has the band gap less than Si02,
by which tunneling leakage is reduced. High-k has
charge-trapping related instability and mobile
degradation. By integration the High-k gate, the
higher gate capacitance per unit area and mobility is
improved.
FINFET offers distinct advantages for scaling to very
short gate lengths. Fabrication of the FINFET- DGCMOS is
similar to that of the conventional CMOS process, with only
minor disruptions, offering the potential for a rapid
deployment to manufacturing. The channel of the FINFET is a
tiny chunk of un-doped silicon perpendicular to the substrate.
The un-doped channel eliminates the coulomb scattering due
to impurities resulting in higher mobility in FINFETs. The
height of the FIN, hfin, acts as the width of the channel.
The channel width of FINFET is given by W=nfin*
hfin, Here, nfin is the number of fins in the transistor.
The control of the short channel effects for FINFETs is
provided by the two gates without aggressively scaling down
the gate-oxide thickness and increasing the channel doping
density. The modes of FINFET operation identified are [2]:
• The short-gate (SG) mode - where transistor gates tied
together, as shown in the figure 1 with an example of
NAND gate.
• The independent gate (IG) mode-where
independentdigital signals are used to drive the two
device gates, the mode is explained in the figure
2, taking the example of NAND gate.
 output of the full adder to 2:1 multiplexer for further selection.
The select line S2 used for 2:1 MUX for selecting the
arithmetic function (S2=O) and logical function (S2=1), as
shown in table 1.
B
B
A A C:i;''''••••••••••• �
.0
:
." ' ••••••••••••••••••••••••••••••••• "

Figure I: SG-mode NAND [2] Figure 2: IG-mode NAND

r�l

• The low-power (LP) mode-where the back-gate is

tired to a reverse-bias voltage to reduce leakage
power, the NAND gate schematic is shown in figure 3.
• The hybrid (IG/LP) mode which employs a

�:':'il!"l :6 �illl 8-;

combination of LP and IG modes, the schematic of
the NAND gate is shown in the figure 4.

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B
B A
A

Figure 5: Block Diagram of 4-bit ALU.

Figure 3: LP-mode[2] Figure 4: IG/LP-mode[2] In the figure 6, the logical operations are performed using
the basic logic gates, the delay for each logic operation would
be delay through the gate. The Arithmetic operations make use
of the complete adder. Increment and decrement operations are
B. Arithmic Logic Unit(ALU) [3][4]
special cases of addition and subtraction. Increment operation
The design of 4-bit ALU of the ripple carry adder is equivalent to an addition byl and subtraction is equivalent to
model, which performs four arithmetic and four logical 2's complement addition. The delay for each arithmetic
operations. The four arithmetic operations include ADD, operation is more complex than that of the logical operation as
SUBTRACT, INCREMENT and DECREMENT. The four it depends not only on the type of logic used to construct the
logical operation are AND, OR NOT and IDENTITY. 4-bit SUM and CARRY units of the full adder, but also input pattern
ALU is designed by cascading four I-bit ALU blocks. Each 1- and the critical paths in the circuit. Optimizing the design of
bit ALU is composed of the following four components: the full adder optimizes all operations to some extent.
l. Arithmetic 4:1 multiplexer,
2. Full adder, A

AND
3. Logical 4:1 multiplexer, R

4. 2:1 multiplexer to select either arithmetic or A

logical operation. B OR
::E
-
�
OUTPUT

Each bit uses three multiplexers and one full adder.

A
NOT
The block diagram of 4-bit ALU is shown in the figure
5.The 4:1 multiplexers have two select inputs SO and SI. These
" I D ENTITY
4:1 MUX designed in CMOS pass- transistors logic for low
power. The MUXs are used to provide the proper input signal
for the adder circuit depending on the operation being
performed on the proper input signal and also to pass the Figure 6: Block diagram of 4: I MUX performing logical operation

191
 Table I. Operation of ALU F = (A. SO'. SI ')+(B. SO. Sl')+(C. SO'. S1)+(D. SO. S1).
52 51 50 Mnemonics Description
Add Data-A and Oata-B
0 0 0 Addition Oata-A + Data-B = Result
Cis Carrv for Addition
Subtract Data-A and D ata-B
0 0 1 Subtraction Data-A - Data-B = Result B
C i s Borrow for S ubtraction
I ncrernent Data-A by 1
0 0 Increment Data-A + 1 = Result
Carry bit has to be 1 c;
Data-B has to be 0 Tl"T I
Decrement Oata-A by 1
0 Decrement Oata-A - 1 -= Result
Carry bit has to be 0
D,_---'TTT I I
Data-B has to be 1
logical AND for Data-A and Data-B
0 0 AND Data-A & Data-B = Result
C is Don't Care

logical OR for Data-A and Data-B

Figure 8:4: I Multiplexer using FINFET IG mode
0 OR Data-A I Data-B = Result
C is Don't Care

Logical NOT for Data-A B. AND, Exclusive-OR, OR and iNVERTER gates:

0 NOT (-Data-A) = Result
C is Don't Care

Logical IDENTITY for Data-A

The AND gate is a digital logic gate that implements
IDENTITY Data-A + 0 = 0 and Data-A + 1 = 1 logical conjunction- it behaves according to the truth table. A
C is Don ' t Care
HIGH output results only if both the inputs to the AND gate
are HIGH. If neither or only one input to the AND gate is
III. WORKING OF ALU HIGH, a LOW output results. The figure 9 shows the
The blocks designed while developing the 4-bit ALU schematic of the AND gate, using IG-mode FINFET.
that performs eight different operations are: VDD

• 4:1 Multiplexers
• Exclusive -OR, AND, OR and INVERTER gates y

A B
• Full Adder block

• 2:1 Multiplexer
The blocks are developed using the dual-gate IG-mode
of FINFET modeling. As shown in the figure 7, the two
vertical gates of the Single-FINFET is separated by an oxide
on top of the silicon FIN, thus forming an independent- gate Figure 9: AND Gate using IG-mode FINFET
FINFET. An IG FINFET works on two modes of
operation with different I-V characteristics depending on
input bias to gates. In the dual-gate mode, the two gates are The OR gate is a digital logic gate that implements
biased with the same signal and in the single-gate-mode; one logical disjunction- it behaves according to the truth table to
gate is biased with the input signal to induce channel the right. A HIGH output results if one or both the inputs to
inversion while the other gate is disable. As two gates are the gate are HIGH. If neither input is HIGH, a LOW output
strongly coupled in the dual-gate- mode, the threshold results. The schematic is shown in the figure 10, using IG­
voltage IVthl is lowered when compared to the single-gate­ mode FINFET.
mode. For example, the maximum drain current VDD
produced in the dual-gate-mode is 2.77 times higher as
compared to the single-gate-mode in a minimum-sized P­
channel FINFET.
y

A B

Bac.kG_

Figure 10: OR-Gate using IG-mode FINFET

Figure 7: 3D Structure of one-fin FINFET [5]

The EX-OR gate is a digital gate that implements
A. 4: i Multiplexers: logical HIGH when either of the input is HIGH. When both
The figure 8 represents the pass transistor model of 4:1 the inputs are similar the output is LOW. The schematic is
multiplexer block using FINFET in IG mode. The output of shown in the figure 11, using IG-mode FINFET.
4:1 MUX depends on the select line SI and SO.
The equation for 4:1 is given as:

192
 VDD D. 2:1 Multiplexers:
The 2:1 MUX is an combinational design, the 2 input are
13 given and one output. The output depends on the select input
of the design. The Boolean equation is given by
A 13 Y=(A. S')+ (B. S).

A 13
The schematic of the 2:1 MUX is shown in the figure 13.

'GND

Figure I I: EX-OR gate using IG-mode FINFET

In digital logic, an inverter or NOT gate is a logic

gate which implements logical negation. An inverter circuit
outputs a voltage representing the opposite logic-level to its B ----'
input. Inverters can be constructed using a single NMOS
transistor or a single PMOS transistor.

C. Full adder Block:

A full adder is a combinational circuit that forms the Figure 13: 2: 1 Multiplexer using IG-mode FlNFET
arithmetic sum of three input bits. It consists of three inputs
and two outputs. In this design, the designated three inputs are E. Modeling the 4-bit AL U
A,B and Cin. The third input Cin represents carry input to the The I-bit ALU initially starts with a 4:1 MUX The .

first stage. The outputs are SUM and CARRY. The Boolean
expression for SUM and CARRY bits are given below.
SUM=A Ef)BEf)Cin.
CARRY=AB+BCin+CinA.
SUM bit is the EXOR function of all three inputs and
CARRY bit is the AND function of the three inputs. The
schematic of the full adder using AND OR and EX-OR gates ,
is shown in the figureI2.
select lines of the MUX SO and S, will be used to select
the operations that the ALU performs. The input lines of the
MUX will BO (used for addition), BOn(used for
subtraction),O(used for increment) and 1 (used for decrement).
The input lines of 4:1 MUX corresponds to only Input Date-B.
The next block is Full Adder block. The input Data-A
and carry Bit will be given externally to the FULL ADDER.
With these 3 input variables the Arithmetic operations will be
performed with respect to the select lines. The next block is
being the Logical Block which again requires a 4:1 MUX The .

D-- select lines will be the same as SO and S l. The input lines for
::::JC>L::::JC>------o SU�I
XOR2
the second 4:1 MUX is AND (Intermediate stage output in
carry), OR, NOT (Inverter used for subtractor) and
J IDENTITY. As AND NOT logic gates are already used for in
,

the design it can be called once again. One more OR gate is

I �D----OCOUT required for the OR operation as well as IDENTITY
=c>-- operation. The output of Arithmetic operations and Logical
I
.D---f operations are taken to 2:1 MUX which is controlled by S2
select line. Whenever S2 goes LOW, arithmetic operations
output will be displayed and when it goes HIGH, logical
operations output will be displayed. The same set of logical is
Figure 12: Schematic offull adder.
copied 4 times so that 4-Bit ALU operations can be
The truth table of a full adder is shown in table2. performed. The Carry Out of the I-bit ALU will pass on to
Depending on the status of input bits A and B, the CARRY bit second I-bit ALU so that arithmetic operations can work very
is either generated or deleted or propagated. easily. The remaining operations will perform as usual. The
carry will be ignored whenever the Logical operations are
Table II: Truth table of Full Adder
being performed.
Carry IV. RESULTS
A B 'Gin Su m Carry
Status
The ALU operation can be monitored by arithmetic and
0 () 0 0 () Delete
logical. The figure 14 represents the addition and subtraction
0 () :Jl :Jl () Delete
operation for I-bit inputs A (0), B(O) and Cin. When these
0 1 0 :Jl 0 Propagate inputs are given as 1, the outputs Sum, Cout, Difference and
0 1 :Jl 0 1 Propagate Borrow are obtained as 1. These operations will be performed
1 () 0 :Jl () Propagate when the select lines SI and S) are 0, ° and 0, 1 respectively.
1 0 :Jl 0 1 Propagate
1 1 0 0 1 Ge nerate
1 1 :Jl :Jl 1 Gene ;rate
193
 i':

f� ruJuruGJU1Jll

Figure 16: Waveform for AND and OR operations

By comparing the figure 17 and 18, it is clearly observed

Figure 14: Add and Subtract Operations of designed ALU
The figure 15 represents the increment and decrement
operations for 4-bit ALU based on the select line SO which is
Cin. The inputs applied are A=IIII, based on the carry signal
the operation varies, if the carry Cin, SO is 1 then the operation
performed is increment else decrement.
The figure 16 represents the AND and OR logical
operations. These are obtained based on the select line S2. The
INVERT and IDENTITY operations are performed by an
inverter and one, and gate whose one input is 1 and other is A.
the verification of 4-bit ALU has been observed from the
figure 14 to 16.
that the switching or the transition of the signals is faster in
32nrn than 45nrn waveforms. Though the switching is faster in
32nrn the signal transition will be visible only if the
geometries are accurately decided.
(AJ Delay andpower Calculation
The delay of the design can be calculated by measuring
the waveforms. The rise delay is calculated by the time
difference between the 50% of rise in input to 50% of rise in
the output. The fall delay is calculated by the time difference
between the 50% of fall in the input to 50% of fall in the
output. The total delay is considered as (Rise + Fall) / 2. The
delay of the sub-blocks is given in the table 3.

The output waveforms of the Adder operation for 45nrn

and 32nm are shown in the figure 17 and 18 respectively. In
the figure 17 the inputs A and B as per the tracer are 0III and
0100 respectively and carry input is 1, the output of the ALU
for addition operation is 1100 with an output carry of O. The
delay of the 4-bit ALU is calculated by measuring the
waveforms obtained. The total delay is calculated from the
equation (Rise+ faU)/2.

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R Figure 17: Result of 4-bit ALU of ADDITION operation for 45nm

�:I I technology

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�:I I II ,�, I' I I! III I I

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�jl ' -j--

� I U[[JUUUOUbbbUCtJUJLPL[�JUL[]\J
�c I
�I ULJ uL "L..�JLJ �l IIILJ �LI'
'

�L
��· ����
L=�
_ J ��
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Figure IS: Increment and Decrement Operations of ALU

Figure 18: Result of 4-bit ALU of ADDITION operation for 32nm
technology

194
 Table Ill: Delay and power of the ALU Design operations V. CONCLUSION

The design of the 4-bit ALU have been designed by

Operation Delay for Max power using the sub blocks of full Adder, 4xl and 2xl
45nm for 45nm multiplexers, and gates like exclusive-or, and, or and
Addition 7. 83ns 1.74nW inverter. The ALU performs a total of eight operations, out of
Subtraction 2. 87ns l.53mW which four are arithmetic and remaining are logical
operations. The four arithmetic operations performed are
Increment 70.1ps 2.04mW Addition, Subtraction, Increment and Decrement and the four
Decrement 69.5ps 5.37mW logical operations are And, Or, Invert and Identity. The
AND 22.01ns 0.23mW selections of these operations are made by the selection lines S
(2), S (1) and S (0). The design of the 4-bit ALU is
OR 5.09ns 0.215mW
performed for 32nm technology. The delay by the design in
NOT 12.1ps 0.117mW 45nm and 2nm the technologies are observed to be -0. 38ns
IDENTITY 5.09ns 0.215mW and -0.47ns respectively and the maximum power consumed
I-Bit ALU 101. 8ps 1.96mW by the design is found to be 8.2mW and 21.47mW
respectively.
4-Bit ALU 3. 83ns 8. 38mW
VI. FUTURE WORK
The ALU has been designed for both 45run and 32 run As per the table 4, when the technology shrinks less
technology nodes. From both technology nodes power and than sub deep microns, power consumption of circuit will be
delay has been calculated and tabulated below in table 4. From more due to its interconnection. To avoid this we can able to
this table, it is observed that the maximum and average power adopt some power compression logics such as adiabatic circuit
consumed by the 32 nm is more when compared to 45run which implements the power conservation techniques in
technology node. But in delay wise, 45run has more delay FINFET based design.
when compared to 32 run.
VII. REFERENCES
Table IV: Comparison between Power and delay of 45 and 32nm technology
node
[1] Unknown, FINFET, Electronics Seminar Topic,
www.techalone.com retrieved on 24-08- 1 1.
Power consumed [2] Nirmal , Vijay Kumar and Sam Jabaraj, NAND Gate Using FinFET for
Technology Max Avg Delay NanoScale Technology, International Journal of Engineering Science
power power and Technology, VoI2(5), 13 15- 1358,20 10
5nm 8.2 mW 0.47 mW 0.38ns [3] Neil H.E.Weste, Kamran Eshraghian Principles of CMO S VLSI
2nm 2 1.4 mW .4 mW 0.47ns Design, Second Edition, Pearson Education ( Sg) pte. ltd, 2004.
[4] S.M kang and Y.Leblebici, CMOS digital integrated circuits, TMH
publishing company limited, 2007
[5] Sheriff A. Tawfik and Volkan Kursun, FINFET domino logic with
independent gate keepers, Microelectronics Journal, 29 January, 2009.

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