Silicon

https://doi.org/10.1007/s12633-020-00861-z

ORIGINAL PAPER

Improving Short Channel Effects by Reformed U-Channel UTBB FD

SOI MOSFET: A Feasible Scaled Device
Moslem Ghassemi 1 & Ali A. Orouji 1

Received: 5 August 2020 / Accepted: 20 November 2020

# Springer Nature B.V. 2021

Abstract
U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect
Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS
technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel.
This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-
channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As
it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed
U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel
effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage
roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed
structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition,
the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel
thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering
(DIBL).

Keywords U-channel . UTBB . SOI MOSFET . TCAD . Short Channel effects . High-k dielectric

1 Introduction (SOI) technique, which is acceptable and vastly utilized.

In the past decades, ongoing demand of Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs) provid-
ing high speed, high packing density, and low power consum-
ing in VLSI industries for smart and mobile applications, has
been leading researchers to shrink transistors in size. As these
basic unit of Integrated Circuits (ICs) are scaled to nanometer
regime, numerous undesirable effects which are named Short
Channel Effects (SCEs) arise. Threshold voltage roll-off,
Drain Induced Barrier Lowering (DIBL), subthreshold swing,
punch through, Hot Carrier Effect (HCE), are problematic
issues which deeply affect the MOSFET performance.
Of all the proposed solutions, the most prominent approach
to overcome these provoking effects was Silicon On Insulator
* Ali A. Orouji
Aliaorouji@semnan.ac.ir
1
Electrical Engineering Department, Semnan University,
Semnan, Iran
Because of lessening parasitic capacitance, SOI-MOSFETs
were became faster and offer more benefits, such as higher
drive current, lower power characteristics, latch-up current
immunity and shorter interconnect length over bulk competi-
tors [1–3]. As SOI MOSFETs scaling down to sub 50 nm,
conventional methods to defeat SCEs were inefficient and
many alterations have been applied to lessen degradation ef-
fects of channel length shrinkage. Lots of different solutions
have been proposed to overcome these problems [4–13].
Channel engineering techniques are effective methods to
suppress degradation effects of device miniaturization [14],
involving U-channel MOSFETs [15, 16]. In the U-channel
scheme, the silicon film is etched to form U-shape grooves,
so helps to separate the source and drain depletion region
which reduces punch-through effect. In addition to more gate
control over the channel, this separation also has decreased
threshold voltage roll-off [16]. One recent promising strategy
on ultra-scaled device which is planar and compatible with the
bulk silicon CMOS fabrication process, is Ultra-Thin Body
and Buried oxide (UTBB) implementation of Fully Depleted

(FD) SOI MOSFETs. It has advantages for future low-cost
energy-efficient applications [15], excellent for short channel
effect immunity and ideal subthreshold characteristics [17,
18]. In UTBB device, short-channel effects are usually con-
trolled by a narrow silicon layer, thus this thin silicon body
enhances the electrostatic qualities [19], reduces the leakage
current [5, 20], increases on-to-off current ratio because of
carrier mobility improvement [21], and allows the channel to
be un-doped [5, 22]. Furthermore, thinning of the BOX has
been suggested as a good solution to lower self-heating effect
and fringing electric fields through the BOX and substrate
[23]. By using intrinsic channel, higher drive current and
steeper subthreshold slope are attained. Possessing awesome
subthreshold swing and DIBL are critical for good overdrive
and hence device switching speed. Moreover, because of re-
moving the random dopant fluctuation, significant improve-
ment of variability control is achieved [24, 25].
To derive the most forgoing benefits, an innovative U-
channel UTBB (U-UTBB) SOI MOSFET has submitted in
this work which has no fabrication process complexity in
comparison with FinFET and fully compatible with SOI
CMOS technology as well as owing admissible Technology
Computer-Aided Design (TCAD) analysis. In the proposed
U-channel MOSFET device, two spacers around the recessed
metal gate are removed. The proposed structure is called
Reformed U-UTBB (R-U-UTBB) FD SOI MOSFET. Our
results show the superiority of proposed structure compared
with the U-UTBB FD SOI MOSFET and a conventional
UTBB (C-UTBB) FD SOI MOSFET. The paper is organized
as follows: In Section 2, the macroscopic novel device tem-
plate, simulation details, and modeling are described. And in
Section 3, the proposed device compares with its conventional
counterparts and advantages are discussed individually.
2 Device Structure and Simulation
Methodology
Figure 1(a) shows schematic cross section of the C-UTBB
structure with raised drain and source. In the UTBB device,
the body thickness should be as thin as possible, but the
series resistance of the source and drain regions increase
and so affect the transistor current [26–28]. By creating a
raised source and drain structure, the parasitic resistance
can be diminished. Nevertheless, one downside of this
structure is growing overlap capacitance. Thus, spacer
widths between the gates and raised source and drain have
located [5]. Also, Hafnium dioxide, HfO2, is used as a
high-k gate dielectric due to its high dielectric constants.
They have thermal firmness when in contact with Si [29].
In fact, HfO2 exhibits robust ferroelectricity when it is
doped with Si, Yttrium, or Al [30].
Silicon
The schematic cross section of U-channel UTBB (U-
UTBB) structure [15] is shown in Fig. 1(b) which is asserted
by moving up the spacers located between gate and source/
drain and adding two vertical channels (Xj) to the horizontal
channel (Lg), DIBL and subthreshold slope are enhanced.
Source and drain regions in these structures have constructed
using uniform doping profiles with Gaussian tails. In the pro-
posed nMOS structure that is shown in Fig. 1(c) and we have
called it as Reformed U-channel UTBB (R-U-UTBB) struc-
ture, the spacers are eliminated entirely, so the Gaussian dop-
ing profile with minimum uniform doping part in an intrinsic
silicon film is used.
There is a ration of the gate length to the channel
thickness (Lg /Tch) of UTB MOSFETs that short-channel
effects are sufficiently defeated when this ratio is greater
than 4 [5]. So, the gate lengths of structures have chosen
16-nm. Also, the top silicon film has 15-nm thick and
reaches to 4-nm beneath the metal gate to satisfy Lg/Tch
ratio. For the reason that thin body devices can control
short channel effects with only un-doped channel, the
channel of novel structure has left intrinsic. Significant
performance enhancements such as improving carrier mo-
bility and high on-to-off current ratio with low change
because of random dopant fluctuation can be expected
[21]. Although, with un-doped channel in UTBB
MOSFETs, threshold voltage adjustment can be attained
by gate work function engineering if necessary [5].
According to experimental results reported in [29], a prac-
tical limit for SiO2 thickness as a gate oxide is 10–12 Å
for excellent electrical properties, which a 1-nm film of
SiO2 as an interfacial layer has used. An aluminum gate
with a 2-nm-thick HfO2 dielectric has specified. So the
effective work function is calculated by simulator and is
given by:
Φmeff ¼ E  HIGHK þ S  HIGHK ðWORKF–E  HIGHKÞ ð1Þ
where Φmeff is the effective gate work function,
E.HIGHK is the charge neutrality level of the high-k ma-
terial, S.HIGHK is a slope parameter of the high-k mate-
rial, and WORKF is the metal work function in vacuum
[31]. These default parameters are given in Table 1.
Active layer deposited on the 20-nm buried oxide (BOX),
so heat generated by the hot carriers is delivered smoothly to
substrate. Thin BOX devices also become more suitable for
applying back-gate biasing idea used for tuning device char-
acteristics like set or modulate threshold voltage [32]. Table 2
summarizes the crucial parameters of contemporary formation
which have utilized for the device simulation.
A two dimensional ATLAS device simulator [31] is used to
simulate the device’s electrical behavior. Simulated device
geometries and structure are close as possible as experimental
device. In order to achieve more realistic results, several
Silicon

Fig. 1 Schematic cross section of

(a) C-UTBB, (b) U-UTBB, and
(c) R-U-UTBB SOI-MOSFETs

models have activated in simulation. The physical device 3 Results and Discussion
model includes the effects such as band gap narrowing
(BGN) for the carrier statistics, combination of Klaassen 3.1 Output Characteristic and Sub-Threshold Slope
(KLA) and Shiharata (SHI) and parallel electric field depen-
dence are considered for carrier mobility modeling (doping In this paper, we compare the simulation results of R-U-
dependence, high field saturation effects). Also, Shockley– UTBB structure with the U-UTBB and the C-UTBB struc-
Read–Hall (SRH) and Auger (AUG) for recombination as tures. The output characteristics of three structures for two
well as avalanche generation are used. With continued scaling gate-source voltages of 0.4 and 0.8 V are shown in Fig. 2.
into the deep nanometer regime, the energy balance model has
activated (HCTE) to perform accurate simulation. When the
energy balance transport model is applied, the appropriate Table 2 Critical parameters of the proposed structure in the device
impact ionization model is (CONCANNON). This accurate simulation
model calculates the probability of a carrier having sufficient
Device parameter Value
energy to cause impact ionization. In addition, due to take into
account quantum effects, Bohm Quantum Potential (BQP) for Gate length (Lg) 16 nm
quantum modelling has applied. Second interfacial layer (SiO2) thickness (TSio2) 1 nm
high-k gate dielectric (HfO2) thickness (THk) 2 nm
Top silicon thickness (TSOI) 15 nm
Table 1 Dielectric Channel thickness (Tch) 4 nm
parameter defaults Parameter name Value
Buried Oxide (BOX) thickness (TBOX) 20 nm
E·HIGHK 4.81 eV Effective work function (Φmeff) 4.3065 eV
S·HIGHK 0.95 n+ Source & Drain maximum doping 1020 cm−3
WORKF 4.28 eV Substrate doping 1015 cm−3
 Silicon

Fig. 3 Compare of R-U-UTBB subthreshold slope to U-UTBB and C-

UTBB SOI-MOSFETs in transfer characteristics for 16 nm gate length of
Fig. 2 The simulated output characteristics of the C-UTBB, U-UTBB,
nMOS device on Vds = 0.05 V
and R-U-UTBB SOI-MOSFETs for Vgs = 0.4 and 0.8 V

However, the R-U-UTBB device has a lower saturation cur- Leff ¼ Lg þ 2X j ð5Þ
rent than the U-channel and conventional UTBB, but it is
more stable than the C-UTBB and U-UTBB structures as it
can be concluded from slope of the graphs. The values of this parameter is 24-nm for the U-UTBB
The sub-threshold slope is one of the important quality of a and 38-nm for the R-U-UTBB structures which are given
MOSFET’s current–voltage characteristic. The drain current in Table 3. However, by increasing Leff in the U-UTBB
behavior in the sub-threshold region is similar to the exponen- and the R-U-UTBB structures, both the Cdep and Cox are
tially decreasing the current of a forward biased diode. The growing, but the effect of rising C o x is dominant.
sub-threshold slope is linked to the depletion capacitance by Consequently, the sub-threshold slope of R-U-UTBB
the equation: structure improved about 8% and 18% in comparison with

 the U-UTBB and the C-UTBB structures, respectively.
KT C dep These values are summarized in Table 3. As transfer char-
S¼ lnð10Þ 1 þ ð2Þ
q C OX acteristics of three structures are shown in Fig. 3, the re-
duction of sub-threshold slope for the proposed R-U-
where T is the temperature, q is the electronic charge, S is the
UTBB device than the C-UTBB and U-UTBB devices
sub-threshold slope, Cdep is the capacitance of depletion re-
are notable. To show the variation of sub-threshold slop
gion, and Cox is the gate-oxide capacitance [33]. It can be seen
versus gate length, this short channel effect has simulated
from Eq. 2 that decreasing the depletion capacitance Cdep, or
for gate length of 8 to 26-nm and plotted in Fig. 4.
increasing Cox will improve the sub-threshold slope.
In fact, with decreasing the gate length, an extra factor is
introduced to account for increasing the sub-threshold slope
Table 3 SCEs parameters of R-U-UTBB SOI-MOSFET compared to
[19], so that:
U-UTBB and C-UTBB devices
 
T OX el X j 3 T dep
EIS ¼ 1þ ð3Þ parameter C-UTBB U-UTBB R-U-UTBB
Lel 2 4 Lel
" sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi# Xj (nm) 0 4 11
KT C dep εSi V ds Lg (nm) 16 16 16
S¼ lnð10Þ 1 þ þ EIC 1 þ 2 ð4Þ
q C OX εOX φd Leff (nm) 16 24 38
DIBL (mV/V) 137 100 81
where Vds is the source to drain potential and φd is the drain Subthreshold slope (mV/dec) 93 81 76
barrier potential that should be taken to 1 V for simplicity. Threshold voltage (V) 0.27 0.23 0.25
Figure 3 shows the transfer characteristic for Vds = 0.05 V and Threshold voltage roll-off (mV) 46 47 25
subthreshold slope of the R-U-UTBB in comparison with the Ioff (A) 8 × 10−08 2 × 10−08 4.3 × 10−09
U-UTBB and the C-UTBB structures. In fact, in the U-channel Ion/Ioff 4.4 × 103 1.6 × 104 6.4 × 104
structures instead of Lg, Leff should be used as follows [14]:
Silicon

Fig. 4 Sub-threshold slope variation of 8 to 26 nm gate length for the C-

Fig. 6 DIBL variation of 8 to 22 nm gate length for the C-UTBB, U-
UTBB, U-UTBB, and R-U-UTBB SOI-MOSFETs
UTBB, and R-U-UTBB SOI-MOSFETs

3.2 Drain Induced Barrier Lowering (DIBL)

Reduction of threshold voltage of the MOSFET at higher
drain voltages is known as DIBL. In practice, the DIBL with
typical unit of mV/V can be calculated as follows:
Th −V Th
V DD low
DIBL ¼ −
V DD −V low
where V DD
Th is the threshold voltage measured at a supply volt-
age, and V low
Th is the threshold voltage measured at a very low
drain voltage, typically 0.05 V. The VDD is the supply voltage
and Vlow is the low drain voltage. To illustrate DIBL that has
been defined as the difference between the linear threshold
voltage and the saturation threshold voltage, the transfer char-
acteristics of R-U-UTBB for Vds = 0.05 and 1 V shows in
Fig. 5.
DIBL is also could defined as the gate voltage shift due
to a drain voltage variation extracted at a constant nor-
malized drain current. We use this definition to extract
DIBL for 8 to 22-nm range of gate length for the C-
U T B B , th e U - U T B B , a n d t h e R - U - U T B B S O I -
MOSFETs. The DIBL variations of three structures are
shown in Fig. 6. Because by drain voltage increasing,
the surface potential in the U-UTBB device is not
ð6Þ changed much near to the source, it has much immunity
on this effect [14]. In other words, because of increasing
Leff, the DIBL of R-U-UTBB structure improves 21%
than the U-UTBB and 41% than the conventional one.
The simulated values of three structures are summarize
in Table 3.
3.3 Leakage Current and Ion/Ioff Figure of Merit
Leakage current in MOSFETs is classified to three type of
junction leakage, gate leakage, and off-state leakage, and all
of them increase when transistors are scaled down. Channel

Fig. 5 Id-Vg curves on linear (Vds = 0.05 V) and saturation (Vds = 1 V) Fig. 7 Ion/Ioff ratio of the C-UTBB, U-UTBB, and R-U-UTBB SOI-
threshold voltage for showing DIBL of R-U-UTBB SOI-MOSFET MOSFETs versus gate length which

Fig. 8 Threshold voltage roll-off due to gate length variation of 8 to
26 nm gate length for the C-UTBB, U-UTBB, and R-U-UTBB SOI-
MOSFETs
doping is the main reason of junction leakage, which is re-
quired to set threshold voltage, and to defeat SCEs in short
channel devices [27]. Using un-doped channel can be de-
creased this type of leakage which is employed in our struc-
tures. Device scaling causes gate-oxide thickness is becoming
as thin as about 2-nm, which means reaching the thickness of
several SiO2 atoms. In this situation, the gate leakage would
dominant in comparison with the off-current leakage of tran-
sistor. Considering this, high-k dielectrics for MOSFET appli-
cations has become a suitable solution. It has been reported
that for the same equivalent oxide thickness, the MOSFET
with high-k dielectric has more than four orders of magnitude
less than gate leakage of transistor which gate oxide made
from SiO2 [27]. Therefore, we have inserted a change in the
proposed MOSFET architecture to include 2-nm HfO2 film to
reduce gate leakage and benefit other advantages which is
mentioned in the previous section.
By transistor shrinkage, because of increment of internal
electric field scaling of the power supply voltage is inevitable.
This means that the power generated by the chip, which is
define as Eq. (7) need to decrease [27]:
Fig. 9 Effect of BOX thickness
variation on threshold voltage and
sub-threshold slope (a) and DIBL
(b) of R-U-UTBBUTBB SOI-
MOSFET
Silicon
P ¼ C:V2 :f þ Ioff :V ð7Þ
where f is the frequency, C is the gate-oxide capacitance, and
Ioff is the total leakage current. It is concluded from this equa-
tion that reducing V has a significant effect on power. Scaling
the power supply voltage, reducing threshold voltage.
However, Ioff will increase as a result of decreasing threshold
voltage, which the off-state power will increase, so there is
trade-off in this case.
For an ideal device working as a switch, the off current is
ideally zero. But when MOSFETs is used as switches, it is
very small and equal to current passing in the transistor when
Vg = 0 V and Vds = VDD. The Ioff is simulated and summarized
in Table 3 for the C-UTBB, U-UTBB, and R-U-UTBB SOI-
MOSFETs. As the transistor is scaled down, due to short
channel effects the off current increases. For having high per-
formance device, on to off current is defined as a figure of
merit and try to maximize the Ion/Ioff ratio to drop static power
losses. Figure 7 shows Ion/Ioff ratio of the C-UTBB, U-UTBB,
and R-U-UTBB devices versus gate length which outstanding
enhancement of novel device is considerable.
3.4 Threshold Voltage Roll-off
The relationship between threshold voltage and gate
length of a MOSFET is traditionally threshold voltage
roll-off’ which is used to measure the short channel
effects. Therefore, for different gate lengths, the electri-
cal characteristics of the transistor vary. An ideal device
should have electrical parameters that are insensitive
against geometry fluctuations. As shown in Fig. 8.,
threshold voltage roll-off’ of R-U-UTBB SOI-MOSFET
has improved 46% compared to the U-UTBB and the
C-UTBB devices. For larger gate lengths three devices
have shown a rather constant threshold voltage, but for
shorter channel lengths the slope of the threshold volt-
age curve is increased. The R-U-UTBB device also
shows a much better threshold voltage roll-off for
shorter channel lengths because of its longer effective
gate length. The simulation results of threshold voltage
Silicon
Fig. 10 Effect of SOI thickness
variation on threshold voltage and
sub-threshold slope (a) and DIBL
(b) of R-U-UTBB UTBB SOI-
MOSFET
roll-off UTBB SOI-MOSFETs are documented at 16-nm
gate length in Table 3.
3.5 Process-Induced Variations
Due to variations during the device fabrication process, the
geometry and different parameters of the R-U-UTBB SOI-
MOSFET are subject to uncertainties. Process-induced varia-
tions have investigated by studying the effect of buried oxide
thickness (TBOX), top silicon thickness (TSOI), channel thick-
ness (Tch), substrate doping, and oxide thickness (Tox) on
threshold voltage, sub-threshold slope, and DIBL.
Figure 9(a) shows the effect of BOX thickness variation from
10 to 30-nm on threshold voltage and sub-threshold slope of
R-U-UTBB device. However sub-threshold slope become al-
most unchanged for thicknesses more than 20-nm, but thresh-
old voltage is decreasing constantly due to reducing effect of
substrate acceptor dopant. The minimum value of DIBL occur
at BOX thickness of 20-nm as demonstrate in Fig. 9(b), while
for thin BOX it has significant increase.
Figure 10(a) and (b) shows the effect of silicon film varia-
tion on threshold voltage, sub-threshold slope, and DIBL, re-
spectively, which has minor impact on them compared with
other parameters. As shown in Fig. 10(b), the minimum value
of DIBL belong to SOI thickness of 16-nm and is about
80 mV/V.
The next geometry parameter of novel device is
channel thickness which has been changed from 2 to
Fig. 11 Effect of channel
thickness variation on threshold
voltage and sub-threshold slope
(a) and DIBL (b) of the R-U-
UTBB SOI-MOSFET
7-nm with a step of 1-nm. As shown in Fig. 11(a),
despite the gradually increase and decrease, respectively
in the threshold voltage and the sub-threshold slop,
DIBL behavior in Fig. 11(b) is different. Because of
Quantum effects [15] and strongly dependence of
SCEs on the body thickness for UTBB SOI-MOSFETs
[5], the amount of DIBL has increased at channel thick-
nesses less than 4 nm. On the other hand, as the chan-
nel thickens, due to deviation of the structure from U-
shape and thus reducing the effect of channel separation
in U-channel device [16], a significant increment on
DIBL has been occurred. Therefore, in the simulation
results of 4 nm channel thickness, the lowest value of
DIBL has been observed.
However, the ballistic transport has ignored in simulations.
It has reported in a 30-nm gate of UTBB MOSFET, about
20% of electrons arriving to the drain terminal are ballistic.
Moreover, it is to be emphasized that the requirement of an
un-doped channel will increase this value [19].
To reduce the doping concentration of channel and as
a result the Vth variations in the UTBB SOI-MOSFET,
high-impurity-concentration substrate has been proposed
[25]. The effect of this parameter variation on threshold
voltage, sub-threshold slope, and DIBL has been inves-
tigated for both donor and acceptor dopant of substrate
and present measured data in Fig. 12(a), (b), and (c). As
shown in these figures, if the substrate dopes with donor
dopant with density of 1015 atom/cm3, 48 mV/V will be
 Silicon

Fig. 12 Effect of substrate doping

variation (donor and acceptor) on
threshold voltage (a), sub-
threshold slope (b), and DIBL (c)
of the R-U-UTBB SOI-MOSFET

brought for DIBL, 72 mV/dec. for subthreshold slope 4 Conclusion

and 0.19 V for threshold voltage, which is the best re-
sults among all the parameter variations without biasing
the substrate.
For the last variation, Tox (SiO2 and HfO2) is changed
from 21 Å to 39 Å and measured results of threshold volt-
age, sub-threshold slope and DIBL have plotted in
Fig. 13(a) and (b), respectively. The proposed device is
more sensitive to this variation than other parameter varia-
tions as illustrated in Fig. 13. To sum up sensitivity of
threshold voltage, sub-threshold slope, and DIBL of the
proposed structure, the six parameters which are investigat-
ed latterly are fluctuated ±20% and revealed its results in a
bar graph on Fig. 14.
In this paper a proposed approach for more scaling has pre-
sented by reforming the U-channel ultra-thin body and bur-
ied oxide (UTBB) SOI MOSFET. The simulation results
have been declared that if the substrate of proposed struc-
ture was doped by donor dopant, it offers enhancement in
short channel effects (SCEs) such as 50% decrement in
DIBL, 10% in sub-threshold slope, and 45% in threshold
voltage roll-off in comparison with the U-channel structure.
Also, by reaching threshold voltage to 0.19 V, VDD can be
scaled to 0.8 V. Moreover, the value of Ion/Ioff ratio has
quadrupled as a figure of merit for having high performance
device. So this device can be an excellent candidate for

Fig. 13 Effect of gate oxide

thickness variation on threshold
voltage and sub-threshold slope
(a) and DIBL (b) of the R-U-
UTBB SOI-MOSFET
Silicon
Fig. 14 Threshold voltage, sub-threshold slope and DIBL fluctuation of
the R-U-UTBB SOI-MOSFET due to various parameter variations at gate
length of 16-nm
digital and mobile application due to low power consump-
tion and high switching speed.
Author Contributions Conceptualization, Methodology, Formal analysis
and investigation, and Writing - original draft preparation: [Moslem
Ghassemi].
Writing - review and editing, Funding acquisition, Resources, and
Supervision: [Ali A. Orouji].
Data Availability The data that support the findings of this study are
openly available at http:// www.silvaco.com, reference number [31].
Compliance with Ethical Standards
Conflict of Interest The Authors declare that there is no conflict of
interest.
Ethical Approval This article does not contain any studies with human
participants or animals performed by any of the authors.
Informed Consent Informed consent was obtained from all individual
participants involved in the study.
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